* interp.c (sim_fetch_register): Convert internal r5900 regs to

target byte order

diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index 7900ebabb6dda2c9859abe50bd137ce310d8f7ca..2afcd498ceae6d10df74c6498ba9c73f9fbca453 100644 (file)
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,10 @@
+start-sanitize-r5900
+Thu May 21 17:15:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
+
+       * interp.c (sim_fetch_register): Convert internal r5900 regs to
+       target byte order
+       
+end-sanitize-r5900
 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
 
        * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
@@ -35,11 +42,13 @@ Wed May 13 14:27:53 1998  Gavin Koch  <gavin@cygnus.com>
        function check_op_hilo_hi1lo1 with the pair 
        check_mult_hilo_hi1lo1 and check_mult_hilo_hi1lo1.
 
+start-sanitize-r5900
 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
 
        * tx.igen (madd,maddu):  Replace calls to check_op_hilo
        with calls to check_div_hilo.
 
+end-sanitize-r5900
 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
 
        * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):

diff --git a/sim/mips/interp.c b/sim/mips/interp.c
index f83fdc3a31b8da3f9b404cceeca5e3337385e051..e0c878d676325ffa61de4e605af1d3b37b88148b 100644 (file)
--- a/sim/mips/interp.c
+++ b/sim/mips/interp.c
@@ -1017,7 +1017,7 @@ sim_fetch_register (sd,rn,memory,length)
   /* start-sanitize-r5900 */
   if (rn >= 90 && rn < 90 + 32)
     {
-      *(unsigned64*)memory = GPR1[rn - 90];
+      *((unsigned64*)memory) = H2T_8 (GPR1[rn - 90]);
       return 8;
     }
   switch (rn)