[AArch64] Add zero_extend variants of logical+not ops

	* config/aarch64/aarch64.md (*<NLOGICAL:optab>_one_cmplsidi3_ze):
	New pattern.
	(*xor_one_cmplsidi3_ze): Likewise.

From-SVN: r222263

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 73ede9eada0b098bc894d2194fb470b52407280e..2a982b1bd7f0fe0eb96c86e5e5af17366ad4f5c0 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2015-04-21  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * config/aarch64/aarch64.md (*<NLOGICAL:optab>_one_cmplsidi3_ze):
+       New pattern.
+       (*xor_one_cmplsidi3_ze): Likewise.
+
 2015-04-21  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 
        * df-core.c (df_finish_pass): Iterate over df->problems_by_index[] and

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 534a862b4adbab9b9e2dce938850089e99875359..429c5bac00078b1b3d751518f0f4b0e488a9d338 100644 (file)
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -3058,6 +3058,26 @@
    (set_attr "simd" "*,yes")]
 )
 
+(define_insn "*<NLOGICAL:optab>_one_cmplsidi3_ze"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+       (zero_extend:DI
+         (NLOGICAL:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
+                      (match_operand:SI 2 "register_operand" "r"))))]
+  ""
+  "<NLOGICAL:nlogical>\\t%w0, %w2, %w1"
+  [(set_attr "type" "logic_reg")]
+)
+
+(define_insn "*xor_one_cmplsidi3_ze"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (zero_extend:DI
+          (not:SI (xor:SI (match_operand:SI 1 "register_operand" "r")
+                          (match_operand:SI 2 "register_operand" "r")))))]
+  ""
+  "eon\\t%w0, %w1, %w2"
+  [(set_attr "type" "logic_reg")]
+)
+
 ;; (xor (not a) b) is simplify_rtx-ed down to (not (xor a b)).
 ;; eon does not operate on SIMD registers so the vector variant must be split.
 (define_insn_and_split "*xor_one_cmpl<mode>3"