mem: Replace EventWrapper use with EventFunctionWrapper

NOTE: With this change there is a possibility for `DRAMCtrl::Rank`s
event names to not properly match the rank they were generated by. This
could occur if the public rank member is modified after the Rank's
construction. A patch would mean refactoring Rank and `DRAMCtrl`b to
privatize many of the members of Rank behind getters.

Change-Id: I7b8bd15086f4ffdfd3f40be4aeddac5e786fd78e
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3745
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc
index a7adcba64383e2e2cc102c7212c67f67eca7a173..0c9e2c15a09c7d4736557d9b47d28eb43cbc653a 100644 (file)
--- a/src/mem/bridge.cc
+++ b/src/mem/bridge.cc
@@ -61,8 +61,8 @@ Bridge::BridgeSlavePort::BridgeSlavePort(const std::string& _name,
                                          std::vector<AddrRange> _ranges)
     : SlavePort(_name, &_bridge), bridge(_bridge), masterPort(_masterPort),
       delay(_delay), ranges(_ranges.begin(), _ranges.end()),
-      outstandingResponses(0), retryReq(false),
-      respQueueLimit(_resp_limit), sendEvent(*this)
+      outstandingResponses(0), retryReq(false), respQueueLimit(_resp_limit),
+      sendEvent([this]{ trySendTiming(); }, _name)
 {
 }
 
@@ -71,7 +71,8 @@ Bridge::BridgeMasterPort::BridgeMasterPort(const std::string& _name,
                                            BridgeSlavePort& _slavePort,
                                            Cycles _delay, int _req_limit)
     : MasterPort(_name, &_bridge), bridge(_bridge), slavePort(_slavePort),
-      delay(_delay), reqQueueLimit(_req_limit), sendEvent(*this)
+      delay(_delay), reqQueueLimit(_req_limit),
+      sendEvent([this]{ trySendTiming(); }, _name)
 {
 }
 

diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh
index ad3585997e240a424d3f626df23abd93134a3db9..f2cc44501f46b5e90b9e4f16dbf1f70eca39e728 100644 (file)
--- a/src/mem/bridge.hh
+++ b/src/mem/bridge.hh
@@ -156,8 +156,7 @@ class Bridge : public MemObject
         void trySendTiming();
 
         /** Send event for the response queue. */
-        EventWrapper<BridgeSlavePort,
-                     &BridgeSlavePort::trySendTiming> sendEvent;
+        EventFunctionWrapper sendEvent;
 
       public:
 
@@ -255,8 +254,7 @@ class Bridge : public MemObject
         void trySendTiming();
 
         /** Send event for the request queue. */
-        EventWrapper<BridgeMasterPort,
-                     &BridgeMasterPort::trySendTiming> sendEvent;
+        EventFunctionWrapper sendEvent;
 
       public:
 

diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 7f08d173e0bd6968d927bf8ac43a03d0ca2fb8c9..6f25323712b1eeb4610d4806ff5d73340dba6ce6 100644 (file)
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -62,7 +62,8 @@ BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name,
                                           BaseCache *_cache,
                                           const std::string &_label)
     : QueuedSlavePort(_name, _cache, queue), queue(*_cache, *this, _label),
-      blocked(false), mustSendRetry(false), sendRetryEvent(this)
+      blocked(false), mustSendRetry(false),
+      sendRetryEvent([this]{ processSendRetry(); }, _name)
 {
 }
 

diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 2787eea8c8d0c374dd6b12048191f2cd2ada5362..2f4b934b341001cbdac0050631f152fdf0cf1f08 100644 (file)
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -177,8 +177,7 @@ class BaseCache : public MemObject
 
         void processSendRetry();
 
-        EventWrapper<CacheSlavePort,
-                     &CacheSlavePort::processSendRetry> sendRetryEvent;
+        EventFunctionWrapper sendRetryEvent;
 
     };
 

diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 09148100eec968b91ff2c8b29ce039e3475ff317..fdc14a7c0d1e13510d6bab7f2058266fc5e1e06c 100644 (file)
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -73,7 +73,8 @@ Cache::Cache(const CacheParams *p)
       clusivity(p->clusivity),
       writebackClean(p->writeback_clean),
       tempBlockWriteback(nullptr),
-      writebackTempBlockAtomicEvent(this, false,
+      writebackTempBlockAtomicEvent([this]{ writebackTempBlockAtomic(); },
+                                    name(), false,
                                     EventBase::Delayed_Writeback_Pri)
 {
     tempBlock = new CacheBlk();

diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index e5c8ab61f581acd59995746a59140ffbb83ccfaa..9d135c652a52c04d7609049e55bdb87275c52118 100644 (file)
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -257,8 +257,7 @@ class Cache : public BaseCache
      * finishes. To avoid other calls to recvAtomic getting in
      * between, we create this event with a higher priority.
      */
-    EventWrapper<Cache, &Cache::writebackTempBlockAtomic> \
-        writebackTempBlockAtomicEvent;
+    EventFunctionWrapper writebackTempBlockAtomicEvent;
 
     /**
      * Store the outstanding requests that we are expecting snoop

diff --git a/src/mem/comm_monitor.cc b/src/mem/comm_monitor.cc
index 0914f34bbf0853cb823d7bb2454e3f089741ee6e..354f66092e0afcd3122b5b460e4919bb49bd5d69 100644 (file)
--- a/src/mem/comm_monitor.cc
+++ b/src/mem/comm_monitor.cc
@@ -52,7 +52,7 @@ CommMonitor::CommMonitor(Params* params)
     : MemObject(params),
       masterPort(name() + "-master", *this),
       slavePort(name() + "-slave", *this),
-      samplePeriodicEvent(this),
+      samplePeriodicEvent([this]{ samplePeriodic(); }, name()),
       samplePeriodTicks(params->sample_period),
       samplePeriod(params->sample_period / SimClock::Float::s),
       stats(params)

diff --git a/src/mem/comm_monitor.hh b/src/mem/comm_monitor.hh
index fa28eaee438626289f0f8ba31fc421d505855811..d27594d232f0f158dde263c0b2a0566892ebbf1d 100644 (file)
--- a/src/mem/comm_monitor.hh
+++ b/src/mem/comm_monitor.hh
@@ -410,7 +410,7 @@ class CommMonitor : public MemObject
     void samplePeriodic();
 
     /** Periodic event called at the end of each simulation time bin */
-    EventWrapper<CommMonitor, &CommMonitor::samplePeriodic> samplePeriodicEvent;
+    EventFunctionWrapper samplePeriodicEvent;
 
     /**
      *@{

diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc
index 9e5c00b0e3a4eaf8be6d01e6cf5e74c679b2f029..da494a1d23313f6dfb5a1aeb6032e7aeb48c93e6 100644 (file)
--- a/src/mem/dram_ctrl.cc
+++ b/src/mem/dram_ctrl.cc
@@ -63,7 +63,8 @@ DRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) :
     retryRdReq(false), retryWrReq(false),
     busState(READ),
     busStateNext(READ),
-    nextReqEvent(this), respondEvent(this),
+    nextReqEvent([this]{ processNextReqEvent(); }, name()),
+    respondEvent([this]{ processRespondEvent(); }, name()),
     deviceSize(p->device_size),
     deviceBusWidth(p->device_bus_width), burstLength(p->burst_length),
     deviceRowBufferSize(p->device_rowbuffer_size),
@@ -1610,8 +1611,12 @@ DRAMCtrl::Rank::Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p, int rank)
       readEntries(0), writeEntries(0), outstandingEvents(0),
       wakeUpAllowedAt(0), power(_p, false), banks(_p->banks_per_rank),
       numBanksActive(0), actTicks(_p->activation_limit, 0),
-      writeDoneEvent(*this), activateEvent(*this), prechargeEvent(*this),
-      refreshEvent(*this), powerEvent(*this), wakeUpEvent(*this)
+      writeDoneEvent([this]{ processWriteDoneEvent(); }, name()),
+      activateEvent([this]{ processActivateEvent(); }, name()),
+      prechargeEvent([this]{ processPrechargeEvent(); }, name()),
+      refreshEvent([this]{ processRefreshEvent(); }, name()),
+      powerEvent([this]{ processPowerEvent(); }, name()),
+      wakeUpEvent([this]{ processWakeUpEvent(); }, name())
 {
     for (int b = 0; b < _p->banks_per_rank; b++) {
         banks[b].bank = b;

diff --git a/src/mem/dram_ctrl.hh b/src/mem/dram_ctrl.hh
index 1883041ccc4e4bb5256d0b64caec7901466dfba8..226897b7ea1ab7957003c6123dd22f05dddf12bf 100644 (file)
--- a/src/mem/dram_ctrl.hh
+++ b/src/mem/dram_ctrl.hh
@@ -556,28 +556,22 @@ class DRAMCtrl : public AbstractMemory
         void scheduleWakeUpEvent(Tick exit_delay);
 
         void processWriteDoneEvent();
-        EventWrapper<Rank, &Rank::processWriteDoneEvent>
-        writeDoneEvent;
+        EventFunctionWrapper writeDoneEvent;
 
         void processActivateEvent();
-        EventWrapper<Rank, &Rank::processActivateEvent>
-        activateEvent;
+        EventFunctionWrapper activateEvent;
 
         void processPrechargeEvent();
-        EventWrapper<Rank, &Rank::processPrechargeEvent>
-        prechargeEvent;
+        EventFunctionWrapper prechargeEvent;
 
         void processRefreshEvent();
-        EventWrapper<Rank, &Rank::processRefreshEvent>
-        refreshEvent;
+        EventFunctionWrapper refreshEvent;
 
         void processPowerEvent();
-        EventWrapper<Rank, &Rank::processPowerEvent>
-        powerEvent;
+        EventFunctionWrapper powerEvent;
 
         void processWakeUpEvent();
-        EventWrapper<Rank, &Rank::processWakeUpEvent>
-        wakeUpEvent;
+        EventFunctionWrapper wakeUpEvent;
 
     };
 
@@ -685,10 +679,10 @@ class DRAMCtrl : public AbstractMemory
      * in these methods
      */
     void processNextReqEvent();
-    EventWrapper<DRAMCtrl,&DRAMCtrl::processNextReqEvent> nextReqEvent;
+    EventFunctionWrapper nextReqEvent;
 
     void processRespondEvent();
-    EventWrapper<DRAMCtrl, &DRAMCtrl::processRespondEvent> respondEvent;
+    EventFunctionWrapper respondEvent;
 
     /**
      * Check if the read queue has room for more entries

diff --git a/src/mem/dramsim2.cc b/src/mem/dramsim2.cc
index 106ea264fd4cd795d6059bd5cfae1c595f32d608..b900d4df07d71769b7251e6ee5e9855e2707769c 100644 (file)
--- a/src/mem/dramsim2.cc
+++ b/src/mem/dramsim2.cc
@@ -53,7 +53,8 @@ DRAMSim2::DRAMSim2(const Params* p) :
             p->traceFile, p->range.size() / 1024 / 1024, p->enableDebug),
     retryReq(false), retryResp(false), startTick(0),
     nbrOutstandingReads(0), nbrOutstandingWrites(0),
-    sendResponseEvent(this), tickEvent(this)
+    sendResponseEvent([this]{ sendResponse(); }, name()),
+    tickEvent([this]{ tick(); }, name())
 {
     DPRINTF(DRAMSim2,
             "Instantiated DRAMSim2 with clock %d ns and queue size %d\n",

diff --git a/src/mem/dramsim2.hh b/src/mem/dramsim2.hh
index 5cde19cd87af59e2810f75e4239ba22413faaba8..6444f75d646a7b30d596f9e1ec5808cf229495f3 100644 (file)
--- a/src/mem/dramsim2.hh
+++ b/src/mem/dramsim2.hh
@@ -148,7 +148,7 @@ class DRAMSim2 : public AbstractMemory
     /**
      * Event to schedule sending of responses
      */
-    EventWrapper<DRAMSim2, &DRAMSim2::sendResponse> sendResponseEvent;
+    EventFunctionWrapper sendResponseEvent;
 
     /**
      * Progress the controller one clock cycle.
@@ -158,7 +158,7 @@ class DRAMSim2 : public AbstractMemory
     /**
      * Event to schedule clock ticks
      */
-    EventWrapper<DRAMSim2, &DRAMSim2::tick> tickEvent;
+    EventFunctionWrapper tickEvent;
 
     /**
      * Upstream caches need this packet until true is returned, so

diff --git a/src/mem/serial_link.cc b/src/mem/serial_link.cc
index ee21163b741d88954441015b5d173245b7096bdc..97563c0d0838c33abe7d3102ea569912ac7350f5 100644 (file)
--- a/src/mem/serial_link.cc
+++ b/src/mem/serial_link.cc
@@ -66,7 +66,8 @@ SerialLink::SerialLinkSlavePort::SerialLinkSlavePort(const std::string& _name,
       masterPort(_masterPort), delay(_delay),
       ranges(_ranges.begin(), _ranges.end()),
       outstandingResponses(0), retryReq(false),
-      respQueueLimit(_resp_limit), sendEvent(*this)
+      respQueueLimit(_resp_limit),
+      sendEvent([this]{ trySendTiming(); }, _name)
 {
 }
 
@@ -76,7 +77,7 @@ SerialLink::SerialLinkMasterPort::SerialLinkMasterPort(const std::string&
                                            Cycles _delay, int _req_limit)
     : MasterPort(_name, &_serial_link), serial_link(_serial_link),
       slavePort(_slavePort), delay(_delay), reqQueueLimit(_req_limit),
-      sendEvent(*this)
+      sendEvent([this]{ trySendTiming(); }, _name)
 {
 }
 

diff --git a/src/mem/serial_link.hh b/src/mem/serial_link.hh
index 9fbcce335dcf3978f2fdaee0a8d2095b7cfb7923..64f262d0f6f69873289f85981ea8d17d9d22a5ee 100644 (file)
--- a/src/mem/serial_link.hh
+++ b/src/mem/serial_link.hh
@@ -146,8 +146,7 @@ class SerialLink : public MemObject
         void trySendTiming();
 
         /** Send event for the response queue. */
-        EventWrapper<SerialLinkSlavePort,
-                     &SerialLinkSlavePort::trySendTiming> sendEvent;
+        EventFunctionWrapper sendEvent;
 
       public:
 
@@ -247,8 +246,7 @@ class SerialLink : public MemObject
         void trySendTiming();
 
         /** Send event for the request queue. */
-        EventWrapper<SerialLinkMasterPort,
-                     &SerialLinkMasterPort::trySendTiming> sendEvent;
+        EventFunctionWrapper sendEvent;
 
       public:
 

diff --git a/src/mem/simple_mem.cc b/src/mem/simple_mem.cc
index f524d01abad720a52c3574ab006a3369f24dc8b4..8358a828b1b0e77741b51232b073bb5e34e2c15d 100644 (file)
--- a/src/mem/simple_mem.cc
+++ b/src/mem/simple_mem.cc
@@ -55,7 +55,8 @@ SimpleMemory::SimpleMemory(const SimpleMemoryParams* p) :
     port(name() + ".port", *this), latency(p->latency),
     latency_var(p->latency_var), bandwidth(p->bandwidth), isBusy(false),
     retryReq(false), retryResp(false),
-    releaseEvent(this), dequeueEvent(this)
+    releaseEvent([this]{ release(); }, name()),
+    dequeueEvent([this]{ dequeue(); }, name())
 {
 }
 

diff --git a/src/mem/simple_mem.hh b/src/mem/simple_mem.hh
index 23cd3c80d3c5bb9aced69524c68656905dd8787d..6636f2c9062685d5e7a98692fc81823172ae2563 100644 (file)
--- a/src/mem/simple_mem.hh
+++ b/src/mem/simple_mem.hh
@@ -158,7 +158,7 @@ class SimpleMemory : public AbstractMemory
      */
     void release();
 
-    EventWrapper<SimpleMemory, &SimpleMemory::release> releaseEvent;
+    EventFunctionWrapper releaseEvent;
 
     /**
      * Dequeue a packet from our internal packet queue and move it to
@@ -166,7 +166,7 @@ class SimpleMemory : public AbstractMemory
      */
     void dequeue();
 
-    EventWrapper<SimpleMemory, &SimpleMemory::dequeue> dequeueEvent;
+    EventFunctionWrapper dequeueEvent;
 
     /**
      * Detemine the latency.

diff --git a/src/mem/xbar.cc b/src/mem/xbar.cc
index 03546194413420677d291879c1cef4e7242dbf2e..b7826fd25bc5935843472f6a6861e25a965ec315 100644 (file)
--- a/src/mem/xbar.cc
+++ b/src/mem/xbar.cc
@@ -147,7 +147,7 @@ template <typename SrcType, typename DstType>
 BaseXBar::Layer<SrcType,DstType>::Layer(DstType& _port, BaseXBar& _xbar,
                                        const std::string& _name) :
     port(_port), xbar(_xbar), _name(_name), state(IDLE),
-    waitingForPeer(NULL), releaseEvent(this)
+    waitingForPeer(NULL), releaseEvent([this]{ releaseLayer(); }, name())
 {
 }
 

diff --git a/src/mem/xbar.hh b/src/mem/xbar.hh
index c9949e3642b092eccca073db25ad2c135a6badda..f826e142acdab03bcdc2fd5f0af75901b961d7fe 100644 (file)
--- a/src/mem/xbar.hh
+++ b/src/mem/xbar.hh
@@ -237,7 +237,7 @@ class BaseXBar : public MemObject
         void releaseLayer();
 
         /** event used to schedule a release of the layer */
-        EventWrapper<Layer, &Layer::releaseLayer> releaseEvent;
+        EventFunctionWrapper releaseEvent;
 
         /**
          * Stats for occupancy and utilization. These stats capture