Progress on presentation
authorClifford Wolf <clifford@clifford.at>
Tue, 28 Jan 2014 05:51:50 +0000 (06:51 +0100)
committerClifford Wolf <clifford@clifford.at>
Tue, 28 Jan 2014 05:51:50 +0000 (06:51 +0100)
manual/PRESENTATION_Intro.tex
manual/presentation.tex

index e243da88ef6f91aa6dbf287ebc38e69c84f0ccd7..9fbcd4cb38c3e882946fae447d2efacfcbb27185 100644 (file)
@@ -5,6 +5,8 @@
 \sectionpage
 \end{frame}
 
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+
 \subsection{Representations of (digital) Circuits}
 
 \begin{frame}[t]{\subsecname}
        \item Non-graphical
                \begin{itemize}
                        \item \alert<3>{Netlists}
-                       \item \alert<4>{Hardware Description Language}
+                       \item \alert<4>{Hardware Description Languages (HDLs)}
                \end{itemize}
 \end{itemize}
 \bigskip
-\begin{block}{Definition}
-       \only<1>{Schematic Diagrams are ... TBD}
-       \only<2>{Physical Layouts are ... TBD}
-       \only<3>{Netlists are ... TBD}
-       \only<4>{Hardware Description Languages are ... TBD}
+\begin{block}{Definition:
+\only<1>{Schematic Diagram}%
+\only<2>{Physical Layout}%
+\only<3>{Netlists}%
+\only<4>{Hardware Description Languages (HDLs)}}
+       \only<1>{TBD}
+       \only<2>{TBD}
+       \only<3>{TBD}
+       \only<4>{TBD}
 \end{block}
 \end{frame}
 
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
 \subsection{Levels of Abstraction for Digital Circuits}
 
 \end{block}
 \end{frame}
 
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
 \subsection{Digital Circuit Synthesis}
 
 \begin{frame}{\subsecname}
 \end{frame}
 
-
index bd1e7c6a4ac20b488e4e40f348870b6cf4f62c45..efdc1cc93acdfb5587873b15a622bfc530a9eb78 100644 (file)
@@ -1,5 +1,55 @@
 \documentclass{beamer}
 
+\usepackage[T1]{fontenc}   % required for luximono!
+\usepackage{lmodern}
+\usepackage[scaled=0.8]{luximono}  % typewriter font with bold face
+
+% To install the luximono font files:
+% getnonfreefonts-sys --all        or
+% getnonfreefonts-sys luximono
+%
+% when there are trouble you might need to:
+% - Create /etc/texmf/updmap.d/99local-luximono.cfg
+%   containing the single line: Map ul9.map
+% - Run update-updmap followed by mktexlsr and updmap-sys
+%
+% This commands must be executed as root with a root environment
+% (i.e. run "sudo su" and then execute the commands in the root
+% shell, don't just prefix the commands with "sudo").
+
+% formats the text accourding the set language
+\usepackage[english]{babel}
+\usepackage{amsmath}
+\usepackage{multirow}
+\usepackage{booktabs}
+\usepackage{listings}
+\usepackage{skull}
+
+\usepackage{tikz}
+\usetikzlibrary{calc}
+\usetikzlibrary{arrows}
+\usetikzlibrary{scopes}
+\usetikzlibrary{through}
+\usetikzlibrary{shapes.geometric}
+
+\lstset{basicstyle=\ttfamily}
+
+\def\B#1{{\tt\textbackslash{}#1}}
+\def\C#1{\lstinline[language=C++]{#1}}
+\def\V#1{\lstinline[language=Verilog]{#1}}
+
+\lstdefinelanguage{liberty}{
+       morecomment=[s]{/*}{*/},
+       morekeywords={library,cell,area,pin,direction,function,clocked_on,next_state,clock,ff},
+       morestring=[b]",
+}
+
+\lstdefinelanguage{rtlil}{
+       morecomment=[l]{\#},
+       morekeywords={module,attribute,parameter,wire,memory,auto,width,offset,size,input,output,inout,cell,connect,switch,case,assign,sync,low,high,posedge,negedge,edge,always,update,process,end},
+       morestring=[b]",
+}
+
 \title{Yosys Open SYnthesis Suite}
 \author{Clifford Wolf}
 \institute{http://www.clifford.at/}
 \titlepage
 \end{frame}
 
-\begin{frame}{Overview}
+\setcounter{section}{-1}
+\section{Outline}
+
+\begin{frame}{Outline}
 Yosys is an Open Source Verilog synthesis tool, and more.
 
 \bigskip
@@ -29,6 +82,7 @@ Outline of this presentation:
 \begin{itemize}
 \item Introduction to the field and Yosys
 \item Yosys usage examples (synthesis)
+\item Yosys usage examples (advanced synthesis)
 \item Yosys usage examples (beyond synthesis)
 \item Programming Yosys extensions
 \end{itemize}