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Update all boards to use default_rst.
authorwhitequark <whitequark@whitequark.org>
Sat, 3 Aug 2019 16:28:57 +0000 (16:28 +0000)
committerwhitequark <whitequark@whitequark.org>
Sat, 3 Aug 2019 16:28:57 +0000 (16:28 +0000)
This is pretty much just Versa ECP5 (5G).

nmigen_boards/versa_ecp5.py patch | blob | history

diff --git a/nmigen_boards/versa_ecp5.py b/nmigen_boards/versa_ecp5.py
index 4b2b9f0a1b0d757b843725d831d11e4d8d63f1d7..4462e4d8222516a7b9e6d54ec27b34e3f76a858c 100644 (file)
--- a/nmigen_boards/versa_ecp5.py
+++ b/nmigen_boards/versa_ecp5.py
@@ -14,6 +14,7 @@ class VersaECP5Platform(LatticeECP5Platform):
     package     = "BG381"
     speed       = "8"
     default_clk = "clk100"
+    default_rst = "rst"
     resources   = [
         Resource("rst", 0, PinsN("T1", dir="i"), Attrs(IO_TYPE="LVCMOS33")),
         Resource("clk100", 0, DiffPairs("P3", "P4", dir="i"),