[AArch64] Simplify+improve patterns for ushr(d?)_n_u64 intrinsic

gcc/:
	* config/aarch64/aarch64-simd.md (aarch64_lshr_simddi): Handle shift
	by 64 by moving const0_rtx.
	(aarch64_ushr_simddi): Delete.

	* config/aarch64/aarch64.md (enum unspec): Delete UNSPEC_USHR64.

gcc/testsuite/:

        * gcc.target/aarch64/ushr64_1.c: Remove scan-assembler "ushr...64".

From-SVN: r218868

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3bb1dae5d073686e53b0b60620f98e08cc313d43..1fd5b4f6f1a2ed0ebb811e1d0c191e6ad55cebde 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2014-12-18  Alan Lawrence  <alan.lawrence@arm.com>
+
+       * config/aarch64/aarch64-simd.md (aarch64_lshr_simddi): Handle shift
+       by 64 by moving const0_rtx.
+       (aarch64_ushr_simddi): Delete.
+
+       * config/aarch64/aarch64.md (enum unspec): Delete UNSPEC_USHR64.
+
 2014-12-18  Alan Lawrence  <alan.lawrence@arm.com>
 
        * config/aarch64/aarch64.md (enum "unspec"): Remove UNSPEC_SSHR64.

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 9a48537a33bc097051f9dd7095a816d5221259f0..52a1c3ba792adcaeaec9be4d8ada0f81bfa4714a 100644 (file)
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -756,24 +756,13 @@
   "TARGET_SIMD"
   {
     if (INTVAL (operands[2]) == 64)
-      emit_insn (gen_aarch64_ushr_simddi (operands[0], operands[1]));
+      emit_move_insn (operands[0], const0_rtx);
     else
       emit_insn (gen_lshrdi3 (operands[0], operands[1], operands[2]));
     DONE;
   }
 )
 
-;; SIMD shift by 64.  This pattern is a special case as standard pattern does
-;; not handle NEON shifts by 64.
-(define_insn "aarch64_ushr_simddi"
-  [(set (match_operand:DI 0 "register_operand" "=w")
-        (unspec:DI
-          [(match_operand:DI 1 "register_operand" "w")] UNSPEC_USHR64))]
-  "TARGET_SIMD"
-  "ushr\t%d0, %d1, 64"
-  [(set_attr "type" "neon_shift_imm")]
-)
-
 (define_expand "vec_set<mode>"
   [(match_operand:VDQ_BHSI 0 "register_operand")
    (match_operand:<VEL> 1 "register_operand")

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index ebde2768d30c80825645b0ab9ce9921e9ca730ab..12532c1675fa6e6a1e335be127ed3a8902e44b52 100644 (file)
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -117,7 +117,6 @@
     UNSPEC_TLS
     UNSPEC_TLSDESC
     UNSPEC_USHL_2S
-    UNSPEC_USHR64
     UNSPEC_VSTRUCTDUMMY
     UNSPEC_SP_SET
     UNSPEC_SP_TEST

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 025dfcead10ea6ba602f136ba0d558d5c08cb3b1..f7e72ed7a848c2933c3c10826b99fa267cf433a6 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2014-12-18  Alan Lawrence  <alan.lawrence@arm.com>
+
+       * gcc.target/aarch64/ushr64_1.c: Remove scan-assembler "ushr...64".
+
 2014-12-18  Martin Liska  <mliska@suse.cz>
 
        * g++.dg/ipa/pr64146.C: New test.

diff --git a/gcc/testsuite/gcc.target/aarch64/ushr64_1.c b/gcc/testsuite/gcc.target/aarch64/ushr64_1.c
index b1c741dac3125d97ca3440329ecb32c7d2889d81..ee494894f6fb6f9cb354d836121a7bc6d0d2cdb6 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/ushr64_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/ushr64_1.c
@@ -42,7 +42,6 @@ test_vshrd_n_u64_0 (uint64_t passed, uint64_t expected)
   return vshrd_n_u64 (passed, 0) != expected;
 }
 
-/* { dg-final { scan-assembler-times "ushr\\td\[0-9\]+, d\[0-9\]+, 64" 2 } } */
 /* { dg-final { (scan-assembler-times "ushr\\td\[0-9\]+, d\[0-9\]+, 4" 2)  || \
    (scan-assembler-times "lsr\\tx\[0-9\]+, x\[0-9\]+, 4" 2) } } */
 /* { dg-final { scan-assembler-not "ushr\\td\[0-9\]+, d\[0-9\]+, 0" } } */