Remove DDR4 modules

diff --git a/gram/modules.py b/gram/modules.py
index e481f33243f0e357034302e524efcd62c60028fd..635a5d418c1ea211cb9c3ae1ef1668cdbb9f3ae6 100644 (file)
--- a/gram/modules.py
+++ b/gram/modules.py
@@ -558,105 +558,3 @@ class MT16KTF1G64HZ(DDR3Module):
         "1866": _SpeedgradeTimings(tRP=13.125, tRCD=13.125, tWR=15, tRFC=(None, 260), tFAW=(None, 27), tRAS=34),
     }
     speedgrade_timings["default"] = speedgrade_timings["1866"]
-
-
-# DDR4 (Chips) -------------------------------------------------------------------------------------
-
-class DDR4Module(SDRAMModule):
-    memtype = "DDR4"
-
-
-class DDR4RegisteredModule(SDRAMRegisteredModule):
-    memtype = "DDR4"
-
-
-class EDY4016A(DDR4Module):
-    # geometry
-    ngroupbanks = 4
-    ngroups = 2
-    nbanks = ngroups * ngroupbanks
-    nrows = 32768
-    ncols = 1024
-    # timings
-    trefi = {"1x": 64e6/8192,   "2x": (64e6/8192)/2, "4x": (64e6/8192)/4}
-    trfc = {"1x": (None, 260), "2x": (None, 160),   "4x": (None, 110)}
-    technology_timings = _TechnologyTimings(tREFI=trefi, tWTR=(
-        4, 7.5), tCCD=(4, None), tRRD=(4, 4.9), tZQCS=(128, 80))
-    speedgrade_timings = {
-        "2400": _SpeedgradeTimings(tRP=13.32, tRCD=13.32, tWR=15, tRFC=trfc, tFAW=(28, 30), tRAS=32),
-    }
-    speedgrade_timings["default"] = speedgrade_timings["2400"]
-
-
-class MT40A1G8(DDR4Module):
-    # geometry
-    ngroupbanks = 4
-    ngroups = 4
-    nbanks = ngroups * ngroupbanks
-    nrows = 65536
-    ncols = 1024
-    # timings
-    trefi = {"1x": 64e6/8192,   "2x": (64e6/8192)/2, "4x": (64e6/8192)/4}
-    trfc = {"1x": (None, 350), "2x": (None, 260),   "4x": (None, 160)}
-    technology_timings = _TechnologyTimings(tREFI=trefi, tWTR=(
-        4, 7.5), tCCD=(4, None), tRRD=(4, 6.4), tZQCS=(128, 80))
-    speedgrade_timings = {
-        "2400": _SpeedgradeTimings(tRP=13.32, tRCD=13.32, tWR=15, tRFC=trfc, tFAW=(20, 25), tRAS=32),
-        "2666": _SpeedgradeTimings(tRP=13.50, tRCD=13.50, tWR=15, tRFC=trfc, tFAW=(20, 21), tRAS=32),
-    }
-    speedgrade_timings["default"] = speedgrade_timings["2400"]
-
-
-class MT40A256M16(DDR4Module):
-    # geometry
-    ngroupbanks = 4
-    ngroups = 2
-    nbanks = ngroups * ngroupbanks
-    nrows = 32768
-    ncols = 1024
-    # timings
-    trefi = {"1x": 64e6/8192, "2x": (64e6/8192)/2, "4x": (64e6/8192)/4}
-    trfc = {"1x": (None, 260), "2x": (None, 160), "4x": (None, 110)}
-    technology_timings = _TechnologyTimings(tREFI=trefi, tWTR=(
-        4, 7.5), tCCD=(4, None), tRRD=(4, 4.9), tZQCS=(128, 80))
-    speedgrade_timings = {
-        "2400": _SpeedgradeTimings(tRP=13.32, tRCD=13.32, tWR=15, tRFC=trfc, tFAW=(28, 35), tRAS=32),
-    }
-    speedgrade_timings["default"] = speedgrade_timings["2400"]
-
-
-class MT40A512M8(DDR4Module):
-    # geometry
-    ngroupbanks = 4
-    ngroups = 4
-    nbanks = ngroups * ngroupbanks
-    nrows = 32768
-    ncols = 1024
-    # timings
-    trefi = {"1x": 64e6/8192,   "2x": (64e6/8192)/2, "4x": (64e6/8192)/4}
-    trfc = {"1x": (None, 350), "2x": (None, 260),   "4x": (None, 160)}
-    technology_timings = _TechnologyTimings(tREFI=trefi, tWTR=(
-        4, 7.5), tCCD=(4, None), tRRD=(4, 4.9), tZQCS=(128, 80))
-    speedgrade_timings = {
-        "2400": _SpeedgradeTimings(tRP=13.32, tRCD=13.32, tWR=15, tRFC=trfc, tFAW=(20, 25), tRAS=32),
-        "2666": _SpeedgradeTimings(tRP=13.50, tRCD=13.50, tWR=15, tRFC=trfc, tFAW=(20, 21), tRAS=32),
-    }
-    speedgrade_timings["default"] = speedgrade_timings["2400"]
-
-
-class MT40A512M16(DDR4Module):
-    # geometry
-    ngroupbanks = 4
-    ngroups = 2
-    nbanks = ngroups * ngroupbanks
-    nrows = 65536
-    ncols = 1024
-    # timings
-    trefi = {"1x": 64e6/8192,   "2x": (64e6/8192)/2, "4x": (64e6/8192)/4}
-    trfc = {"1x": (None, 350), "2x": (None, 260),   "4x": (None, 160)}
-    technology_timings = _TechnologyTimings(tREFI=trefi, tWTR=(
-        4, 7.5), tCCD=(4, None), tRRD=(4, 4.9), tZQCS=(128, 80))
-    speedgrade_timings = {
-        "2400": _SpeedgradeTimings(tRP=13.32, tRCD=13.32, tWR=15, tRFC=trfc, tFAW=(20, 25), tRAS=32),
-    }
-    speedgrade_timings["default"] = speedgrade_timings["2400"]