[pk, sim] added FPU emulation support to proxy kernel

diff --git a/config.h.in b/config.h.in
index 0c3b9aa813446498f560f367e2aae54303234cf3..6ef883daeb65ffce3c91fa61cace1090bc2c6c47 100644 (file)
--- a/config.h.in
+++ b/config.h.in
@@ -21,6 +21,12 @@
 /* Define if subproject MCPPBS_SPROJ_NORM is enabled */
 #undef RISCV_ENABLED
 
+/* Define if 64-bit mode is supported */
+#undef RISCV_ENABLE_64BIT
+
+/* Define if floating-point instructions are supported */
+#undef RISCV_ENABLE_FPU
+
 /* Define if libopcodes exists */
 #undef RISCV_HAVE_LIBOPCODES
 

diff --git a/configure b/configure
index 30b9fc3e7439ba80c694a374c9dadc10a1133c61..82ea6a473ebec06c6eedb430a2d620def56a64da 100755 (executable)
--- a/configure
+++ b/configure
@@ -635,6 +635,8 @@ ac_user_opts='
 enable_option_checking
 enable_stow
 enable_optional_subprojects
+enable_fpu
+enable_64bit
 '
       ac_precious_vars='build_alias
 host_alias
@@ -1267,6 +1269,8 @@ Optional Features:
   --enable-stow           Enable stow-based install
   --enable-optional-subprojects
                           Enable all optional subprojects
+  --disable-fpu           Disable floating-point
+  --disable-64bit         Disable 64-bit mode
 
 Some influential environment variables:
   CC          C compiler command
@@ -4015,7 +4019,33 @@ $as_echo "$as_me: configuring default subproject : riscv" >&6;}
 
 $as_echo "#define RISCV_ENABLED /**/" >>confdefs.h
 
-      libopc=`dirname \`which riscv-gcc\``/../`$ac_config_guess`/riscv/lib/libopcodes.a
+      # Check whether --enable-fpu was given.
+if test "${enable_fpu+set}" = set; then :
+  enableval=$enable_fpu;
+fi
+
+if test "x$enable_fpu" != "xno"; then :
+
+
+$as_echo "#define RISCV_ENABLE_FPU /**/" >>confdefs.h
+
+
+fi
+
+# Check whether --enable-64bit was given.
+if test "${enable_64bit+set}" = set; then :
+  enableval=$enable_64bit;
+fi
+
+if test "x$enable_64bit" != "xno"; then :
+
+
+$as_echo "#define RISCV_ENABLE_64BIT /**/" >>confdefs.h
+
+
+fi
+
+libopc=`dirname \`which riscv-gcc\``/../`$ac_config_guess`/riscv/lib/libopcodes.a
 as_ac_File=`$as_echo "ac_cv_file_$libopc" | $as_tr_sh`
 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $libopc" >&5
 $as_echo_n "checking for $libopc... " >&6; }

diff --git a/riscv/decode.h b/riscv/decode.h
index 56157d3e4eb2a2018b2c726f8b64cfbe29b50ea4..810af3f07635d4cf3c275e9f28ada3850b8396d4 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -3,10 +3,25 @@
 
 #define __STDC_LIMIT_MACROS
 #include <stdint.h>
+
+#include "config.h"
+
+#ifdef RISCV_ENABLE_64BIT
+# define support_64bit 1
+#else
+# define support_64bit 0
+#endif
+
+#ifdef RISCV_ENABLE_FPU
+# define support_fp 1
+#else
+# define support_fp 0
+#endif
+
+
 typedef int int128_t __attribute__((mode(TI)));
 typedef unsigned int uint128_t __attribute__((mode(TI)));
 
-#define support_64bit 1
 typedef int64_t sreg_t;
 typedef uint64_t reg_t;
 typedef uint64_t freg_t;

diff --git a/riscv/execute.h b/riscv/execute.h
index 1a6e8ecf5e2706e2cddaa1ffad2101600081b0f4..bbd7e496f1a09b65e3b77f0707ba95f97ddca4e0 100644 (file)
--- a/riscv/execute.h
+++ b/riscv/execute.h
@@ -288,7 +288,7 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/sgninjn_d.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd4006ba0)
+        if((insn.bits & 0xfe007fe0) == 0xd4006f80)
         {
           #include "insns/mtflh_d.h"
           break;

diff --git a/riscv/processor.cc b/riscv/processor.cc
index b018347afa23b6eb5bb027d135ccb76700ec388c..a889f75ccc23f64cf1d1a5a29016ad5a31b011ce 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -51,6 +51,8 @@ void processor_t::set_sr(uint32_t val)
   sr = val & ~SR_ZERO;
   if(!support_64bit)
     sr &= ~(SR_SX | SR_UX);
+  if(!support_fp)
+    sr &= ~SR_EF;
 
   gprlen = ((sr & SR_S) ? (sr & SR_SX) : (sr & SR_UX)) ? 64 : 32;
 }

diff --git a/riscv/riscv.ac b/riscv/riscv.ac
index e6866c75dc16903f048c4b5b493ed840abf4a573..7898145098c70b75f829bf5b114a500051576ccf 100644 (file)
--- a/riscv/riscv.ac
+++ b/riscv/riscv.ac
@@ -1,3 +1,13 @@
+AC_ARG_ENABLE([fpu], AS_HELP_STRING([--disable-fpu], [Disable floating-point]))
+AS_IF([test "x$enable_fpu" != "xno"], [
+  AC_DEFINE([RISCV_ENABLE_FPU],,[Define if floating-point instructions are supported])
+])
+
+AC_ARG_ENABLE([64bit], AS_HELP_STRING([--disable-64bit], [Disable 64-bit mode]))
+AS_IF([test "x$enable_64bit" != "xno"], [
+  AC_DEFINE([RISCV_ENABLE_64BIT],,[Define if 64-bit mode is supported])
+])
+
 libopc=`dirname \`which riscv-gcc\``/../`$ac_config_guess`/riscv/lib/libopcodes.a
 AC_CHECK_FILES([$libopc],[have_libopcodes="yes"],[have_libopcodes="no"])