i965: Use MI_FLUSH_DW for blt ring flush on sandybridge

Old MI_FLUSH command is deprecated on sandybridge blt.

diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index 20574ab546247a1f3b64a3c9a6afc7d93963eb48..67ce8a4da026dcbda6d06aca81b34784c02da8bd 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -271,8 +271,11 @@ intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch)
 
    if (intel->gen >= 6) {
       if (intel->batch->is_blit) {
-        BEGIN_BATCH_BLT(1);
-        OUT_BATCH(MI_FLUSH);
+        BEGIN_BATCH_BLT(4);
+        OUT_BATCH(MI_FLUSH_DW);
+        OUT_BATCH(0);
+        OUT_BATCH(0);
+        OUT_BATCH(0);
         ADVANCE_BATCH();
       } else {
         BEGIN_BATCH(8);

diff --git a/src/mesa/drivers/dri/intel/intel_reg.h b/src/mesa/drivers/dri/intel/intel_reg.h
index 955b100b212e088b921badfebcd397665e42c434..5258699d3f948a71dbdbd4ed8265883dc33bbe46 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_reg.h
+++ b/src/mesa/drivers/dri/intel/intel_reg.h
@@ -37,6 +37,8 @@
 #define FLUSH_MAP_CACHE                                (1 << 0)
 #define INHIBIT_FLUSH_RENDER_CACHE             (1 << 2)
 
+#define MI_FLUSH_DW                    (CMD_MI | (0x26 << 23) | 2)
+
 /* Stalls command execution waiting for the given events to have occurred. */
 #define MI_WAIT_FOR_EVENT               (CMD_MI | (0x3 << 23))
 #define MI_WAIT_FOR_PLANE_B_FLIP        (1<<6)