Merge pull request #1359 from YosysHQ/xc7dsp
authorEddie Hung <eddie@fpgeh.com>
Sun, 29 Sep 2019 18:26:22 +0000 (11:26 -0700)
committerGitHub <noreply@github.com>
Sun, 29 Sep 2019 18:26:22 +0000 (11:26 -0700)
DSP inference for Xilinx (improved for ice40, initial support for ecp5)

1  2 
backends/aiger/xaiger.cc
techlibs/xilinx/abc_xc7.box
techlibs/xilinx/synth_xilinx.cc

Simple merge
Simple merge
Simple merge