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diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 22daccc61bce062c4113e9ab0e17ae4310eeed6d..a4980c339eb077e2246c3553cc6f4cc0a1908849 100644 (file)
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -226,6 +226,17 @@ However if elwidth overrides are set to 16 for both source and destination:
         int_regfile[RT].halfs[i] = int_regfile[RA].halfs[i] + int_regfile[RB].halfs[i]
 ```
 
+The most fundamental aspect here to understand is that the wrapping into
+subsequent Scalar GPRs that occurs on larger-numbered elements
+including and especially on smaller element widths is **deliberate and intentional**.
+From this Canonical definition it should be clear that sequential elements begin
+at the LSB end of any given underlying Scalar GPR, progress to the MSB end, and
+then to the LSB end of the *next numerically-larger Scalar GPR*.  In the
+example above if VL=5 and RT=1 then the contents of GPR(1) and GPR(2) will
+be as follows:
+
+
+
 Hardware Architectural note: to avoid a Read-Modify-Write at the register
 file it is strongly recommended to implement byte-level write-enable lines
 exactly as has been implemented in DRAM ICs for many decades. Additionally