Remove ANNULed cycle - was confusing gdb.

diff --git a/sim/tic80/ChangeLog b/sim/tic80/ChangeLog
index cbd7fcf67bf9ac973765aaae046aa4d91b38f9e1..c955fdcc7cad0f451891c7c999981a62fddb35b6 100644 (file)
--- a/sim/tic80/ChangeLog
+++ b/sim/tic80/ChangeLog
@@ -1,3 +1,15 @@
+Tue May 13 16:39:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+       * alu.h (IMEM): Take full cia not just IP as argument.
+
+       * interp.c (engine_run_until_stop): Delete handling of annuled
+       instructions.
+       (engine_step): Ditto.
+
+       * insn (do_branch): New function.
+       (do_bbo, do_bbz, do_bcnd, do_bsr, do_jsr): Use do_branch to handle
+       annuled branches.
+
 Mon May 12 17:15:52 1997  Mike Meissner  <meissner@cygnus.com>
 
        * insns (do_{ld,st}): Fix tracing for ld/st.

diff --git a/sim/tic80/alu.h b/sim/tic80/alu.h
index 4300723322fa443a35ccef95d6316bc761013fb3..3f13759e61bda403439cf1fcead3a851f515e0ed 100644 (file)
--- a/sim/tic80/alu.h
+++ b/sim/tic80/alu.h
@@ -38,8 +38,8 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 
 /* Bring data in from the cold */
 
-#define IMEM(EA) \
-(sim_core_read_aligned_4(STATE_CPU (sd, 0), cia, sim_core_execute_map, (EA)))
+#define IMEM(CIA) \
+(sim_core_read_aligned_4(STATE_CPU (sd, 0), CIA, sim_core_execute_map, (CIA).ip))
 
 #define MEM(SIGN, EA, NR_BYTES) \
 ((SIGN##_##NR_BYTES) sim_core_read_unaligned_##NR_BYTES (STATE_CPU (sd, 0), cia, \

diff --git a/sim/tic80/insns b/sim/tic80/insns
index f057f1c3ca01f86ba61a9f5f2cfd79dc462e2beb..ea0a5f31794846fb3b82f52690f9c34b1294c1c5 100644 (file)
--- a/sim/tic80/insns
+++ b/sim/tic80/insns
@@ -21,10 +21,31 @@
 
 // The following is called when ever an illegal instruction is encountered.
 ::internal::illegal
-       engine_error (SD, CPU, cia, "illegal instruction at 0x%lx", cia.ip);
+       engine_error (SD, CPU, cia,
+                     "illegal instruction at 0x%lx", cia.ip);
 // The following is called when ever an FP op is attempted with FPU disabled.
 ::internal::fp_unavailable
-       engine_error (SD, CPU, cia, "floating-point unavailable at 0x%lx", cia.ip);
+       engine_error (SD, CPU, cia,
+                     "floating-point unavailable at 0x%lx", cia.ip);
+
+// Handle a branch instruction
+instruction_address::function::do_branch:int annul, address_word target, int rLink_p, unsigned32 *rLink
+       instruction_address nia;
+       if (annul)
+         {
+           if (rLink_p)
+             *rLink = cia.dp;
+           nia.ip = target;
+           nia.dp = target + 4;
+         }
+       else
+         {
+           if (rLink_p)
+             *rLink = cia.dp + sizeof (instruction_word);
+           nia.ip = cia.dp;
+           nia.dp = target;
+         }
+       return nia;
 
 // Signed Integer Add - add source1, source2, dest
 void::function::do_add:signed32 *rDest, signed32 Source1, signed32 Source2
@@ -106,13 +127,11 @@ void::function::do_and:signed32 *rDest, signed32 Source1, signed32 Source2
 // bbo.[a]
 instruction_address::function::do_bbo:instruction_address nia, int bitnum, unsigned32 source, int annul, unsigned32 offset
        int jump_p;
-       unsigned32 target = cia.ip + 4 * offset;
+       address_word target = cia.ip + 4 * offset;
        bitnum = (~ bitnum) & 0x1f;
        if (MASKED32 (source, bitnum, bitnum))
          {
-           if (annul)
-             nia.ip = -1;
-           nia.dp = target;
+           nia = do_branch (_SD, annul, target, 0, NULL);
            jump_p = 1;
          }
        else
@@ -131,13 +150,11 @@ instruction_address::function::do_bbo:instruction_address nia, int bitnum, unsig
 // bbz[.a]
 instruction_address::function::do_bbz:instruction_address nia, int bitnum, unsigned32 source, int annul, unsigned32 offset
        int jump_p;
-       unsigned32 target = cia.ip + 4 * offset;
+       address_word target = cia.ip + 4 * offset;
        bitnum = (~ bitnum) & 0x1f;
        if (!MASKED32 (source, bitnum, bitnum))
          {
-           if (annul)
-             nia.ip = -1;
-           nia.dp = target;
+           nia = do_branch (_SD, annul, target, 0, NULL);
            jump_p = 1;
          }
        else
@@ -159,7 +176,7 @@ instruction_address::function::do_bcnd:instruction_address nia, int Cond, unsign
        int size = EXTRACTED32 (Cond, 31 - 27, 30 - 27);
        int code = EXTRACTED32 (Cond, 29 - 27, 27 - 27);
        signed32 val = 0;
-       unsigned32 target = cia.ip + 4 * offset;
+       address_word target = cia.ip + 4 * offset;
        switch (size)
          {
          case 0: val = SEXT32 (source, 7); break;
@@ -180,9 +197,7 @@ instruction_address::function::do_bcnd:instruction_address nia, int Cond, unsign
          }
        if (condition)
          {
-           if (annul)
-             nia.ip = -1;
-           nia.dp = target;
+           nia = do_branch (_SD, annul, target, 0, NULL);
          }
        TRACE_COND_BR(MY_INDEX, condition, source, target);
        return nia;
@@ -226,15 +241,9 @@ sim_cia::function::do_brcr:instruction_address nia, int cr
 
 // bsr[.a]
 instruction_address::function::do_bsr:instruction_address nia, signed32 *rLink, int annul, unsigned32 offset
-       if (annul)
-         {
-           *rLink = nia.ip;
-           nia.ip = -1;
-         }
-       else
-         *rLink = nia.ip + sizeof (instruction_word);
-       nia.dp = cia.ip + 4 * offset;
-       TRACE_UCOND_BR (MY_INDEX, nia.dp);
+       address_word target = cia.ip + 4 * offset;
+       nia = do_branch (_SD, annul, target, 1, rLink);
+       TRACE_UCOND_BR (MY_INDEX, target);
        return nia;
 31.Link,26./,21.0b100000,15.A,14.SignedOffset::::bsr i
        nia = do_bsr (_SD, nia, rLink, A, vSignedOffset);
@@ -606,15 +615,9 @@ void::function::do_fsub:int Dest, int PD, sim_fpu s1, sim_fpu s2
 
 // jsr[.a]
 instruction_address::function::do_jsr:instruction_address nia, signed32 *rLink, int annul, unsigned32 offset, unsigned32 base
-       TRACE_UCOND_BR (MY_INDEX, nia.ip);
-       if (annul)
-         {
-           *rLink = nia.ip;
-           nia.ip = -1;
-         }
-       else
-         *rLink = nia.ip + sizeof (instruction_word);
-       nia.dp = offset + base;
+       address_word target = offset + base;
+       TRACE_UCOND_BR (MY_INDEX, target);
+       nia = do_branch (_SD, annul, target, 1, rLink);
        if (nia.dp & 0x3)
          engine_error (SD, CPU, cia,
                        "0x%lx: destination address 0x%lx misaligned",

diff --git a/sim/tic80/interp.c b/sim/tic80/interp.c
index 072b9be1b0fb5c121f11a0d956b64dbc58958475..24cfad13af4e4c5b86258cc988a676b2a7d8b3d3 100644 (file)
--- a/sim/tic80/interp.c
+++ b/sim/tic80/interp.c
@@ -113,17 +113,8 @@ engine_run_until_stop (SIM_DESC sd,
       cia = cpu->cia;
       do
        {
-         if (cia.ip == -1)
-           {
-             /* anulled instruction */
-             cia.ip = cia.dp;
-             cia.dp = cia.dp + sizeof (instruction_word);
-           }
-         else
-           {
-             instruction_word insn = IMEM (cia.ip);
-             cia = idecode_issue (sd, insn, cia);
-           }
+         instruction_word insn = IMEM (cia);
+         cia = idecode_issue (sd, insn, cia);
        }
       while (*keep_running);
       engine_halt (sd, cpu, cia, sim_stopped, SIGINT);
@@ -137,22 +128,14 @@ engine_step (SIM_DESC sd)
   if (!setjmp (sd->path_to_halt))
     {
       instruction_address cia;
+      instruction_word insn;
       sim_cpu *cpu = STATE_CPU (sd, 0);
       sd->halt_ok = 1;
       setjmp (sd->path_to_restart);
       sd->restart_ok = 1;
       cia = cpu->cia;
-      if (cia.ip == -1)
-       {
-         /* anulled instruction */
-         cia.ip = cia.dp;
-         cia.dp = cia.dp + sizeof (instruction_word);
-       }
-      else
-       {
-         instruction_word insn = IMEM (cia.ip);
-         cia = idecode_issue (sd, insn, cia);
-       }
+      insn = IMEM (cia);
+      cia = idecode_issue (sd, insn, cia);
       engine_halt (sd, cpu, cia, sim_stopped, SIGTRAP);
     }
 }