ARM/opcodes: Fix negative hexadecimal offset disassembly

2014-08-21  Nathan Sidwell  <nathan@codesourcery.com>
            Maciej W. Rozycki  <macro@codesourcery.com>

	opcodes/
	* arm-dis.c (print_arm_address): Negate the GPR-relative offset
	returned if the U bit is set.

2014-08-21  Paul Brook  <paul@codesourcery.com>

	gas/testsuite/
	* gas/arm/arch7a-mp.d: Adjust according to `print_arm_address'
	offset fix.
	* gas/arm/arch7r-mp.d: Likewise.

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 88b49eebb92cbf208ee27f23549afbb1dc35bc29..edba881a5ff119bf1a72119c87a5e46d3fe4e5c4 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2014-08-22  Paul Brook  <paul@codesourcery.com>
+
+       * gas/arm/arch7a-mp.d: Adjust according to `print_arm_address'
+       offset fix.
+       * gas/arm/arch7r-mp.d: Likewise.
+
 2014-08-21  Maciej W. Rozycki  <macro@codesourcery.com>
 
        * gas/mips/mips.exp: Correct indentation.

diff --git a/gas/testsuite/gas/arm/arch7a-mp.d b/gas/testsuite/gas/arm/arch7a-mp.d
index bf6c6da6d5ffb6bcabf6fca5205ddd152577fd08..85a1a014ece7da56dbff5f2e1f5a7afcce6622d7 100644 (file)
--- a/gas/testsuite/gas/arm/arch7a-mp.d
+++ b/gas/testsuite/gas/arm/arch7a-mp.d
@@ -11,7 +11,7 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> f59ef000    pldw    \[lr\]
 0[0-9a-f]+ <[^>]+> f591f000    pldw    \[r1\]
 0[0-9a-f]+ <[^>]+> f590ffff    pldw    \[r0, #4095\]   ; 0xfff
-0[0-9a-f]+ <[^>]+> f510ffff    pldw    \[r0, #-4095\]  ; 0xfff
+0[0-9a-f]+ <[^>]+> f510ffff    pldw    \[r0, #-4095\]  ; 0xfffff001
 0[0-9a-f]+ <[^>]+> f790f000    pldw    \[r0, r0\]
 0[0-9a-f]+ <[^>]+> f791f000    pldw    \[r1, r0\]
 0[0-9a-f]+ <[^>]+> f79ef000    pldw    \[lr, r0\]

diff --git a/gas/testsuite/gas/arm/arch7r-mp.d b/gas/testsuite/gas/arm/arch7r-mp.d
index 8908c98c727215dc2ef65bd6c9d3c9eaea3b1cca..b6efd6a934eb31ea74e4f490449045faebbf4e0d 100644 (file)
--- a/gas/testsuite/gas/arm/arch7r-mp.d
+++ b/gas/testsuite/gas/arm/arch7r-mp.d
@@ -10,7 +10,7 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> f59ef000    pldw    \[lr\]
 0[0-9a-f]+ <[^>]+> f591f000    pldw    \[r1\]
 0[0-9a-f]+ <[^>]+> f590ffff    pldw    \[r0, #4095\]   ; 0xfff
-0[0-9a-f]+ <[^>]+> f510ffff    pldw    \[r0, #-4095\]  ; 0xfff
+0[0-9a-f]+ <[^>]+> f510ffff    pldw    \[r0, #-4095\]  ; 0xfffff001
 0[0-9a-f]+ <[^>]+> f790f000    pldw    \[r0, r0\]
 0[0-9a-f]+ <[^>]+> f791f000    pldw    \[r1, r0\]
 0[0-9a-f]+ <[^>]+> f79ef000    pldw    \[lr, r0\]

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index dfea7d366b4f12051679ab4cd5ea7636885215b5..a9581ae457dc54b27cbcfcbf7d0ab9b18a0a0c9a 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2014-08-21  Nathan Sidwell  <nathan@codesourcery.com>
+           Maciej W. Rozycki  <macro@codesourcery.com>
+
+       * arm-dis.c (print_arm_address): Negate the GPR-relative offset
+       returned if the U bit is set.
+
 2014-08-21  Maciej W. Rozycki  <macro@codesourcery.com>
 
        * micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index f43ce0df209b9645e5c6c924a6bca5438a13f579..8f399fbfafe7d848abc2f83d928f04400ce17614 100644 (file)
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -2583,6 +2583,8 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
              arm_decode_shift (given, func, stream, TRUE);
            }
        }
+      if (NEGATIVE_BIT_SET)
+       offset = -offset;
     }
 
   return (signed long) offset;