fprintf(stderr, " -o <offset in bytes> start address for read/write [default: 0]\n");
fprintf(stderr, " (append 'k' to the argument for size in kilobytes,\n");
fprintf(stderr, " or 'M' for size in megabytes)\n");
- fprintf(stderr, " -s slow SPI (50 kHz instead of 6 MHz)\n");
+ fprintf(stderr, " -k <divider> divider for SPI clock [default: 1]\n");
+ fprintf(stderr, " clock speed is 6MHz/divider");
+ fprintf(stderr, " -s slow SPI. (50 kHz instead of 6 MHz)\n");
+ fprintf(stderr, " Equivalent to -k 30\n");
fprintf(stderr, " -v verbose output\n");
fprintf(stderr, " -i [4,32,64] select erase block size [default: 64k]\n");
+ fprintf(stderr, " -a reinitialize the device after any operation\n");
fprintf(stderr, "\n");
fprintf(stderr, "Mode of operation:\n");
fprintf(stderr, " [default] write file contents to flash, then verify\n");
int erase_block_size = 64;
int erase_size = 0;
int rw_offset = 0;
+ int clkdiv = 1;
+ bool reinitialize = false;
bool read_mode = false;
bool check_mode = false;
bool erase_mode = false;
/**
* Performs any start-of-day tasks necessary to talk JTAG to our FPGA.
*/
-void jtag_init(int ifnum, const char *devstr, bool slow_clock)
+void jtag_init(int ifnum, const char *devstr, int clkdiv)
{
- mpsse_init(ifnum, devstr, slow_clock);
+ mpsse_init(ifnum, devstr, clkdiv);
jtag_set_current_state(STATE_TEST_LOGIC_RESET);
- jtag_go_to_state(STATE_TEST_LOGIC_RESET);
+ jtag_go_to_state(STATE_TEST_LOGIC_RESET);
}
uint8_t data[32*1024];
static inline void jtag_pulse_clock_and_read_tdo(bool tms, bool tdi)
{
- *ptr++ = MC_DATA_TMS | MC_DATA_IN | MC_DATA_LSB | MC_DATA_BITS | MC_DATA_OCN | MC_DATA_ICN;
- *ptr++ = MC_DATA_TMS | MC_DATA_IN | MC_DATA_LSB | MC_DATA_BITS | MC_DATA_OCN;
++ *ptr++ = MC_DATA_TMS | MC_DATA_IN | MC_DATA_LSB | MC_DATA_BITS | MC_DATA_OCN | MC_DATA_ICN;
*ptr++ = 0;
- *ptr++ = (tdi ? 0x80 : 0) | (tms ? 0x01 : 0);
+ *ptr++ = (tdi ? 0x80 : 0) | (tms ? 0x01 : 0);
rx_cnt++;
}