back.pysim: warn if simulation is not run.
authorwhitequark <whitequark@whitequark.org>
Sat, 29 Dec 2018 15:02:04 +0000 (15:02 +0000)
committerwhitequark <whitequark@whitequark.org>
Sat, 29 Dec 2018 15:02:04 +0000 (15:02 +0000)
This would have prevented 3ea35b85.

nmigen/back/pysim.py
nmigen/test/test_sim.py

index 7a5639cb8fd55089a3e28193b62c408ab15bb2a8..0bcb0b338100238631528fd0cf28cc9ce9b90943 100644 (file)
@@ -1,5 +1,6 @@
 import math
 import inspect
+import warnings
 from contextlib import contextmanager
 from bitarray import bitarray
 from vcd import VCDWriter
@@ -365,6 +366,8 @@ class Simulator:
         self._gtkw_file       = gtkw_file
         self._traces          = traces
 
+        self._run_called      = False
+
         while not isinstance(self._fragment, Fragment):
             self._fragment = self._fragment.get_fragment(platform=None)
 
@@ -755,10 +758,14 @@ class Simulator:
         return False
 
     def run(self):
+        self._run_called = True
+
         while self.step():
             pass
 
     def run_until(self, deadline, run_passive=False):
+        self._run_called = True
+
         while self._timestamp < deadline:
             if not self.step(run_passive):
                 return False
@@ -766,6 +773,9 @@ class Simulator:
         return True
 
     def __exit__(self, *args):
+        if not self._run_called:
+            warnings.warn("Simulation created, but not run", UserWarning)
+
         if self._vcd_writer:
             vcd_timestamp = (self._timestamp + self._delta) / self._epsilon
             self._vcd_writer.close(vcd_timestamp)
index cdd83d7648af7503392030e5dff149e854f8e1f7..5b7722286db2835b3694b25f7e1630b8a0c514ac 100644 (file)
@@ -530,3 +530,9 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
                 self.assertEqual((yield self.rdport.data), 0x33)
             sim.add_clock(1e-6)
             sim.add_process(process)
+
+    def test_wrong_not_run(self):
+        with self.assertWarns(UserWarning,
+                msg="Simulation created, but not run"):
+            with Simulator(Fragment()) as sim:
+                pass