removed question mark

diff --git a/openpower/svp64-primer/summary.tex b/openpower/svp64-primer/summary.tex
index 318125d8b72b0d06f211569efa465b5603bf9125..9523bfdf337a2c8d145c97356b433db0c835b3d2 100644 (file)
--- a/openpower/svp64-primer/summary.tex
+++ b/openpower/svp64-primer/summary.tex
@@ -161,7 +161,7 @@ how a Vector's elements are sequentially and linearly mapped onto the
 
 \subsection{Simple Vectorisation}
 \acs{SV} is a Scalable Vector ISA designed for hybrid workloads (CPU, GPU,
-VPU, 3D?).  Includes features normally found only on Cray-style Supercomputers
+VPU, 3D).  Includes features normally found only on Cray-style Supercomputers
 (Cray-1, NEC SX-Aurora) and GPUs.  Keeps to a strict uniform RISC paradigm,
 leveraging a scalar ISA by using "Prefixing".
 \textbf{No dedicated vector opcodes exist in SV, at all}.