r600g: don't use register mask for CB_COLOR_CONTROL on r6xx-r7xx

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index 169d5817fd0f1ac81166fc6892a36fdd70464388..b7c5e55b5405c4350b0321106ae513ff71088ec2 100644 (file)
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -116,6 +116,7 @@ struct r600_pipe_rasterizer {
 struct r600_pipe_blend {
        struct r600_pipe_state          rstate;
        unsigned                        cb_target_mask;
+       unsigned                        cb_color_control;
 };
 
 struct r600_pipe_dsa {
@@ -207,6 +208,7 @@ struct r600_pipe_context {
        struct r600_pipe_resource_state fs_resource[PIPE_MAX_ATTRIBS];
        struct pipe_framebuffer_state   framebuffer;
        unsigned                        cb_target_mask;
+       unsigned                        cb_color_control;
        /* for saving when using blitter */
        struct pipe_stencil_ref         stencil_ref;
        struct pipe_viewport_state      viewport;

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 821da0d9e276d86ea3a8df11fb84fecceca4ad67..e1d8ab3afc5613c1739f5124785738f44dc8699b 100644 (file)
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -810,9 +810,7 @@ static void *r600_create_blend_state(struct pipe_context *ctx,
                }
        }
        blend->cb_target_mask = target_mask;
-       /* MULTIWRITE_ENABLE is controlled by r600_pipe_shader_ps(). */
-       r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
-                               color_control, 0xFFFFFFFD, NULL, 0);
+       blend->cb_color_control = color_control;
 
        for (int i = 0; i < 8; i++) {
                /* state->rt entries > 0 only written if independent blending */
@@ -2166,10 +2164,6 @@ void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shad
        r600_pipe_state_add_reg(rstate,
                                R_0288CC_SQ_PGM_CF_OFFSET_PS,
                                0x00000000, 0xFFFFFFFF, NULL, 0);
-       r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
-                               S_028808_MULTIWRITE_ENABLE(!!rshader->fs_write_all),
-                               S_028808_MULTIWRITE_ENABLE(1),
-                               NULL, 0);
        /* only set some bits here, the other bits are set in the dsa state */
        r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
                                db_shader_control,

diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
index 8bf55132dfdf61f83b2d4ca3e877c13c0edfbe8a..9833de0f5222963a0c25b511021e51a40c85d7a9 100644 (file)
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -73,6 +73,11 @@ void r600_bind_blend_state(struct pipe_context *ctx, void *state)
        rstate = &blend->rstate;
        rctx->states[rstate->id] = rstate;
        rctx->cb_target_mask = blend->cb_target_mask;
+
+       /* Replace every bit except MULTIWRITE_ENABLE. */
+       rctx->cb_color_control &= ~C_028808_MULTIWRITE_ENABLE;
+       rctx->cb_color_control |= blend->cb_color_control & C_028808_MULTIWRITE_ENABLE;
+
        r600_context_pipe_state_set(&rctx->ctx, rstate);
 }
 
@@ -326,6 +331,9 @@ void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
        rctx->ps_shader = (struct r600_pipe_shader *)state;
        if (state) {
                r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_shader->rstate);
+
+               rctx->cb_color_control &= C_028808_MULTIWRITE_ENABLE;
+               rctx->cb_color_control |= S_028808_MULTIWRITE_ENABLE(!!rctx->ps_shader->shader.fs_write_all);
        }
        if (rctx->ps_shader && rctx->vs_shader) {
                r600_adjust_gprs(rctx);
@@ -750,6 +758,8 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
                r600_pipe_state_add_reg(&rctx->vgt, R_028814_PA_SU_SC_MODE_CNTL,
                                        0,
                                        S_028814_PROVOKING_VTX_LAST(1), NULL, 0);
+               if (rctx->chip_class <= R700)
+                       r600_pipe_state_add_reg(&rctx->vgt, R_028808_CB_COLOR_CONTROL, rctx->cb_color_control, 0xFFFFFFFF, NULL, 0);
        }
 
        rctx->vgt.nregs = 0;
@@ -771,7 +781,11 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
 
        if (info.mode == PIPE_PRIM_QUADS || info.mode == PIPE_PRIM_QUAD_STRIP || info.mode == PIPE_PRIM_POLYGON) {
                r600_pipe_state_mod_reg(&rctx->vgt, S_028814_PROVOKING_VTX_LAST(1));
+       } else {
+               r600_pipe_state_mod_reg(&rctx->vgt, 0);
        }
+       if (rctx->chip_class <= R700)
+               r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_color_control);
 
        r600_context_pipe_state_set(&rctx->ctx, &rctx->vgt);