CellTypes ct;
SigMap sigmap;
- std::map<RTLIL::IdString, std::set<WireInfo,WireInfoOrder>> inter_wire_map;//<wire, dependency list> for maping the intermediate wires that are output of some cell
+ std::map<RTLIL::IdString, std::set<WireInfo,WireInfoOrder>> inter_wire_map;//<wire, dependency list> for mapping the intermediate wires that are output of some cell
std::map<RTLIL::IdString, int> line_ref;//mapping of ids to line_num of the btor file
std::map<RTLIL::SigSpec, int> sig_ref;//mapping of sigspec to the line_num of the btor file
int line_num;//last line number of btor file
//registers
else if(cell->type == "$dff" || cell->type == "$adff" || cell->type == "$dffsr")
{
- //TODO: remodelling fo adff cells
+ //TODO: remodelling of adff cells
log("writing cell - %s\n", cstr(cell->type));
int output_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
log(" - width is %d\n", output_width);
f << stringf("[%d:%d] ", wire->width - 1 + wire->start_offset, wire->start_offset);
f << stringf("%s;\n", id(wire->name).c_str());
#else
- // do not use Verilog-2k "outut reg" syntax in verilog export
+ // do not use Verilog-2k "output reg" syntax in Verilog export
std::string range = "";
if (wire->width != 1) {
if (wire->upto)
void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire);
// parametric modules are supported directly by the AST library
- // therfore we need our own derivate of RTLIL::Module with overloaded virtual functions
+ // therefore we need our own derivate of RTLIL::Module with overloaded virtual functions
struct AstModule : RTLIL::Module {
AstNode *ast;
bool nolatches, nomeminit, nomem2reg, mem2reg, lib, noopt, icells, autowire;
RTLIL::Process *proc;
RTLIL::SigSpec outputSignals;
- // This always points to the RTLIL::CaseRule beeing filled at the moment
+ // This always points to the RTLIL::CaseRule being filled at the moment
RTLIL::CaseRule *current_case;
// This map contains the replacement pattern to be used in the right hand side
// of an assignment. E.g. in the code "foo = bar; foo = func(foo);" the foo in the right
// hand side of the 2nd assignment needs to be replace with the temporary signal holding
- // the value assigned in the first assignment. So when the first assignement is processed
+ // the value assigned in the first assignment. So when the first assignment is processed
// the according information is appended to subst_rvalue_from and subst_rvalue_to.
stackmap<RTLIL::SigBit, RTLIL::SigBit> subst_rvalue_map;
// signal that is used as input for the register that drives the signal foo.
stackmap<RTLIL::SigBit, RTLIL::SigBit> subst_lvalue_map;
- // The code here generates a number of temprorary signal for each output register. This
+ // The code here generates a number of temporary signal for each output register. This
// map helps generating nice numbered names for all this temporary signals.
std::map<RTLIL::Wire*, int> new_temp_count;
// in the following big switch() statement there are some uses of
// Clifford's Device (http://www.clifford.at/cfun/cliffdev/). In this
// cases this variable is used to hold the type of the cell that should
- // be instanciated for this type of AST node.
+ // be instantiated for this type of AST node.
std::string type_name;
current_filename = filename;
switch (type)
{
// simply ignore this nodes.
- // they are eighter leftovers from simplify() or are referenced by other nodes
+ // they are either leftovers from simplify() or are referenced by other nodes
// and are only accessed here thru this references
case AST_TASK:
case AST_FUNCTION:
}
// generate cells for unary operations: $reduce_bool
- // (this is actually just an $reduce_or, but for clearity a different cell type is used)
+ // (this is actually just an $reduce_or, but for clarity a different cell type is used)
if (0) { case AST_REDUCE_BOOL: type_name = "$reduce_bool"; }
{
RTLIL::SigSpec arg = children[0]->genRTLIL();
}
// this is a wrapper for AstNode::genRTLIL() when a specific signal width is requested and/or
-// signals must be substituted before beeing used as input values (used by ProcessGenerator)
+// signals must be substituted before being used as input values (used by ProcessGenerator)
// note that this is using some global variables to communicate this special settings to AstNode::genRTLIL().
RTLIL::SigSpec AstNode::genWidthRTLIL(int width, const dict<RTLIL::SigBit, RTLIL::SigBit> *new_subst_ptr)
{
using namespace AST;
using namespace AST_INTERNAL;
-// convert the AST into a simpler AST that has all parameters subsitited by their
+// convert the AST into a simpler AST that has all parameters substituted by their
// values, unrolled for-loops, expanded generate blocks, etc. when this function
// is done with an AST it can be converted into RTLIL using genRTLIL().
//
set_line_num(linenum);
// we do not look inside a task or function
- // (but as soon as a task of function is instanciated we process the generated AST as usual)
+ // (but as soon as a task or function is instantiated we process the generated AST as usual)
if (type == AST_FUNCTION || type == AST_TASK) {
recursion_counter--;
return false;
}
- // deactivate all calls to non-synthesis system taks
+ // deactivate all calls to non-synthesis system tasks
if ((type == AST_FCALL || type == AST_TCALL) && (str == "$display" || str == "$strobe" || str == "$monitor" || str == "$time" || str == "$stop" || str == "$finish" ||
str == "$dumpfile" || str == "$dumpvars" || str == "$dumpon" || str == "$dumpoff" || str == "$dumpall")) {
log_warning("Ignoring call to system %s %s at %s:%d.\n", type == AST_FCALL ? "function" : "task", str.c_str(), filename.c_str(), linenum);
goto apply_newNode;
}
- // replace primitives with assignmens
+ // replace primitives with assignments
if (type == AST_PRIMITIVE)
{
if (children.size() < 2)
name_map.swap(backup_name_map);
}
-// rename stuff (used when tasks of functions are instanciated)
+// rename stuff (used when tasks of functions are instantiated)
void AstNode::replace_ids(const std::string &prefix, const std::map<std::string, std::string> &rules)
{
if (type == AST_BLOCK)
return did_something;
}
-// calulate memory dimensions
+// calculate memory dimensions
void AstNode::meminfo(int &mem_width, int &mem_size, int &addr_bits)
{
log_assert(type == AST_MEMORY);
log("\n");
log(" verific -import [-gates] {-all | <top-module>..}\n");
log("\n");
- log("Elaborate the design for the sepcified top modules, import to Yosys and\n");
+ log("Elaborate the design for the specified top modules, import to Yosys and\n");
log("reset the internal state of Verific. A gate-level netlist is created\n");
log("when called with -gates.\n");
log("\n");
log("\n");
log(" verilog_defaults -add [options]\n");
log("\n");
- log("Add the sepcified options to the list of default options to read_verilog.\n");
+ log("Add the specified options to the list of default options to read_verilog.\n");
log("\n");
log("\n");
log(" verilog_defaults -clear");
printf(" print version information and exit\n");
printf("\n");
printf("The option -S is an shortcut for calling the \"synth\" command, a default\n");
- printf("script for transforming the verilog input to a gate-level netlist. For example:\n");
+ printf("script for transforming the Verilog input to a gate-level netlist. For example:\n");
printf("\n");
printf(" yosys -o output.blif -S input.v\n");
printf("\n");
// ------------------------------------------------------------
// simple timer for performance measurements
-// toggle the '#if 1' to get a baseline for the perormance penalty added by the measurement
+// toggle the '#if 1' to get a baseline for the performance penalty added by the measurement
struct PerformanceTimer
{
#if 1
bool operator==(IdString rhs) const { return index_ == rhs.index_; }
bool operator!=(IdString rhs) const { return index_ != rhs.index_; }
- // The methods below are just convinience functions for better compatibility with std::string.
+ // The methods below are just convenience functions for better compatibility with std::string.
bool operator==(const std::string &rhs) const { return str() == rhs; }
bool operator!=(const std::string &rhs) const { return str() != rhs; }
log("The tcl command 'yosys -import' can be used to import all yosys\n");
log("commands directly as tcl commands to the tcl shell. The yosys\n");
log("command 'proc' is wrapped using the tcl command 'procs' in order\n");
- log("to avoid a name collision with the tcl builting command 'proc'.\n");
+ log("to avoid a name collision with the tcl builtin command 'proc'.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
class ezSAT
{
- // each token (terminal or non-terminal) is represented by an interger number
+ // each token (terminal or non-terminal) is represented by an integer number
//
// the zero token:
// the number zero is not used as valid token number and is used to encode
\begin{document}
\title{Yosys Application Note 011: \\ Interactive Design Investigation}
-\author{Clifford Wolf \\ Original Verision December 2013}
+\author{Clifford Wolf \\ Original Version December 2013}
\maketitle
\begin{abstract}
In this case however we would like to see the cells connected properly. This
can be achieved using the {\tt \%x} action, that broadens the selection, i.e.
for each selected wire it selects all cells connected to the wire and vice
-versa. So {\tt show a:sumstuff \%x} yields the diagram schon in Fig.~\ref{sumprod_01}.
+versa. So {\tt show a:sumstuff \%x} yields the diagram shown in Fig.~\ref{sumprod_01}.
\begin{figure}[t]
\includegraphics[width=\linewidth]{APPNOTE_011_Design_Investigation/sumprod_01.pdf}
2'11 1'0 | 2'00 2'00
2'11 1'1 | 2'xx 2'11
- Assumend undef (x) value for the following singals: \s2
+ Assumed undef (x) value for the following signals: \s2
\end{verbatim}
}
We assume that the Verilog design is synthesizable and we also assume
that the design does not have multi-dimensional memories. As BTOR
implicitly initializes registers to zero value and memories stay
-uninitilized, we assume that the Verilog design does
+uninitialized, we assume that the Verilog design does
not contain initial blocks. For more details about the BTOR format,
please refer to~\cite{btor}.
% \end{fixme}
%
% \section{Synthesizing using a Cell Library in Liberty Format}
-% \section{Reverse Engeneering the MOS6502 from an NMOS Transistor Netlist}
+% \section{Reverse Engineering the MOS6502 from an NMOS Transistor Netlist}
% \section{Reconfigurable Coarse-Grain Synthesis using Intersynth}
This appendix contains copies of the Yosys application notes.
\section{Internal Formats in Yosys}
-Yosys uses two different internal formats. The first is used to store an abstract syntax tree (AST) of a verilog
+Yosys uses two different internal formats. The first is used to store an abstract syntax tree (AST) of a Verilog
input file. This format is simply called {\it AST} and is generated by the Verilog Frontend. This data structure
is consumed by a subsystem called {\it AST Frontend}\footnote{In Yosys the term {\it pass} is only used to
refer to commands that operate on the RTLIL data structure.}. This AST Frontend then generates a design in Yosys'
described by the Liberty file \citeweblink{LibertyFormat} {\tt cells.lib}:
\begin{lstlisting}[language=sh,numbers=left,frame=single]
-# read input file tpo internal representation
+# read input file to internal representation
read_verilog design.v
# convert high-level behavioral parts ("processes") to d-type flip-flops and muxes
-\chapter{Auxilary Libraries}
+\chapter{Auxiliary Libraries}
-The Yosys source distribution contains some auxilary libraries that are bundled
+The Yosys source distribution contains some auxiliary libraries that are bundled
with Yosys.
\section{SHA1}
-\chapter{Auxilary Programs}
+\chapter{Auxiliary Programs}
Besides the main {\tt yosys} executable, the Yosys distribution contains a set
of additional helper programs.
must be able to transfer this representation into an appropriate datapath followed
by the appropriate types of register.
-For example consider the following verilog code fragment:
+For example consider the following Verilog code fragment:
\begin{lstlisting}[numbers=left,frame=single,language=Verilog]
always @(posedge clk)
\subsection{Register-Transfer Level (RTL)}
On the Register-Transfer Level the design is represented by combinatorial data
-paths and registers (usually d-type flip flops). The following verilog code fragment
-is equivalent to the previous verilog example, but is in RTL representation:
+paths and registers (usually d-type flip flops). The following Verilog code fragment
+is equivalent to the previous Verilog example, but is in RTL representation:
\begin{lstlisting}[numbers=left,frame=single,language=Verilog]
assign tmp = a + b; // combinatorial data path
and identification of shareable resources.
Note that RTL is the first abstraction level in which the circuit is represented as a
-graph of circuit elements (registers and combinatorical cells) and signals. Such a graph,
+graph of circuit elements (registers and combinatorial cells) and signals. Such a graph,
when encoded as list of cells and connections, is called a netlist.
RTL synthesis is easy as each circuit node element in the netlist can simply be replaced
\end{itemize}
Many tools (especially at the back end of the synthesis chain) only support
-structural verilog as input. ABC is an example of such a tool. Unfortunately
+structural Verilog as input. ABC is an example of such a tool. Unfortunately
there is no standard specifying what {\it Structural Verilog} actually is,
leading to some confusion about what syntax constructs are supported in
-structural verilog when it comes to features such as attributes or multi-bit
+structural Verilog when it comes to features such as attributes or multi-bit
signals.
\subsection{Expressions in Verilog}
During synthesis these operators are replaced by cells that implement the respective function.
Many FOSS tools that claim to be able to process Verilog in fact only support
-basic structural verilog and simple expressions. Yosys can be used to convert
-full featured synthesizable verilog to this simpler subset, thus enabling such
+basic structural Verilog and simple expressions. Yosys can be used to convert
+full featured synthesizable Verilog to this simpler subset, thus enabling such
applications to be used with a richer set of Verilog features.
\subsection{Behavioural Modelling}
automatic steps in a design project with a fixed set of settings easily.
Because of this, usually all programs used in a synthesis flow can be
controlled using scripts. This means that all functions are available via
-text commands. When such a tool provides a gui, this is complementary to,
+text commands. When such a tool provides a GUI, this is complementary to,
and not instead of, a command line interface.
Usually a synthesis flow in an UNIX/Linux environment would be controlled by a
from RTLIL::Process objects to logic.
The simplest multiplexer cell type is {\tt \$mux}. Cells of this type have a \B{WIDTH} parameter
-and data inputs \B{A} and \B{B} and a data ouput \B{Y}, all of the specified width. This cell also
+and data inputs \B{A} and \B{B} and a data output \B{Y}, all of the specified width. This cell also
has a single bit control input \B{S}. If \B{S} is 0 the value from the \B{A} input is sent to
the output, if it is 1 the value from the \B{B} input is sent to the output. So the {\tt \$mux}
cell implements the function \lstinline[language=Verilog]; Y = S ? B : A;.
The cell types {\tt \$\_DFF\_NN0\_}, {\tt \$\_DFF\_NN1\_}, {\tt \$\_DFF\_NP0\_}, {\tt \$\_DFF\_NP1\_},
{\tt \$\_DFF\_PN0\_}, {\tt \$\_DFF\_PN1\_}, {\tt \$\_DFF\_PP0\_} and {\tt \$\_DFF\_PP1\_} implement
d-type flip-flops with asynchronous resets. The values in the table for these cell types relate to the
-following verilog code template, where \lstinline[mathescape,language=Verilog];$RstEdge$; is \lstinline[language=Verilog];posedge;
+following Verilog code template, where \lstinline[mathescape,language=Verilog];$RstEdge$; is \lstinline[language=Verilog];posedge;
if \lstinline[mathescape,language=Verilog];$RstLvl$; if \lstinline[language=Verilog];1;, and \lstinline[language=Verilog];negedge;
otherwise.
make test} is executed. During development of Yosys it was shown that this
collection of test cases is sufficient to catch most bugs. The following more
sophisticated test procedures only caught a few additional bugs. Whenever this
-happend, an appropiate test case was added to the collection of small test
+happened, an appropriate test case was added to the collection of small test
cases for {\tt make test} to ensure better testability of the feature in
question in the future.
\item VlogHammer \citeweblink{VlogHammer} is a set of scripts that
auto-generate a large collection of test cases\footnote{At the time of this
writing over 6600 test cases.} and synthesize them using Yosys and the
-following freely available propritary synthesis tools.
+following freely available proprietary synthesis tools.
\begin{itemize}
\item Xilinx Vivado WebPack (2013.2) \citeweblink{XilinxWebPACK}
\item Xilinx ISE (XST) WebPack (14.5) \citeweblink{XilinxWebPACK}
according to Sec.~5.1.10 of IEEE Std. 1364-2005 \cite{Verilog2005}.
The next two lines assume the value 0 for undef states. These two rules are only
-used if no other subsitutions are possible in the current module. If other substitutions
+used if no other substitutions are possible in the current module. If other substitutions
are possible they are performed first, in the hope that the `any' will change to
an undef value or a 1 and therefore the output can be set to undef.
\item Entries in the transition table that yield the same output and only
differ in the value of a single control input bit are merged and the different bit is removed
from the sensitivity list (turned into a don't-care bit).
-\item Constant inputs are removed and the transition table is alterered to give an unchanged behaviour.
+\item Constant inputs are removed and the transition table is altered to give an unchanged behaviour.
\item Unused inputs are removed.
\end{itemize}
\end{itemize}
As with modules, the attributes can be Verilog attributes imported by the
-Verilog frontend or attributes assigned by passees.
+Verilog frontend or attributes assigned by passes.
In Yosys, busses (signal vectors) are represented using a single wire object
with a width > 1. So Yosys does not convert signal vectors to individual signals.
presence of these objects in a module increases the complexity. Therefore the passes to translate
processes to a netlist of cells are usually called early in a synthesis script. The {\tt proc}
pass calls a series of other passes that together perform this conversion in a way that is suitable
-for most synthesis taks.
+for most synthesis tasks.
\subsection{RTLIL::Memory}
// count how many times a single-bit signal is used
std::map<RTLIL::SigBit, int> bit_usage_count;
- // count ouput lines for this module (needed only for summary output at the end)
+ // count output lines for this module (needed only for summary output at the end)
int line_count = 0;
log("Looking for stub wires in module %s:\n", RTLIL::id2cstr(module->name));
ends and/or additional synthesis passes.
Chapter~\ref{chapter:eval} contains a more detailed evaluation of Yosys using real-world
-designes that are far out of reach for any of the other tools discussed in this appendix.
+designs that are far out of reach for any of the other tools discussed in this appendix.
\vskip2cm
\begin{table}[h]
*
* The internal logic cell simulation library.
*
- * This verilog library contains simple simulation models for the internal
+ * This Verilog library contains simple simulation models for the internal
* logic cells (_NOT_, _AND_, ...) that are generated by the default technology
* mapper (see "stdcells.v" in this directory) and expected by the "abc" pass.
*
Previous chapters outlined how HDL code is transformed into an RTL netlist. The
RTL netlist is still based on abstract coarse-grain cell types like arbitrary
width adders and even multipliers. This chapter covers how an RTL netlist is
-transformed into a functionally equivialent netlist utililizing the cell types
+transformed into a functionally equivalent netlist utilizing the cell types
available in the target architecture.
Technology mapping is often performed in two phases. In the first phase RTL cells
recognised by the Yosys Verilog frontend.
\end{sloppypar}
-The lexer keeps track of the current location in the verilog source code using
+The lexer keeps track of the current location in the Verilog source code using
some global variables. These variables are used by the constructor of AST nodes
to annotate each node with the source code location it originated from.
\hline
%
{\tt AST\_PARASET} &
-Parameter set in cell instanciation \\
+Parameter set in cell instantiation \\
\hline
%
{\tt AST\_ARGUMENT} &
-Port connection in cell instanciation \\
+Port connection in cell instantiation \\
\hline
%
{\tt AST\_RANGE} &
\hline
%
{\tt AST\_CELLTYPE} &
-The type of cell in cell instanciation \\
+The type of cell in cell instantiation \\
\hline
%
{\tt AST\_IDENTIFIER} &
\hline
%
{\tt AST\_REDUCE\_BOOL} &
-Conversion from multi-bit value to boolian value
-(equivialent to {\tt AST\_REDUCE\_OR}) \\
+Conversion from multi-bit value to boolean value
+(equivalent to {\tt AST\_REDUCE\_OR}) \\
\hline
%
{\tt AST\_SHIFT\_LEFT},
\hline
%
{\tt AST\_CELL} &
-A cell instanciation \\
+A cell instantiation \\
\hline
%
{\tt AST\_PRIMITIVE} &
\hline
%
{\tt AST\_FOR} &
-A \lstinline[language=Verilog];for;-loop witn an
+A \lstinline[language=Verilog];for;-loop with an
\lstinline[language=Verilog];always;- or
\lstinline[language=Verilog];initial;-block \\
\hline
\subsection{Generating RTLIL}
After AST simplification, the \lstinline[language=C++]{AST::AstNode::genRTLIL()} method of each {\tt AST\_MODULE} node
-in the AST is called. This initiates a recursive process that generates equivialent RTLIL data for the AST data.
+in the AST is called. This initiates a recursive process that generates equivalent RTLIL data for the AST data.
The \lstinline[language=C++]{AST::AstNode::genRTLIL()} method returns an \lstinline[language=C++]{RTLIL::SigSpec} structure.
For nodes that represent expressions (operators, constants, signals, etc.), the cells needed to implement the calculation
generated \lstinline[language=C++]{RTLIL::Process}.
\end{itemize}
-As the algorithm runs these variables are continously modified as well as pushed
+As the algorithm runs these variables are continuously modified as well as pushed
to the stack and later restored to their earlier values by popping from the stack.
On startup the ProcessGenerator generates a new
\item A new \lstinline[language=C++]{RTLIL::SwitchRule} object is generated, the selection expression is evaluated using
\lstinline[language=C++]{AST::AstNode::genRTLIL()} (with the use of \lstinline[language=C++]{subst_rvalue_from} and
\lstinline[language=C++]{subst_rvalue_to}) and added to the \lstinline[language=C++]{RTLIL::SwitchRule} object and the
-obect is added to the \lstinline[language=C++]{current_case}.
+object is added to the \lstinline[language=C++]{current_case}.
%
\item All lvalues assigned to within the {\tt AST\_CASE} node using blocking assignments are collected and
saved in the local variable \lstinline[language=C++]{this_case_eq_lvalue}.
\begin{fixme}
Add some information on the generation of {\tt \$memrd} and {\tt \$memwr} cells
-and how they are processsed in the {\tt memory} pass.
+and how they are processed in the {\tt memory} pass.
\end{fixme}
\section{Synthesizing Parametric Designs}
\begin{itemize}
\item
The {\tt techmap} command replaces cells in the design with implementations given
-as verilog code (called ``map files''). It can replace Yosys' internal cell
+as Verilog code (called ``map files''). It can replace Yosys' internal cell
types (such as {\tt \$or}) as well as user-defined cell types.
\medskip\item
Verilog parameters are used extensively to customize the internal cell types.
\subsubsection{Intro to coarse-grain synthesis}
\begin{frame}[fragile]{\subsubsecname}
-In coarse-grain synthesis the target architecure has cells of the same
+In coarse-grain synthesis the target architecture has cells of the same
complexity or larger complexity than the internal RTL representation.
For example:
\begin{frame}{\subsubsecname}
\scriptsize
Often a coarse-grain element has a constant bit-width, but can be used to
-implement oprations with a smaller bit-width. For example, a 18x25-bit multiplier
+implement operations with a smaller bit-width. For example, a 18x25-bit multiplier
can also be used to implement 16x20-bit multiplication.
\bigskip
\item {\bf Behavioral changes} \\
Commands such as {\tt techmap} can be used to make behavioral changes to the design, for example
-changing asynchonous resets to synchronous resets. This has applications in design space exploration
+changing asynchronous resets to synchronous resets. This has applications in design space exploration
(evaluation of various architectures for one circuit).
\end{itemize}
\end{frame}
\begin{frame}{\subsecname}
\begin{itemize}
-\item A lot can be achived in Yosys just with the standard set of commands.
+\item A lot can be achieved in Yosys just with the standard set of commands.
\item The commands {\tt techmap} and {\tt extract} can be used to prototype many complex synthesis tasks.
\end{itemize}
\item
Commands such as {\tt submod}, {\tt expose}, {\tt splice}, \dots can be used
-to transform the design into an equivialent design that is easier to analyse.
+to transform the design into an equivalent design that is easier to analyse.
\item
Commands such as {\tt eval} and {\tt sat} can be used to investigate the
(or has not) a given property.
\bigskip
-One appliction is Formal Equivalence Checking: Proving that two circuits
+One application is Formal Equivalence Checking: Proving that two circuits
are identical. For example this is a very useful feature when debugging custom
passes in Yosys.
# apply the techmap only to test_mapped
techmap -map techmap_01_map.v test_mapped
-# create a miter circuit to test equivialence
+# create a miter circuit to test equivalence
miter -equiv -make_assert -make_outputs test_orig test_mapped miter
flatten miter
-# run equivialence check
+# run equivalence check
sat -verify -prove-asserts -show-inputs -show-outputs miter
\end{lstlisting}
# apply the techmap only to test_mapped
techmap -map ../PRESENTATION_ExSyn/techmap_01_map.v test_mapped
-# create a miter circuit to test equivialence
+# create a miter circuit to test equivalence
miter -equiv -make_assert -make_outputs test_orig test_mapped miter
flatten miter
-# run equivialence check
+# run equivalence check
sat -verify -prove-asserts -show-inputs -show-outputs miter
\begin{frame}{\subsecname}
Usually it does not hurt to call {\tt opt} after each regular command in the
synthesis script. But it increases the synthesis time, so it is favourable
-to only call {\tt opt} when an improvement can be archieved.
+to only call {\tt opt} when an improvement can be achieved.
\bigskip
The designs in {\tt yosys-bigsim} are a good playground for experimenting with
\end{frame}
\begin{frame}{\subsecname{} -- details}
-Some details on the most importand commands from the {\tt fsm\_*} group:
+Some details on the most important commands from the {\tt fsm\_*} group:
\bigskip
The {\tt fsm\_detect} command identifies FSM state registers and marks them
\only<3>{Netlists}%
\only<4>{Hardware Description Languages (HDLs)}}
\only<1>{
- Graphical representation of the circtuit topology. Circuit elements
- are represented by symbols and electrical connections by lines. The gometric
+ Graphical representation of the circuit topology. Circuit elements
+ are represented by symbols and electrical connections by lines. The geometric
layout is for readability only.
}%
\only<2>{
- The actual physical geometry of the device (PCB or ASIC manufracturing masks).
+ The actual physical geometry of the device (PCB or ASIC manufacturing masks).
This is the final product of the design process.
}%
\only<3>{
}%
\only<4>{
List of registers (flip-flops) and logic functions that calculate the next state from the previous one. Usually
- a netlist utilizing high-level cells such as adders, multiplieres, multiplexer, etc.
+ a netlist utilizing high-level cells such as adders, multipliers, multiplexer, etc.
}%
\only<5>{
Netlist of single-bit registers and basic logic gates (such as AND, OR,
}%
\only<6>{
Netlist of cells that actually are available on the target architecture
- (such as CMOS gates in an ASCI or LUTs in an FPGA). Optimized for
+ (such as CMOS gates in an ASIC or LUTs in an FPGA). Optimized for
area, power, and/or speed (static timing or number of logic levels).
}%
\only<7>{
\begin{itemize}
\item Read and process (most of) modern Verilog-2005 code.
\item Perform all kinds of operations on netlist (RTL, Logic, Gate).
-\item Perform logic optimiziations and gate mapping with ABC\footnote[frame]{\url{http://www.eecs.berkeley.edu/~alanmi/abc/}}.
+\item Perform logic optimizations and gate mapping with ABC\footnote[frame]{\url{http://www.eecs.berkeley.edu/~alanmi/abc/}}.
\end{itemize}
\bigskip
\subsection{Yosys Data- and Control-Flow}
\begin{frame}{\subsecname}
- A (usually short) synthesis script controlls Yosys.
+ A (usually short) synthesis script controls Yosys.
This scripts contain three types of commands:
\begin{itemize}
\subsection{Verification of Yosys}
\begin{frame}{\subsecname}
-Contiously checking the correctness of Yosys and making sure that new features
+Continuously checking the correctness of Yosys and making sure that new features
do not break old ones is a high priority in Yosys.
\bigskip
\begin{frame}{\subsecname{} -- yosys-bigsim}
yosys-bigsim is a collection of real-world open-source Verilog designs and test
-benches. yosys-bigsim compares the testbench outpus of simulations of the original
+benches. yosys-bigsim compares the testbench outputs of simulations of the original
Verilog code and synthesis results.
\bigskip
\begin{frame}{\subsecname}
\begin{itemize}
\item Cost (also applies to ``free as in free beer'' solutions)
-\item Availablity and Reproducability
+\item Availability and Reproducibility
\item Framework- and all-in-one-aspects
\item Educational Tool
\end{itemize}
ASIC flows are an important enabler for ASIC-level Open Source Hardware.
\bigskip
-\item Availablity and Reproducability: \smallskip\par
+\item Availability and Reproducibility: \smallskip\par
If you are a researcher who is publishing, you want to use tools that everyone
else can also use. Even if most universities have access to all major
commercial tools, you usually do not have easy access to the version that was
\bigskip
\item All-in-one: \smallskip\par
-Because of the framework characterisitcs of Yosys, an increasing number of features
+Because of the framework characteristics of Yosys, an increasing number of features
become available in one tool. Yosys not only can be used for circuit synthesis but
-also for formal equivialence checking, SAT solving, and for circuit analysis, to
+also for formal equivalence checking, SAT solving, and for circuit analysis, to
name just a few other application domains. With proprietary software one needs to
learn a new tool for each of this applications.
\end{itemize}
\begin{frame}{\subsecname{} -- 3/3}
\begin{itemize}
\item Educational Tool: \smallskip\par
-Propritaery synthesis tools are at times very secretive about their inner
+Proprietary synthesis tools are at times very secretive about their inner
workings. They often are ``black boxes''. Yosys is very open about its
internals and it is easy to observe the different steps of synthesis.
\end{itemize}
\begin{itemize}
\item Synthesis of final production designs
\item Pre-production synthesis (trial runs before investing in other tools)
-\item Convertion of full-featured Verilog to simple Verilog
-\item Convertion of Verilog to other formats (BLIF, BTOR, etc)
+\item Conversion of full-featured Verilog to simple Verilog
+\item Conversion of Verilog to other formats (BLIF, BTOR, etc)
\item Demonstrating synthesis algorithms (e.g. for educational purposes)
\item Framework for experimenting with new algorithms
\item Framework for building custom flows\footnote[frame]{Not limited to synthesis
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{Documentation, Downloads, Contatcs}
+\subsection{Documentation, Downloads, Contacts}
\begin{frame}{\subsecname}
\begin{itemize}
\smallskip\hskip1cm\url{http://www.clifford.at/yosys/}
\bigskip
-\item Manual, Command Reference, Appliction Notes: \\
+\item Manual, Command Reference, Application Notes: \\
\smallskip\hskip1cm\url{http://www.clifford.at/yosys/documentation.html}
\bigskip
\begin{frame}{\subsecname}
The RTLIL data structures are simple structs utilizing {\tt pool<>} and
-{\tt dict<>} containers (drop-in replacementments for {\tt
+{\tt dict<>} containers (drop-in replacements for {\tt
std::unordered\_set<>} and {\tt std::unordered\_map<>}).
\bigskip
\item Use {\tt module->fixup\_ports()} after changing the {\tt port\_*} properties of wires.
-\item You can safely remove cells or change the {\tt connetions} property of a cell, but be careful when
+\item You can safely remove cells or change the {\tt connections} property of a cell, but be careful when
changing the size of the {\tt SigSpec} connected to a cell port.
\item Use the {\tt SigMap} helper class (see next slide) when you need a unique handle for each signal bit.
use the specified ABC script file instead of the default script.
if <file> starts with a plus sign (+), then the rest of the filename
- string is interprated as the command string to be passed to ABC. the
+ string is interpreted as the command string to be passed to ABC. The
leading plus sign is removed and all commas (,) in the string are
replaced with blanks before the string is passed to ABC.
-keepff
set the "keep" attribute on flip-flop output wires. (and thus preserve
- them, for example for equivialence checking.)
+ them, for example for equivalence checking.)
-nocleanup
when this option is used, the temporary files created by this pass
cd <cellname>
When no module with the specified name is found, but there is a cell
-with the specified name in the current module, then this is equivialent
+with the specified name in the current module, then this is equivalent
to 'cd <celltype>'.
cd ..
\begin{lstlisting}[numbers=left,frame=single]
connect [-nomap] [-nounset] -set <lhs-expr> <rhs-expr>
-Create a connection. This is equivialent to adding the statement 'assign
-<lhs-expr> = <rhs-expr>;' to the verilog input. Per default, all existing
+Create a connection. This is equivalent to adding the statement 'assign
+<lhs-expr> = <rhs-expr>;' to the Verilog input. Per default, all existing
drivers for <lhs-expr> are unconnected. This can be overwritten by using
the -nounset option.
Wrappers are used in coarse-grain synthesis to wrap cells with smaller ports
in wrapper cells with a (larger) constant port size. I.e. the upper bits
-of the wrapper outut are signed/unsigned bit extended. This command uses this
-knowlege to rewire the inputs of the driven cells to match the output of
+of the wrapper output are signed/unsigned bit extended. This command uses this
+knowledge to rewire the inputs of the driven cells to match the output of
the driving cell.
-signed <cell_type> <port_name> <width_param>
design -copy-to <name> [-as <new_mod_name>] [selection]
-Copy modules from the current design into the soecified one.
+Copy modules from the current design into the specified one.
\end{lstlisting}
\section{dff2dffe -- transform \$dff cells to \$dffe cells}
<external_gate_type> is the cell type name for a cell with an
identical interface to the <internal_gate_type>, except it
also has an high-active enable port 'E'.
- Usually <external_gate_type> is an intemediate cell type
+ Usually <external_gate_type> is an intermediate cell type
that is then translated to the final type using 'techmap'.
\end{lstlisting}
Do not match cells or signals that match the names in the file.
-encfile <file>
- Match FSM encodings using the desiption from the file.
+ Match FSM encodings using the description from the file.
See 'help fsm_recode' for details.
Note: The circuit created by this command is not a miter (with something like
signal path at that wire.
-shared
- only expose those signals that are shared ammong the selected modules.
- this is useful for preparing modules for equivialence checking.
+ only expose those signals that are shared among the selected modules.
+ this is useful for preparing modules for equivalence checking.
-evert
also turn connections to instances of other modules to additional
This pass looks for subcircuits that are isomorphic to any of the modules
in the given map file and replaces them with instances of this modules. The
-map file can be a verilog source file (*.v) or an ilang file (*.il).
+map file can be a Verilog source file (*.v) or an ilang file (*.il).
-map <map_file>
use the modules in this file as reference. This option can be used
match. This option can be used multiple times.
-swap <needle_type> <port1>,<port2>[,...]
- Register a set of swapable ports for a needle cell type.
+ Register a set of swappable ports for a needle cell type.
This option can be used multiple times.
-perm <needle_type> <port1>,<port2>[,...] <portA>,<portB>[,...]
- Register a valid permutation of swapable ports for a needle
+ Register a valid permutation of swappable ports for a needle
cell type. This option can be used multiple times.
-cell_attr <attribute_name>
-ignore_param <cell_type> <parameter_name>
Do not use this parameter when matching cells.
-This pass does not operate on modules with uprocessed processes in it.
+This pass does not operate on modules with unprocessed processes in it.
(I.e. the 'proc' pass should be used first to convert processes to netlists.)
This pass can also be used for mining for frequent subcircuits. In this mode
flatten [selection]
This pass flattens the design by replacing cells by their implementation. This
-pass is very simmilar to the 'techmap' pass. The only difference is that this
+pass is very similar to the 'techmap' pass. The only difference is that this
pass is using the current design as mapping library.
\end{lstlisting}
freduce [options] [selection]
This pass performs functional reduction in the circuit. I.e. if two nodes are
-equivialent, they are merged to one node and one of the redundant drivers is
+equivalent, they are merged to one node and one of the redundant drivers is
disconnected. A subsequent call to 'clean' will remove the redundant drivers.
-v, -vv
operation. this is mostly used for debugging the freduce command.
This pass is undef-aware, i.e. it considers don't-care values for detecting
-equivialent nodes.
+equivalent nodes.
All selected wires are considered for rewiring. The selected cells cover the
circuit that is analyzed.
fsm [options] [selection]
This pass calls all the other fsm_* passes in a useful order. This performs
-FSM extraction and optimiziation. It also calls opt_clean as needed:
+FSM extraction and optimization. It also calls opt_clean as needed:
fsm_detect unless got option -nodetect
fsm_extract
-expand, -norecode, -export, -nomap
enable or disable passes as indicated above
- -encoding tye
+ -encoding type
-fm_set_fsm_file file
-encfile file
passed through to fsm_recode pass
The fsm_extract pass is conservative about the cells that belong to a finite
state machine. This pass can be used to merge additional auxiliary gates into
-the finate state machine.
+the finite state machine.
\end{lstlisting}
\section{fsm\_export -- exporting FSMs to KISS2 files}
Input ports are specified with the 'i' prefix, output ports with the 'o'
prefix and inout ports with the 'io' prefix. The optional <num> specifies
-the position of the port in the parameter list (needed when instanciated
+the position of the port in the parameter list (needed when instantiated
using positional arguments). When <num> is not specified, the <portname> can
also contain wildcard characters.
ports 1 1 # number of ports in each group
wrmode 1 0 # set to '1' if this groups is write ports
enable 4 0 # number of enable bits (for write ports)
- transp 0 2 # transparatent (for read ports)
+ transp 0 2 # transparent (for read ports)
clocks 1 2 # clock configuration
clkpol 2 2 # clock polarity configuration
endbram
greater than 1 share the same configuration bit.
Using the same bram name in different bram blocks will create different variants
-of the bram. Verilog configration parameters for the bram are created as needed.
+of the bram. Verilog configuration parameters for the bram are created as needed.
It is also possible to create variants by repeating statements in the bram block
and appending '@<label>' to the individual statements.
dcells ....... number of cells in 'data-direction'
cells ........ total number of cells (acells*dcells*dups)
-The interface for the created bram instances is dervived from the bram
+The interface for the created bram instances is derived from the bram
description. Use 'techmap' to convert the created bram instances into
instances of the actual bram cells of your target architecture.
\begin{lstlisting}[numbers=left,frame=single]
miter -equiv [options] gold_name gate_name miter_name
-Creates a miter circuit for equivialence checking. The gold- and gate- modules
+Creates a miter circuit for equivalence checking. The gold- and gate- modules
must have the same interfaces. The miter circuit will have all inputs of the
two source modules, prefixed with 'in_'. The miter circuit has a 'trigger'
output that goes high if an output mismatch between the two source modules is
\begin{lstlisting}[numbers=left,frame=single]
proc_init [selection]
-This pass extracts the 'init' actions from processes (generated from verilog
+This pass extracts the 'init' actions from processes (generated from Verilog
'initial' blocks) and sets the initial value to the 'init' attribute on the
respective wire.
\end{lstlisting}
set the specified attribute (to the value 1) on all loaded modules
\end{lstlisting}
-\section{read\_verilog -- read modules from verilog file}
+\section{read\_verilog -- read modules from Verilog file}
\label{cmd:read_verilog}
\begin{lstlisting}[numbers=left,frame=single]
read_verilog [options] [filename]
-Load modules from a verilog file to the current design. A large subset of
+Load modules from a Verilog file to the current design. A large subset of
Verilog-2005 is supported.
-sv
dump abstract syntax tree (after simplification)
-dump_vlog
- dump ast as verilog code (after simplification)
+ dump ast as Verilog code (after simplification)
-yydebug
enable parser debug output
module or register.
-ppdump
- dump verilog code after pre-processor
+ dump Verilog code after pre-processor
-nopp
do not run the pre-processor
Note that the Verilog frontend does a pretty good job of processing valid
verilog input, but has not very good error reporting. It generally is
-recommended to use a simulator (for example icarus verilog) for checking
+recommended to use a simulator (for example Icarus Verilog) for checking
the syntax of the code, rather than to rely on read_verilog for that.
\end{lstlisting}
is passed, a temporal induction proof is performed.
-tempinduct
- Perform a temporal induction proof. In a temporalinduction proof it is
+ Perform a temporal induction proof. In a temporal induction proof it is
proven that the condition holds forever after the number of time steps
specified using -seq.
-prove-x <signal> <value>
Like -prove, but an undef (x) bit in the lhs matches any value on
- the right hand side. Useful for equivialence checking.
+ the right hand side. Useful for equivalence checking.
-prove-asserts
Prove that all asserts in the design hold.
like %d but swap the roles of two top sets on the stack
%c
- create a copy of the top set rom the stack and push it
+ create a copy of the top set from the stack and push it
%x[<num1>|*][.<num2>][:<rule>[:<rule>..]]
expand top set <num1> num times according to the specified rules.
%ci[<num1>|*][.<num2>][:<rule>[:<rule>..]]
%co[<num1>|*][.<num2>][:<rule>[:<rule>..]]
- simmilar to %x, but only select input (%ci) or output cones (%co)
+ similar to %x, but only select input (%ci) or output cones (%co)
%a
expand top set by selecting all wires that are (at least in part)
\begin{lstlisting}[numbers=left,frame=single]
share [options] [selection]
-This pass merges shareable resources into a single resource. A SAT solver
+This pass merges sharable resources into a single resource. A SAT solver
is used to determine if two resources are share-able.
-force
-fast
Only consider the simple part of the control logic in SAT solving, resulting
- in much easier SAT problems at the cost of maybe missing some oportunities
+ in much easier SAT problems at the cost of maybe missing some opportunities
for resource sharing.
-limit N
-colors <seed>
Randomly assign colors to the wires. The integer argument is the seed
for the random number generator. Change the seed value if the colored
- graph still is ambigous. A seed of zero deactivates the coloring.
+ graph still is ambiguous. A seed of zero deactivates the coloring.
-colorattr <attribute_name>
Use the specified attribute to assign colors. A unique color is
annotate busses with a label indicating the width of the bus.
-signed
- mark ports (A, B) that are declarted as signed (using the [AB]_SIGNED
+ mark ports (A, B) that are declared as signed (using the [AB]_SIGNED
cell parameter) with an asterisk next to the port name.
-stretch
enumerate objects with internal ($-prefixed) names
-long
- do not abbeviate objects with internal ($-prefixed) names
+ do not abbreviate objects with internal ($-prefixed) names
-notitle
do not add the module name as graph title to the dot file
This command adds $slice and $concat cells to the design to make the splicing
of multi-bit signals explicit. This for example is useful for coarse grain
-synthesis, where dedidacted hardware is needed to splice signals.
+synthesis, where dedicated hardware is needed to splice signals.
-sel_by_cell
only select the cell ports to rewire by the cell. if the selection
The tcl command 'yosys -import' can be used to import all yosys
commands directly as tcl commands to the tcl shell. The yosys
command 'proc' is wrapped using the tcl command 'procs' in order
-to avoid a name collision with the tcl builting command 'proc'.
+to avoid a name collision with the tcl builtin command 'proc'.
\end{lstlisting}
\section{techmap -- generic technology mapper}
techmap [-map filename] [selection]
This pass implements a very simple technology mapper that replaces cells in
-the design with implementations given in form of a verilog or ilang source
+the design with implementations given in form of a Verilog or ilang source
file.
-map filename
-recursive
instead of the iterative breadth-first algorithm use a recursive
- depth-first algorithm. both methods should yield equivialent results,
+ depth-first algorithm. both methods should yield equivalent results,
but may differ in performance.
-autoproc
as final cell types by this mode.
-D <define>, -I <incdir>
- this options are passed as-is to the verilog frontend for loading the
- map file. Note that the verilog frontend is also called with the
+ this options are passed as-is to the Verilog frontend for loading the
+ map file. Note that the Verilog frontend is also called with the
'-ignore_redef' option set.
When a module in the map file has the 'techmap_celltype' attribute set, it will
of constant inputs and shorted inputs at this point and import the
constant and connected bits into the map module. All further commands
are executed in this copy. This is a very convenient way of creating
- optimizied specializations of techmap modules without using the special
+ optimized specializations of techmap modules without using the special
parameters described below.
A _TECHMAP_DO_* command may start with the special token 'RECURSION; '.
constant value.
A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name
-of the cell that is beeing replaced.
+of the cell that is being replaced.
See 'help extract' for a pass that does the opposite thing.
See 'help flatten' for a pass that does flatten the design (which is
-esentially techmap but using the design itself as map library).
+essentially techmap but using the design itself as map library).
\end{lstlisting}
\section{tee -- redirect command output to file}
\begin{lstlisting}[numbers=left,frame=single]
test_autotb [options] [filename]
-Automatically create primitive verilog test benches for all modules in the
+Automatically create primitive Verilog test benches for all modules in the
design. The generated testbenches toggle the input pins of the module in
a semi-random manner and dumps the resulting output signals.
low in order to explore more inner states in a state machine.
-n <int>
- number of iterations the test bench shuld run (default = 1000)
+ number of iterations the test bench should run (default = 1000)
\end{lstlisting}
\section{test\_cell -- automatically test the implementation of a cell type}
print additional debug information to the console
-vlog {filename}
- create a verilog test bench to test simlib and write_verilog
+ create a Verilog test bench to test simlib and write_verilog
\end{lstlisting}
\section{trace -- redirect command output to file}
verific -import [-gates] {-all | <top-module>..}
-Elaborate the design for the sepcified top modules, import to Yosys and
+Elaborate the design for the specified top modules, import to Yosys and
reset the internal state of Verific. A gate-level netlist is created
when called with -gates.
\begin{lstlisting}[numbers=left,frame=single]
verilog_defaults -add [options]
-Add the sepcified options to the list of default options to read_verilog.
+Add the specified options to the list of default options to read_verilog.
verilog_defaults -clear
-Clear the list of verilog default options.
+Clear the list of Verilog default options.
verilog_defaults -push verilog_defaults -pop
\begin{lstlisting}[numbers=left,frame=single]
write_file [options] output_file [input_file]
-Write the text fron the input file to the output file.
+Write the text from the input file to the output file.
-a
Append to output file (instead of overwriting)
set the specified module as design top module
\end{lstlisting}
-\section{write\_verilog -- write design to verilog file}
+\section{write\_verilog -- write design to Verilog file}
\label{cmd:write_verilog}
\begin{lstlisting}[numbers=left,frame=single]
write_verilog [options] [filename]
-Write the current design to a verilog file.
+Write the current design to a Verilog file.
-norename
without this option all internal object names (the ones with a dollar
with this option attributes are included as comments in the output
-noexpr
- without this option all internal cells are converted to verilog
+ without this option all internal cells are converted to Verilog
expressions.
-blackboxes
% (i.e. run "sudo su" and then execute the commands in the root
% shell, don't just prefix the commands with "sudo").
-% formats the text accourding the set language
+% formats the text according the set language
\usepackage[english]{babel}
\usepackage[table,usenames]{xcolor}
% generates indices with the "\index" command
% (i.e. run "sudo su" and then execute the commands in the root
% shell, don't just prefix the commands with "sudo").
-% formats the text accourding the set language
+% formats the text according the set language
\usepackage[english]{babel}
\usepackage{amsmath}
\usepackage{multirow}
\bigskip
This presentation covers basic concepts of Yosys, writing synthesis scripts
for a wide range of applications, creating Yosys scripts for various
-non-synthesis applications (such as formal equivialence checking) and
+non-synthesis applications (such as formal equivalence checking) and
writing extensions to Yosys using the C++ API.
\end{frame}
log("\n");
log("This pass identifies the following problems in the current design:\n");
log("\n");
- log(" - combinatorical loops\n");
+ log(" - combinatorial loops\n");
log("\n");
log(" - two or more conflicting drivers for one wire\n");
log("\n");
log("\n");
log(" connect [-nomap] [-nounset] -set <lhs-expr> <rhs-expr>\n");
log("\n");
- log("Create a connection. This is equivialent to adding the statement 'assign\n");
+ log("Create a connection. This is equivalent to adding the statement 'assign\n");
log("<lhs-expr> = <rhs-expr>;' to the verilog input. Per default, all existing\n");
log("drivers for <lhs-expr> are unconnected. This can be overwritten by using\n");
log("the -nounset option.\n");
log("\n");
log("Wrappers are used in coarse-grain synthesis to wrap cells with smaller ports\n");
log("in wrapper cells with a (larger) constant port size. I.e. the upper bits\n");
- log("of the wrapper outut are signed/unsigned bit extended. This command uses this\n");
- log("knowlege to rewire the inputs of the driven cells to match the output of\n");
+ log("of the wrapper output are signed/unsigned bit extended. This command uses this\n");
+ log("knowledge to rewire the inputs of the driven cells to match the output of\n");
log("the driving cell.\n");
log("\n");
log(" -signed <cell_type> <port_name> <width_param>\n");
log("\n");
log(" design -copy-to <name> [-as <new_mod_name>] [selection]\n");
log("\n");
- log("Copy modules from the current design into the soecified one.\n");
+ log("Copy modules from the current design into the specified one.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
log("\n");
log(" %%ci[<num1>|*][.<num2>][:<rule>[:<rule>..]]\n");
log(" %%co[<num1>|*][.<num2>][:<rule>[:<rule>..]]\n");
- log(" simmilar to %%x, but only select input (%%ci) or output cones (%%co)\n");
+ log(" similar to %%x, but only select input (%%ci) or output cones (%%co)\n");
log("\n");
log(" %%xe[...] %%cie[...] %%coe\n");
log(" like %%x, %%ci, and %%co but only consider combinatorial cells\n");
log(" cd <cellname>\n");
log("\n");
log("When no module with the specified name is found, but there is a cell\n");
- log("with the specified name in the current module, then this is equivialent\n");
+ log("with the specified name in the current module, then this is equivalent\n");
log("to 'cd <celltype>'.\n");
log("\n");
log(" cd ..\n");
log(" -colors <seed>\n");
log(" Randomly assign colors to the wires. The integer argument is the seed\n");
log(" for the random number generator. Change the seed value if the colored\n");
- log(" graph still is ambigous. A seed of zero deactivates the coloring.\n");
+ log(" graph still is ambiguous. A seed of zero deactivates the coloring.\n");
log("\n");
log(" -colorattr <attribute_name>\n");
log(" Use the specified attribute to assign colors. A unique color is\n");
log(" annotate busses with a label indicating the width of the bus.\n");
log("\n");
log(" -signed\n");
- log(" mark ports (A, B) that are declarted as signed (using the [AB]_SIGNED\n");
+ log(" mark ports (A, B) that are declared as signed (using the [AB]_SIGNED\n");
log(" cell parameter) with an asterisk next to the port name.\n");
log("\n");
log(" -stretch\n");
log(" enumerate objects with internal ($-prefixed) names\n");
log("\n");
log(" -long\n");
- log(" do not abbeviate objects with internal ($-prefixed) names\n");
+ log(" do not abbreviate objects with internal ($-prefixed) names\n");
log("\n");
log(" -notitle\n");
log(" do not add the module name as graph title to the dot file\n");
bool flag_stretch = false;
bool flag_pause = false;
bool flag_enum = false;
- bool flag_abbeviate = true;
+ bool flag_abbreviate = true;
bool flag_notitle = false;
RTLIL::IdString colorattr;
}
if (arg == "-enum") {
flag_enum = true;
- flag_abbeviate = false;
+ flag_abbreviate = false;
continue;
}
if (arg == "-long") {
flag_enum = false;
- flag_abbeviate = false;
+ flag_abbreviate = false;
continue;
}
if (arg == "-notitle") {
delete lib;
log_cmd_error("Can't open dot file `%s' for writing.\n", dot_file.c_str());
}
- ShowWorker worker(f, design, libs, colorSeed, flag_width, flag_signed, flag_stretch, flag_enum, flag_abbeviate, flag_notitle, color_selections, label_selections, colorattr);
+ ShowWorker worker(f, design, libs, colorSeed, flag_width, flag_signed, flag_stretch, flag_enum, flag_abbreviate, flag_notitle, color_selections, label_selections, colorattr);
fclose(f);
for (auto lib : libs)
log("\n");
log("This command adds $slice and $concat cells to the design to make the splicing\n");
log("of multi-bit signals explicit. This for example is useful for coarse grain\n");
- log("synthesis, where dedidacted hardware is needed to splice signals.\n");
+ log("synthesis, where dedicated hardware is needed to splice signals.\n");
log("\n");
log(" -sel_by_cell\n");
log(" only select the cell ports to rewire by the cell. if the selection\n");
log("\n");
log(" write_file [options] output_file [input_file]\n");
log("\n");
- log("Write the text fron the input file to the output file.\n");
+ log("Write the text from the input file to the output file.\n");
log("\n");
log(" -a\n");
log(" Append to output file (instead of overwriting)\n");
log(" Do not match cells or signals that match the names in the file.\n");
log("\n");
log(" -encfile <file>\n");
- log(" Match FSM encodings using the desiption from the file.\n");
+ log(" Match FSM encodings using the description from the file.\n");
log(" See 'help fsm_recode' for details.\n");
log("\n");
log("Note: The circuit created by this command is not a miter (with something like\n");
log(" fsm [options] [selection]\n");
log("\n");
log("This pass calls all the other fsm_* passes in a useful order. This performs\n");
- log("FSM extraction and optimiziation. It also calls opt_clean as needed:\n");
+ log("FSM extraction and optimization. It also calls opt_clean as needed:\n");
log("\n");
log(" fsm_detect unless got option -nodetect\n");
log(" fsm_extract\n");
log(" -expand, -norecode, -export, -nomap\n");
log(" enable or disable passes as indicated above\n");
log("\n");
- log(" -encoding tye\n");
+ log(" -encoding type\n");
log(" -fm_set_fsm_file file\n");
log(" -encfile file\n");
log(" passed through to fsm_recode pass\n");
log("\n");
log("The fsm_extract pass is conservative about the cells that belong to a finite\n");
log("state machine. This pass can be used to merge additional auxiliary gates into\n");
- log("the finate state machine.\n");
+ log("the finite state machine.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
log("\n");
log("Input ports are specified with the 'i' prefix, output ports with the 'o'\n");
log("prefix and inout ports with the 'io' prefix. The optional <num> specifies\n");
- log("the position of the port in the parameter list (needed when instanciated\n");
+ log("the position of the port in the parameter list (needed when instantiated\n");
log("using positional arguments). When <num> is not specified, the <portname> can\n");
log("also contain wildcard characters.\n");
log("\n");
mapped_wr_port:;
}
- // houskeeping stuff for growing more read ports and restarting read port assignments
+ // housekeeping stuff for growing more read ports and restarting read port assignments
int grow_read_ports_cursor = -1;
bool try_growing_more_read_ports = false;
pi.make_transp = true;
enable_make_transp = true;
} else {
- log(" Bram port %c%d.%d has incompatible read transparancy.\n", pi.group + 'A', pi.index + 1, pi.dupidx + 1);
+ log(" Bram port %c%d.%d has incompatible read transparency.\n", pi.group + 'A', pi.index + 1, pi.dupidx + 1);
goto skip_bram_rport;
}
}
log(" ports 1 1 # number of ports in each group\n");
log(" wrmode 1 0 # set to '1' if this groups is write ports\n");
log(" enable 4 0 # number of enable bits (for write ports)\n");
- log(" transp 0 2 # transparatent (for read ports)\n");
+ log(" transp 0 2 # transparent (for read ports)\n");
log(" clocks 1 2 # clock configuration\n");
log(" clkpol 2 2 # clock polarity configuration\n");
log(" endbram\n");
log("greater than 1 share the same configuration bit.\n");
log("\n");
log("Using the same bram name in different bram blocks will create different variants\n");
- log("of the bram. Verilog configration parameters for the bram are created as needed.\n");
+ log("of the bram. Verilog configuration parameters for the bram are created as needed.\n");
log("\n");
log("It is also possible to create variants by repeating statements in the bram block\n");
log("and appending '@<label>' to the individual statements.\n");
log(" dcells ....... number of cells in 'data-direction'\n");
log(" cells ........ total number of cells (acells*dcells*dups)\n");
log("\n");
- log("The interface for the created bram instances is dervived from the bram\n");
+ log("The interface for the created bram instances is derived from the bram\n");
log("description. Use 'techmap' to convert the created bram instances into\n");
log("instances of the actual bram cells of your target architecture.\n");
log("\n");
did_something = false;
// merge trees of reduce_* cells to one single cell and unify input vectors
- // (only handle recduce_and and reduce_or for various reasons)
+ // (only handle reduce_and and reduce_or for various reasons)
const char *type_list[] = { "$reduce_or", "$reduce_and" };
for (auto type : type_list)
log("\n");
log(" -fast\n");
log(" Only consider the simple part of the control logic in SAT solving, resulting\n");
- log(" in much easier SAT problems at the cost of maybe missing some oportunities\n");
+ log(" in much easier SAT problems at the cost of maybe missing some opportunities\n");
log(" for resource sharing.\n");
log("\n");
log(" -limit N\n");
BruteForceEquivChecker(RTLIL::Module *mod1, RTLIL::Module *mod2, bool ignore_x_mod1) :
mod1(mod1), mod2(mod2), counter(0), errors(0), ignore_x_mod1(ignore_x_mod1)
{
- log("Checking for equivialence (brute-force): %s vs %s\n", mod1->name.c_str(), mod2->name.c_str());
+ log("Checking for equivalence (brute-force): %s vs %s\n", mod1->name.c_str(), mod2->name.c_str());
for (auto &w : mod1->wires_)
{
RTLIL::Wire *wire1 = w.second;
log_error("Can't find module `%s'!\n", mod2_name.c_str());
BruteForceEquivChecker checker(design->modules_.at(mod1_name), design->modules_.at(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x");
if (checker.errors > 0)
- log_cmd_error("Modules are not equivialent!\n");
+ log_cmd_error("Modules are not equivalent!\n");
log("Verified %s = %s (using brute-force check on %d cases).\n",
mod1_name.c_str(), mod2_name.c_str(), checker.counter);
return;
log("\n");
if (undef.size() > 0) {
undef.sort_and_unify();
- log("Assumend undef (x) value for the following singals: %s\n\n", log_signal(undef));
+ log("Assumed undef (x) value for the following signals: %s\n\n", log_signal(undef));
}
}
}
log(" signal path at that wire.\n");
log("\n");
log(" -shared\n");
- log(" only expose those signals that are shared ammong the selected modules.\n");
- log(" this is useful for preparing modules for equivialence checking.\n");
+ log(" only expose those signals that are shared among the selected modules.\n");
+ log(" this is useful for preparing modules for equivalence checking.\n");
log("\n");
log(" -evert\n");
log(" also turn connections to instances of other modules to additional\n");
out_depth[idx] = std::numeric_limits<int>::max();
if (verbose_level >= 1) {
- log("%s Found %d equivialent signals:", indt, int(bucket.size()));
+ log("%s Found %d equivalent signals:", indt, int(bucket.size()));
for (int idx : bucket)
log("%s%s%s", idx == bucket.front() ? " " : ", ", out_inverted[idx] ? "~" : "", log_signal(out_bits[idx]));
log("\n");
std::vector<RTLIL::SigBit> r_sigbits;
for (int idx : r)
r_sigbits.push_back(out_bits[idx]);
- log(" Found group of %d equivialent signals: %s\n", int(r.size()), log_signal(r_sigbits));
+ log(" Found group of %d equivalent signals: %s\n", int(r.size()), log_signal(r_sigbits));
}
std::vector<int> undef_slaves;
if (!dump_prefix.empty())
dump();
- log(" Rewiring %d equivialent groups:\n", int(equiv.size()));
+ log(" Rewiring %d equivalent groups:\n", int(equiv.size()));
int rewired_sigbits = 0;
for (auto &grp : equiv)
{
log(" freduce [options] [selection]\n");
log("\n");
log("This pass performs functional reduction in the circuit. I.e. if two nodes are\n");
- log("equivialent, they are merged to one node and one of the redundant drivers is\n");
+ log("equivalent, they are merged to one node and one of the redundant drivers is\n");
log("disconnected. A subsequent call to 'clean' will remove the redundant drivers.\n");
log("\n");
log(" -v, -vv\n");
log(" operation. this is mostly used for debugging the freduce command.\n");
log("\n");
log("This pass is undef-aware, i.e. it considers don't-care values for detecting\n");
- log("equivialent nodes.\n");
+ log("equivalent nodes.\n");
log("\n");
log("All selected wires are considered for rewiring. The selected cells cover the\n");
log("circuit that is analyzed.\n");
log("\n");
log(" miter -equiv [options] gold_name gate_name miter_name\n");
log("\n");
- log("Creates a miter circuit for equivialence checking. The gold- and gate- modules\n");
+ log("Creates a miter circuit for equivalence checking. The gold- and gate- modules\n");
log("must have the same interfaces. The miter circuit will have all inputs of the\n");
log("two source modules, prefixed with 'in_'. The miter circuit has a 'trigger'\n");
log("output that goes high if an output mismatch between the two source modules is\n");
log("\n");
log(" -prove-x <signal> <value>\n");
log(" Like -prove, but an undef (x) bit in the lhs matches any value on\n");
- log(" the right hand side. Useful for equivialence checking.\n");
+ log(" the right hand side. Useful for equivalence checking.\n");
log("\n");
log(" -prove-asserts\n");
log(" Prove that all asserts in the design hold.\n");
log(" use the specified ABC script file instead of the default script.\n");
log("\n");
log(" if <file> starts with a plus sign (+), then the rest of the filename\n");
- log(" string is interprated as the command string to be passed to ABC. the\n");
+ log(" string is interpreted as the command string to be passed to ABC. The\n");
log(" leading plus sign is removed and all commas (,) in the string are\n");
log(" replaced with blanks before the string is passed to ABC.\n");
log("\n");
log("\n");
log(" -keepff\n");
log(" set the \"keep\" attribute on flip-flop output wires. (and thus preserve\n");
- log(" them, for example for equivialence checking.)\n");
+ log(" them, for example for equivalence checking.)\n");
log("\n");
log(" -nocleanup\n");
log(" when this option is used, the temporary files created by this pass\n");
log(" <external_gate_type> is the cell type name for a cell with an\n");
log(" identical interface to the <internal_gate_type>, except it\n");
log(" also has an high-active enable port 'E'.\n");
- log(" Usually <external_gate_type> is an intemediate cell type\n");
+ log(" Usually <external_gate_type> is an intermediate cell type\n");
log(" that is then translated to the final type using 'techmap'.\n");
log("\n");
log(" -direct-match <pattern>\n");
log(" match. This option can be used multiple times.\n");
log("\n");
log(" -swap <needle_type> <port1>,<port2>[,...]\n");
- log(" Register a set of swapable ports for a needle cell type.\n");
+ log(" Register a set of swappable ports for a needle cell type.\n");
log(" This option can be used multiple times.\n");
log("\n");
log(" -perm <needle_type> <port1>,<port2>[,...] <portA>,<portB>[,...]\n");
- log(" Register a valid permutation of swapable ports for a needle\n");
+ log(" Register a valid permutation of swappable ports for a needle\n");
log(" cell type. This option can be used multiple times.\n");
log("\n");
log(" -cell_attr <attribute_name>\n");
log(" -ignore_param <cell_type> <parameter_name>\n");
log(" Do not use this parameter when matching cells.\n");
log("\n");
- log("This pass does not operate on modules with uprocessed processes in it.\n");
+ log("This pass does not operate on modules with unprocessed processes in it.\n");
log("(I.e. the 'proc' pass should be used first to convert processes to netlists.)\n");
log("\n");
log("This pass can also be used for mining for frequent subcircuits. In this mode\n");
log(" techmap [-map filename] [selection]\n");
log("\n");
log("This pass implements a very simple technology mapper that replaces cells in\n");
- log("the design with implementations given in form of a verilog or ilang source\n");
+ log("the design with implementations given in form of a Verilog or ilang source\n");
log("file.\n");
log("\n");
log(" -map filename\n");
log("\n");
log(" -recursive\n");
log(" instead of the iterative breadth-first algorithm use a recursive\n");
- log(" depth-first algorithm. both methods should yield equivialent results,\n");
+ log(" depth-first algorithm. both methods should yield equivalent results,\n");
log(" but may differ in performance.\n");
log("\n");
log(" -autoproc\n");
log(" as final cell types by this mode.\n");
log("\n");
log(" -D <define>, -I <incdir>\n");
- log(" this options are passed as-is to the verilog frontend for loading the\n");
- log(" map file. Note that the verilog frontend is also called with the\n");
+ log(" this options are passed as-is to the Verilog frontend for loading the\n");
+ log(" map file. Note that the Verilog frontend is also called with the\n");
log(" '-ignore_redef' option set.\n");
log("\n");
log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
log(" of constant inputs and shorted inputs at this point and import the\n");
log(" constant and connected bits into the map module. All further commands\n");
log(" are executed in this copy. This is a very convenient way of creating\n");
- log(" optimizied specializations of techmap modules without using the special\n");
+ log(" optimized specializations of techmap modules without using the special\n");
log(" parameters described below.\n");
log("\n");
log(" A _TECHMAP_DO_* command may start with the special token 'RECURSION; '.\n");
log("constant value.\n");
log("\n");
log("A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name\n");
- log("of the cell that is beeing replaced.\n");
+ log("of the cell that is being replaced.\n");
log("\n");
log("See 'help extract' for a pass that does the opposite thing.\n");
log("\n");
log("See 'help flatten' for a pass that does flatten the design (which is\n");
- log("esentially techmap but using the design itself as map library).\n");
+ log("essentially techmap but using the design itself as map library).\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
log(" flatten [selection]\n");
log("\n");
log("This pass flattens the design by replacing cells by their implementation. This\n");
- log("pass is very simmilar to the 'techmap' pass. The only difference is that this\n");
+ log("pass is very similar to the 'techmap' pass. The only difference is that this\n");
log("pass is using the current design as mapping library.\n");
log("\n");
log("Cells and/or modules with the 'keep_hiearchy' attribute set will not be\n");
log("low in order to explore more inner states in a state machine.\n");
log("\n");
log(" -n <int>\n");
- log(" number of iterations the test bench shuld run (default = 1000)\n");
+ log(" number of iterations the test bench should run (default = 1000)\n");
log("\n");
}
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
print STDERR "Usage: $0 [-w N] [-d N] gold.vcd gate.vcd\n";
print STDERR "\n";
print STDERR " -w N\n";
- print STDERR " reserve N characters for bitmap in text ouput (default: auto)\n";
+ print STDERR " reserve N characters for bitmap in text output (default: auto)\n";
print STDERR "\n";
print STDERR " -d N\n";
print STDERR " allow for N timesteps delay between gate and gold (default: 0)\n";
projects / yosys.git / commitdiff