add external_core_top.v to build for ulx3s

diff --git a/Makefile b/Makefile
index 88cbdbec3823c0e7deee20d3c16cca7944eddec0..f4dc54d7a5a559c107ae6e90811b1f05250fed80 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -222,6 +222,7 @@ else
                 core_dummy.vhdl
     fpga_files = $(_fpga_files) $(_soc_files)
     synth_files = $(util_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
+    soc_extra_v = external_core_top.v
 endif
 
 GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \