(no commit message)

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index cdc077698e5a8432f1a5435af332c8c331816623..4eee357e4b92e1726738d3522bdce947bdd92721 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -446,4 +446,8 @@ CPUs were about the same rate.  DRAM bitcells *simply cannot exceed
 these rates*, yet the pressure from Software Engineers is to
 make *sequential* algorithm processing faster and faster because
 parallelising of algorithms is simply too difficult to master and always
-has been.
+has been.  Thus whilst DRAM has to go parallel (like RAID Striping) to
+keep up, CPUs are now at 8-way Multi-Issue 5 ghz clock rates and
+are at an astonishing four levels of cache (L1 to L4).  The amount
+of wiring inside such CPUs is now measured in miles.
+