sparc.md (ashlsi3): If shift count is const1_rtx, use add instead of shift.

2002-05-05  Jakub Jelinek  <jakub@redhat.com>

	* config/sparc/sparc.md (ashlsi3): If shift count is const1_rtx,
	use add instead of shift.
	(ashldi3_sp64): Likewise.
	(ashlsi3_const1, ashldi3_const1): Remove.
	* config/sparc/sparc.h (PREDICATE_CODES): Add const1_operand.
	* config/sparc/sparc.c (const1_operand): New.

From-SVN: r53199

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7cf1b73106d09ae2a878f8a4170fcef761428224..fc401c20801cc5f883630e0bd79f3e37cde2c221 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2002-05-05  Jakub Jelinek  <jakub@redhat.com>
+
+       * config/sparc/sparc.md (ashlsi3): If shift count is const1_rtx,
+       use add instead of shift.
+       (ashldi3_sp64): Likewise.
+       (ashlsi3_const1, ashldi3_const1): Remove.
+       * config/sparc/sparc.h (PREDICATE_CODES): Add const1_operand.
+       * config/sparc/sparc.c (const1_operand): New.
+
 2002-05-05  Jason Thorpe  <thorpej@wasabisystems.com>
 
        * config.gcc (alpha*-*-netbsd*): Don't use crtstuff.

diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 57083801688bf599684a6f3e12b6fcbcd0086bce..b28bcf53e8c917a332c10dbaa65722f4f7067bbc 100644 (file)
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -469,6 +469,16 @@ reg_or_0_operand (op, mode)
   return 0;
 }
 
+/* Return non-zero only if OP is const1_rtx.  */
+
+int
+const1_operand (op, mode)
+     rtx op;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  return op == const1_rtx;
+}
+
 /* Nonzero if OP is a floating point value with value 0.0.  */
 
 int

diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index fa1e792b9c1da0f80044b5f9ea17c6d5a3bebedb..073debda1e7fc03947b311ceb1a9a6959a82d855 100644 (file)
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -3018,6 +3018,7 @@ do {                                                                      \
 
 #define PREDICATE_CODES                                                        \
 {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}},          \
+{"const1_operand", {CONST_INT}},                                       \
 {"fp_zero_operand", {CONST_DOUBLE}},                                   \
 {"fp_register_operand", {SUBREG, REG}},                                        \
 {"intreg_operand", {SUBREG, REG}},                                     \

diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index cb0c6654303ed1edde7fbf19e9a9fd60ccf90078..2af9153a0c32e321c36fc897d0bdc78bba7376b3 100644 (file)
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -7245,18 +7245,13 @@
       && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 31)
     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
 
+  if (operands[2] == const1_rtx)
+    return \"add\\t%1, %1, %0\";
   return \"sll\\t%1, %2, %0\";
 }"
-  [(set_attr "type" "shift")])
-
-;; We special case multiplication by two, as add can be done
-;; in both ALUs, while shift only in IEU0 on UltraSPARC.
-(define_insn "*ashlsi3_const1"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-        (ashift:SI (match_operand:SI 1 "register_operand" "r")
-                   (const_int 1)))]
-  ""
-  "add\\t%1, %1, %0")
+  [(set (attr "type")
+       (if_then_else (match_operand 2 "const1_operand" "")
+                     (const_string "ialu") (const_string "shift")))])
 
 (define_expand "ashldi3"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -7274,15 +7269,6 @@
     }
 }")
 
-;; We special case multiplication by two, as add can be done
-;; in both ALUs, while shift only in IEU0 on UltraSPARC.
-(define_insn "*ashldi3_const1"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-       (ashift:DI (match_operand:DI 1 "register_operand" "r")
-                  (const_int 1)))]
-  "TARGET_ARCH64"
-  "add\\t%1, %1, %0")
-
 (define_insn "*ashldi3_sp64"
   [(set (match_operand:DI 0 "register_operand" "=r")
        (ashift:DI (match_operand:DI 1 "register_operand" "r")
@@ -7294,9 +7280,13 @@
       && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 63)
     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
 
+  if (operands[2] == const1_rtx)
+    return \"add\\t%1, %1, %0\";
   return \"sllx\\t%1, %2, %0\";
 }"
-  [(set_attr "type" "shift")])
+  [(set (attr "type")
+       (if_then_else (match_operand 2 "const1_operand" "")
+                     (const_string "ialu") (const_string "shift")))])
 
 ;; XXX UGH!
 (define_insn "ashldi3_v8plus"