(_bfd_mips_elf_print_private_bfd_data): Print ISA name for
MIPS32.
+ * aoutx.h (NAME(aout,machine_type)): Add cases for
+ bfd_mach_mips5 and bfd_mach_mips64.
+ * archures.c (bfd_mach_mips5, bfd_mach_mips64): New constants.
+ * bfd-in2.h (bfd_mach_mips5, bfd_mach_mips64): Likewise.
+ * cpu_mips.c (I_mips5, I_mips64): New definitions.
+ (arch_info_struct): Add entries for bfd_mach_mips5 and
+ bfd_mach_mips64.
+ * elf32-mips.c (elf_mips_isa, elf_mips_mach,
+ _bfd_mips_elf_print_private_bfd_data): Add cases for
+ E_MIPS_ARCH_5 and E_MIPS_ARCH_64.
+ (_bfd_mips_elf_final_write_processing): Add cases for
+ bfd_mach_mips5 and bfd_mach_mips64.
+
2000-12-01 Joel Sherrill <joel@OARcorp.com>
* config.bfd (arm-*-rtems*, a29k-*rtems*): New targets.
case bfd_mach_mips16:
case bfd_mach_mips32:
case bfd_mach_mips32_4k:
+ case bfd_mach_mips5:
+ case bfd_mach_mips64:
/* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc. */
arch_flags = M_MIPS2;
break;
.#define bfd_mach_mips16 16
.#define bfd_mach_mips32 32
.#define bfd_mach_mips32_4k 3204113 {* 32, 04, octal 'K' *}
+.#define bfd_mach_mips5 5
+.#define bfd_mach_mips64 64
. bfd_arch_i386, {* Intel 386 *}
.#define bfd_mach_i386_i386 0
.#define bfd_mach_i386_i8086 1
#define bfd_mach_mips16 16
#define bfd_mach_mips32 32
#define bfd_mach_mips32_4k 3204113 /* 32, 04, octal 'K' */
+#define bfd_mach_mips5 5
+#define bfd_mach_mips64 64
bfd_arch_i386, /* Intel 386 */
#define bfd_mach_i386_i386 0
#define bfd_mach_i386_i8086 1
I_mips16,
I_mips32,
I_mips32_4k,
+ I_mips5,
+ I_mips64,
};
#define NN(index) (&arch_info_struct[(index) + 1])
static const bfd_arch_info_type arch_info_struct[] =
{
- N (32, 32, bfd_mach_mips3000, "mips:3000", false, NN(I_mips3000)),
- N (32, 32, bfd_mach_mips3900, "mips:3900", false, NN(I_mips3900)),
- N (64, 64, bfd_mach_mips4000, "mips:4000", false, NN(I_mips4000)),
- N (64, 64, bfd_mach_mips4010, "mips:4010", false, NN(I_mips4010)),
- N (64, 64, bfd_mach_mips4100, "mips:4100", false, NN(I_mips4100)),
- N (64, 64, bfd_mach_mips4111, "mips:4111", false, NN(I_mips4111)),
- N (64, 64, bfd_mach_mips4300, "mips:4300", false, NN(I_mips4300)),
- N (64, 64, bfd_mach_mips4400, "mips:4400", false, NN(I_mips4400)),
- N (64, 64, bfd_mach_mips4600, "mips:4600", false, NN(I_mips4600)),
- N (64, 64, bfd_mach_mips4650, "mips:4650", false, NN(I_mips4650)),
- N (64, 64, bfd_mach_mips5000, "mips:5000", false, NN(I_mips5000)),
- N (32, 32, bfd_mach_mips6000, "mips:6000", false, NN(I_mips6000)),
- N (64, 64, bfd_mach_mips8000, "mips:8000", false, NN(I_mips8000)),
- N (64, 64, bfd_mach_mips10000,"mips:10000",false, NN(I_mips10000)),
- N (64, 64, bfd_mach_mips16, "mips:16", false, NN(I_mips16)),
- N (32, 32, bfd_mach_mips32, "mips:mips32", false, NN(I_mips32)),
- N (32, 32, bfd_mach_mips32_4k,"mips:mips32-4k", false, 0),
+ N (32, 32, bfd_mach_mips3000, "mips:3000", false, NN(I_mips3000)),
+ N (32, 32, bfd_mach_mips3900, "mips:3900", false, NN(I_mips3900)),
+ N (64, 64, bfd_mach_mips4000, "mips:4000", false, NN(I_mips4000)),
+ N (64, 64, bfd_mach_mips4010, "mips:4010", false, NN(I_mips4010)),
+ N (64, 64, bfd_mach_mips4100, "mips:4100", false, NN(I_mips4100)),
+ N (64, 64, bfd_mach_mips4111, "mips:4111", false, NN(I_mips4111)),
+ N (64, 64, bfd_mach_mips4300, "mips:4300", false, NN(I_mips4300)),
+ N (64, 64, bfd_mach_mips4400, "mips:4400", false, NN(I_mips4400)),
+ N (64, 64, bfd_mach_mips4600, "mips:4600", false, NN(I_mips4600)),
+ N (64, 64, bfd_mach_mips4650, "mips:4650", false, NN(I_mips4650)),
+ N (64, 64, bfd_mach_mips5000, "mips:5000", false, NN(I_mips5000)),
+ N (32, 32, bfd_mach_mips6000, "mips:6000", false, NN(I_mips6000)),
+ N (64, 64, bfd_mach_mips8000, "mips:8000", false, NN(I_mips8000)),
+ N (64, 64, bfd_mach_mips10000,"mips:10000", false, NN(I_mips10000)),
+ N (64, 64, bfd_mach_mips16, "mips:16", false, NN(I_mips16)),
+ N (32, 32, bfd_mach_mips32, "mips:mips32", false, NN(I_mips32)),
+ N (32, 32, bfd_mach_mips32_4k,"mips:mips32-4k", false, NN(I_mips32_4k)),
+ N (64, 64, bfd_mach_mips5, "mips:mips5", false, NN(I_mips5)),
+ N (64, 64, bfd_mach_mips64, "mips:mips64", false, 0),
};
/* The default architecture is mips:3000, but with a machine number of
return 3;
case E_MIPS_ARCH_4:
return 4;
+ case E_MIPS_ARCH_5:
+ return 5;
case E_MIPS_ARCH_32:
return 32;
+ case E_MIPS_ARCH_64:
+ return 64;
}
return 4;
}
return bfd_mach_mips8000;
break;
+ case E_MIPS_ARCH_5:
+ return bfd_mach_mips5;
+ break;
+
case E_MIPS_ARCH_32:
return bfd_mach_mips32;
break;
+
+ case E_MIPS_ARCH_64:
+ return bfd_mach_mips64;
+ break;
}
}
case bfd_mach_mips32_4k:
val = E_MIPS_ARCH_32 | E_MIPS_MACH_MIPS32_4K;
break;
+
+ case bfd_mach_mips5:
+ val = E_MIPS_ARCH_5;
+ break;
+
+ case bfd_mach_mips64:
+ val = E_MIPS_ARCH_64;
+ break;
}
elf_elfheader (abfd)->e_flags &= ~(EF_MIPS_ARCH | EF_MIPS_MACH);
fprintf (file, _(" [mips3]"));
else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_4)
fprintf (file, _(" [mips4]"));
+ else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_5)
+ fprintf (file, _ (" [mips5]"));
else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32)
fprintf (file, _ (" [mips32]"));
+ else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_64)
+ fprintf (file, _ (" [mips64]"));
else
fprintf (file, _(" [unknown ISA]"));
msgid ""
msgstr ""
"Project-Id-Version: PACKAGE VERSION\n"
-"POT-Creation-Date: 2000-12-01 13:12-0800\n"
+"POT-Creation-Date: 2000-12-01 16:44-0800\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <LL@li.org>\n"
msgid "%s: Bad relocation record imported: %d"
msgstr ""
-#: aoutx.h:1256 aoutx.h:1670
+#: aoutx.h:1258 aoutx.h:1672
#, c-format
msgid "%s: can not represent section `%s' in a.out object file format"
msgstr ""
-#: aoutx.h:1640
+#: aoutx.h:1642
#, c-format
msgid ""
"%s: can not represent section for symbol `%s' in a.out object file format"
msgstr ""
-#: aoutx.h:1642
+#: aoutx.h:1644
msgid "*unknown*"
msgstr ""
-#: aoutx.h:3681
+#: aoutx.h:3683
#, c-format
msgid "%s: relocateable link from %s to %s not supported"
msgstr ""
#. Ignore init flag - it may not be set, despite the flags field
#. containing valid data.
-#: elf32-arm.h:2195 elf32-cris.c:615 elf32-m68k.c:430 elf32-mips.c:2632
+#: elf32-arm.h:2195 elf32-cris.c:615 elf32-m68k.c:430 elf32-mips.c:2652
#, c-format
msgid "private flags = %lx:"
msgstr ""
msgid "Linking mips16 objects into %s format is not supported"
msgstr ""
-#: elf32-mips.c:2519
+#: elf32-mips.c:2539
#, c-format
msgid "%s: linking PIC files with non-PIC files"
msgstr ""
-#: elf32-mips.c:2529
+#: elf32-mips.c:2549
#, c-format
msgid "%s: linking abicalls files with non-abicalls files"
msgstr ""
-#: elf32-mips.c:2558
+#: elf32-mips.c:2578
#, c-format
msgid "%s: ISA mismatch (-mips%d) with previous modules (-mips%d)"
msgstr ""
-#: elf32-mips.c:2567
+#: elf32-mips.c:2587
#, c-format
msgid "%s: ISA mismatch (%d) with previous modules (%d)"
msgstr ""
-#: elf32-mips.c:2590
+#: elf32-mips.c:2610
#, c-format
msgid "%s: ABI mismatch: linking %s module with previous %s modules"
msgstr ""
-#: elf32-mips.c:2604 elf32-ppc.c:1481 elf64-sparc.c:2974
+#: elf32-mips.c:2624 elf32-ppc.c:1481 elf64-sparc.c:2974
#, c-format
msgid "%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)"
msgstr ""
-#: elf32-mips.c:2635
+#: elf32-mips.c:2655
msgid " [abi=O32]"
msgstr ""
-#: elf32-mips.c:2637
+#: elf32-mips.c:2657
msgid " [abi=O64]"
msgstr ""
-#: elf32-mips.c:2639
+#: elf32-mips.c:2659
msgid " [abi=EABI32]"
msgstr ""
-#: elf32-mips.c:2641
+#: elf32-mips.c:2661
msgid " [abi=EABI64]"
msgstr ""
-#: elf32-mips.c:2643
+#: elf32-mips.c:2663
msgid " [abi unknown]"
msgstr ""
-#: elf32-mips.c:2645
+#: elf32-mips.c:2665
msgid " [abi=N32]"
msgstr ""
-#: elf32-mips.c:2647
+#: elf32-mips.c:2667
msgid " [abi=64]"
msgstr ""
-#: elf32-mips.c:2649
+#: elf32-mips.c:2669
msgid " [no abi set]"
msgstr ""
-#: elf32-mips.c:2652
+#: elf32-mips.c:2672
msgid " [mips1]"
msgstr ""
-#: elf32-mips.c:2654
+#: elf32-mips.c:2674
msgid " [mips2]"
msgstr ""
-#: elf32-mips.c:2656
+#: elf32-mips.c:2676
msgid " [mips3]"
msgstr ""
-#: elf32-mips.c:2658
+#: elf32-mips.c:2678
msgid " [mips4]"
msgstr ""
-#: elf32-mips.c:2660
+#: elf32-mips.c:2680
+msgid " [mips5]"
+msgstr ""
+
+#: elf32-mips.c:2682
msgid " [mips32]"
msgstr ""
-#: elf32-mips.c:2662
+#: elf32-mips.c:2684
+msgid " [mips64]"
+msgstr ""
+
+#: elf32-mips.c:2686
msgid " [unknown ISA]"
msgstr ""
-#: elf32-mips.c:2665
+#: elf32-mips.c:2689
msgid " [32bitmode]"
msgstr ""
-#: elf32-mips.c:2667
+#: elf32-mips.c:2691
msgid " [not 32bitmode]"
msgstr ""
-#: elf32-mips.c:4316
+#: elf32-mips.c:4340
msgid "static procedure (no name)"
msgstr ""
-#: elf32-mips.c:4931 elf64-alpha.c:4378
+#: elf32-mips.c:4955 elf64-alpha.c:4378
#, c-format
msgid "%s: illegal section name `%s'"
msgstr ""
-#: elf32-mips.c:5495
+#: elf32-mips.c:5519
msgid "not enough GOT space for local GOT entries"
msgstr ""
-#: elf32-mips.c:6612
+#: elf32-mips.c:6636
#, c-format
msgid "%s: %s+0x%lx: jump to stub routine which is not jal"
msgstr ""
-#: elf32-mips.c:7599
+#: elf32-mips.c:7623
#, c-format
msgid "Malformed reloc detected for section %s"
msgstr ""
-#: elf32-mips.c:7676
+#: elf32-mips.c:7700
#, c-format
msgid "%s: CALL16 reloc at 0x%lx not against global symbol"
msgstr ""
EF_MIPS_ARCH. Replace use of E_MIPS_MACH_MIPS32 with
E_MIPS_MACH_MIPS32_4K and adjust printed CPU name similarly.
+ * readelf.c (get_machine_flags): Add cases for E_MIPS_ARCH_5,
+ and E_MIPS_ARCH_64.
+
2000-11-30 Richard Earnshaw <rearnsha@arm.com>
* readelf.c (frame_display_row): Output 's' for DW_CFA_same_value.
if ((e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_4)
strcat (buf, ", mips4");
+ if ((e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_5)
+ strcat (buf, ", mips5");
+
if ((e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32)
strcat (buf, ", mips32");
+ if ((e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_64)
+ strcat (buf, ", mips64");
+
switch ((e_flags & EF_MIPS_MACH))
{
case E_MIPS_MACH_3900: strcat (buf, ", 3900"); break;
4Kp entries with a single mips32-4k entry. Note that you can
use ".set mips32".
+ * tc-mips.c (ISA_HAS_64BIT_REGS): Add checks for ISA_MIPS5 and
+ ISA_MIPS64.
+ (md_longopts, OPTION_MIPS5, OPTION_MIPS64): Add options for
+ -mips5 and -mips64.
+ (md_parse_option): Add cases for OPTION_MIPS5 and
+ OPTION_MIPS64.
+ (md_show_usage): Mention -mips5 and -mips64 arguments.
+ (s_mipsset): Add cases for MIPS5 and MIPS64.
+ (mips_cpu_info_table): Add entries for MIPS5 and MIPS64 ISAs
+ and pseudo-CPUs.
+ * doc/as.texinfo: Mention -mips5 and -mips64 options
+ and their meanings.
+ * doc/c-mips.texi: Likewise. Also update introduction
+ and ".set" usage information.
+
2000-12-01 Joel Sherrill <joel@OARcorp.com>
* configure.in (arm-*-rtems*, a29k-*rtems*, h8300-*-rtems*):
#define ISA_HAS_64BIT_REGS(ISA) ( \
(ISA) == ISA_MIPS3 \
|| (ISA) == ISA_MIPS4 \
+ || (ISA) == ISA_MIPS5 \
+ || (ISA) == ISA_MIPS32 \
)
/* Whether the processor uses hardware interlocks to protect
{"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
#define OPTION_MIPS32 (OPTION_MD_BASE + 28)
{"mips32", no_argument, NULL, OPTION_MIPS32},
+#define OPTION_MIPS5 (OPTION_MD_BASE + 29)
+ {"mips5", no_argument, NULL, OPTION_MIPS5},
+#define OPTION_MIPS64 (OPTION_MD_BASE + 30)
+ {"mips64", no_argument, NULL, OPTION_MIPS64},
#ifdef OBJ_ELF
#define OPTION_ELF_BASE (OPTION_MD_BASE + 35)
#define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
mips_opts.isa = ISA_MIPS4;
break;
+ case OPTION_MIPS5:
+ mips_opts.isa = ISA_MIPS5;
+ break;
+
case OPTION_MIPS32:
mips_opts.isa = ISA_MIPS32;
break;
+ case OPTION_MIPS64:
+ mips_opts.isa = ISA_MIPS64;
+ break;
+
case OPTION_MCPU:
{
/* Identify the processor type. */
-mips2 generate MIPS ISA II instructions\n\
-mips3 generate MIPS ISA III instructions\n\
-mips4 generate MIPS ISA IV instructions\n\
+-mips5 generate MIPS ISA V instructions\n\
-mips32 generate MIPS32 ISA instructions\n\
+-mips64 generate MIPS64 ISA instructions\n\
-mcpu=CPU generate code for CPU, where CPU is one of:\n"));
first = 1;
isa = atoi (name + 4);
switch (isa)
{
- case 0: mips_opts.isa = file_mips_isa; break;
- case 1: mips_opts.isa = ISA_MIPS1; break;
- case 2: mips_opts.isa = ISA_MIPS2; break;
- case 3: mips_opts.isa = ISA_MIPS3; break;
- case 4: mips_opts.isa = ISA_MIPS4; break;
- case 32: mips_opts.isa = ISA_MIPS32; break;
- default:
- as_bad (_("unknown ISA level"));
- break;
+ case 0: mips_opts.isa = file_mips_isa; break;
+ case 1: mips_opts.isa = ISA_MIPS1; break;
+ case 2: mips_opts.isa = ISA_MIPS2; break;
+ case 3: mips_opts.isa = ISA_MIPS3; break;
+ case 5: mips_opts.isa = ISA_MIPS5; break;
+ case 4: mips_opts.isa = ISA_MIPS4; break;
+ case 32: mips_opts.isa = ISA_MIPS32; break;
+ case 64: mips_opts.isa = ISA_MIPS64; break;
+ default: as_bad (_("unknown ISA level")); break;
}
}
else if (strcmp (name, "autoextend") == 0)
/* MIPS4 ISA */
{ "MIPS4", 1, ISA_MIPS4, CPU_R8000, },
+ /* MIPS5 ISA */
+ { "MIPS5", 1, ISA_MIPS5, CPU_MIPS5, },
+ { "Generic-MIPS5", 0, ISA_MIPS5, CPU_MIPS5, },
+
/* MIPS32 ISA */
{ "MIPS32", 1, ISA_MIPS32, CPU_MIPS32, },
{ "Generic-MIPS32", 0, ISA_MIPS32, CPU_MIPS32, },
+#if 1
/* XXX for now, MIPS64 -> MIPS3 because of history */
{ "MIPS64", 1, ISA_MIPS3, CPU_R4000 }, /* XXX! */
+#else
+ /* MIPS64 ISA */
+ { "MIPS64", 1, ISA_MIPS64, CPU_MIPS64 },
+#endif
+ { "mips64isa", 1, ISA_MIPS64, CPU_MIPS64 },
+ { "Generic-MIPS64", 0, ISA_MIPS64, CPU_MIPS64, },
/* R2000 CPU */
{ "R2000", 0, ISA_MIPS1, CPU_R2000, },
@end ifset
@ifset MIPS
[ -nocpp ] [ -EL ] [ -EB ] [ -G @var{num} ] [ -mcpu=@var{CPU} ]
- [ -mips1 ] [ -mips2 ] [ -mips3 ] [ -mips4 ] [ -mips32 ]
+ [ -mips1 ] [ -mips2 ] [ -mips3 ] [ -mips4 ] [ -mips5 ]
+ [ -mips32 ] [ -mips64 ]
[ -m4650 ] [ -no-m4650 ]
[ --trap ] [ --break ]
[ --emulation=@var{name} ]
@itemx -mips32
Generate code for a particular MIPS Instruction Set Architecture level.
@samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
-@samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the @sc{r4000}
-processor, @samp{-mips32} to a generic @sc{MIPS32} processor.
+@samp{-mips2} to the @sc{r6000} processor, and @samp{-mips3} to the @sc{r4000}
+processor.
+@samp{-mips5}, @samp{-mips32}, and @samp{-mips64} correspond
+to generic @sc{MIPS V}, @sc{MIPS32}, and @sc{MIPS64} ISA
+processors, respectively.
@item -m4650
@itemx -no-m4650
@cindex MIPS processor
@sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several
-different @sc{mips} processors, and MIPS ISA levels I through IV. For
+different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32,
+and MIPS64. For
information about the @sc{mips} instruction set, see @cite{MIPS RISC
Architecture}, by Kane and Heindrich (Prentice-Hall). For an overview
of @sc{mips} assembly conventions, see ``Appendix D: Assembly Language
@itemx -mips2
@itemx -mips3
@itemx -mips4
+@itemx -mips5
@itemx -mips32
+@itemx -mips64
Generate code for a particular MIPS Instruction Set Architecture level.
@samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
@samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
-@sc{r4000} processor, @samp{-mips4} to the @sc{r8000} and
-@sc{r10000} processors, and @samp{-mips32} to a generic @sc(MIPS32)
-processor. You can also switch instruction sets during the
+@sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and
+@sc{r10000} processors.
+@samp{-mips5}, @samp{-mips32}, and @samp{-mips64} correspond
+to generic @sc{MIPS V}, @sc{MIPS32}, and @sc{MIPS64} ISA
+processors, respectively.
+You can also switch instruction sets during the
assembly; see @ref{MIPS ISA, Directives to override the ISA level}.
@item -mgp32
@kindex @code{.set mips@var{n}}
@sc{gnu} @code{@value{AS}} supports an additional directive to change
the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
-mips@var{n}}. @var{n} should be a number from 0 to 4, or 32. The values 1
-to 4 and 32 make the assembler accept instructions for the corresponding
+mips@var{n}}. @var{n} should be a number from 0 to 5, or 32 or 64.
+The values 1 to 5, 32, and 64 make the assembler accept instructions
+for the corresponding
@sc{isa} level, from that point on in the assembly. @code{.set
mips@var{n}} affects not only which instructions are permitted, but also
how certain macros are expanded. @code{.set mips0} restores the
(E_MIPS_MACH_MIPS32, E_MIPS_MACH_MIPS32_4K): Replace the
former with the latter.
+ * mips.h (E_MIPS_ARCH_5, E_MIPS_ARCH_64): New definitions.
+
2000-11-30 Jan Hubicka <jh@suse.cz>
* common.h (EM_X86_64): New macro.
/* -mips4 code. */
#define E_MIPS_ARCH_4 0x30000000
+/* -mips5 code. */
+#define E_MIPS_ARCH_5 0x40000000
+
/* -mips32 code. */
#define E_MIPS_ARCH_32 0x50000000
+/* -mips64 code. */
+#define E_MIPS_ARCH_64 0x60000000
+
/* The ABI of the file. Also see EF_MIPS_ABI2 above. */
#define EF_MIPS_ABI 0x0000F000
(OPCODE_IS_MEMBER): Update for new ISA membership-related
constant meanings.
+ * mips.h (INSN_ISA64, ISA_MIPS5, ISA_MIPS64): New
+ definitions.
+
2000-10-20 Jakub Jelinek <jakub@redhat.com>
* sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B.
#define INSN_ISA4 0x00000080
#define INSN_ISA5 0x00000100
#define INSN_ISA32 0x00000200
+#define INSN_ISA64 0x00000400
/* Chip specific instructions. These are bitmasks. */
#define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2)
#define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3)
#define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4)
+#define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5)
#define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32)
+#define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
/* CPU defines, use instead of hardcoding processor number. Keep this
in sync with bfd/archures.c in order for machine selection to work. */
#define CPU_MIPS16 16
#define CPU_MIPS32 32
#define CPU_MIPS32_4K 3204113 /* 32, 04, octal 'K' */
+#define CPU_MIPS5 5
+#define CPU_MIPS64 64
/* Test for membership in an ISA including chip specific ISAs.
INSN is pointer to an element of the opcode table; ISA is the
(P4): Delete.
(mips_builtin_opcodes) Replace all uses of P4 with I32.
+ * mips-dis.c (set_mips_isa_type): Add cases for
+ bfd_mach_mips5 and bfd_mach_mips64.
+ * mips-opc.c (I64): New definitions.
+
2000-11-28 Hans-Peter Nilsson <hp@bitrange.com>
* sh-dis.c (print_insn_ddt): Make insn_x, insn_y unsigned.
target_processor = CPU_MIPS32_4K;
mips_isa = ISA_MIPS32;
break;
+ case bfd_mach_mips5:
+ target_processor = CPU_MIPS5;
+ mips_isa = ISA_MIPS5;
+ break;
+ case bfd_mach_mips64:
+ target_processor = CPU_MIPS64;
+ mips_isa = ISA_MIPS64;
+ break;
default:
target_processor = CPU_R3000;
mips_isa = ISA_MIPS3;
#define I4 INSN_ISA4
#define I5 INSN_ISA5
#define I32 INSN_ISA32
+#define I64 INSN_ISA64
#define P3 INSN_4650
#define L1 INSN_4010
msgid ""
msgstr ""
"Project-Id-Version: PACKAGE VERSION\n"
-"POT-Creation-Date: 2000-12-01 13:18-0800\n"
+"POT-Creation-Date: 2000-12-01 16:51-0800\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <LL@li.org>\n"
projects / binutils-gdb.git / commitdiff