radv: set depth/stencil enable values correctly for the meta clear path
authorSamuel Pitoiset <samuel.pitoiset@gmail.com>
Wed, 8 Jul 2020 11:12:37 +0000 (13:12 +0200)
committerMarge Bot <eric+marge@anholt.net>
Wed, 8 Jul 2020 12:41:10 +0000 (12:41 +0000)
They are booleans.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5803>

src/amd/vulkan/radv_meta_clear.c

index fa3832e70ea35231d9612dfab8e551950b4fc990..4d4dd1091655852b1331cde7a68b27797cb57730 100644 (file)
@@ -664,11 +664,11 @@ create_depthstencil_pipeline(struct radv_device *device,
 
        const VkPipelineDepthStencilStateCreateInfo ds_state = {
                .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
-               .depthTestEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
+               .depthTestEnable = !!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
                .depthCompareOp = VK_COMPARE_OP_ALWAYS,
-               .depthWriteEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
+               .depthWriteEnable = !!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
                .depthBoundsTestEnable = false,
-               .stencilTestEnable = (aspects & VK_IMAGE_ASPECT_STENCIL_BIT),
+               .stencilTestEnable = !!(aspects & VK_IMAGE_ASPECT_STENCIL_BIT),
                .front = {
                        .passOp = VK_STENCIL_OP_REPLACE,
                        .compareOp = VK_COMPARE_OP_ALWAYS,