altivec-7.c: Add qualifiers for counts on AIX versus Linux.

gcc/testsuite/ChangeLog:

2018-06-22  Carl Love  <cel@us.ibm.com>

 	* gcc.target/powerpc/altivec-7.c: Add qualifiers for counts on AIX
	versus Linux.  Change checks for xxlnor, xxland and xxlxor to also look
	for the vnor, vand and vxor instructions.
	* gcc.target/powerpc/builtins-1.c: Move vec_or tests to a new file.
	Remove counts for xxlor. Fix match on bl __divdi3 and bl __udivdi3.
	* gcc.target/powerpc/builtins-4.c: Fix matching for vsl instructions.
	* gcc.target/powerpc/builtins-5.c: New test file for vec_or test cases.
 	* gcc.target/powerpc/vsx-vector-6.p7.c: Fix xxlnor BE expected count.
	Add -dp to dg-options, update expected counts.

From-SVN: r261904

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index b3bb851c8abffd4801d1ac336fbac6e070f70319..5147236766d52ece18f0cf7e1ab95563e45d7b60 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,15 @@
+2018-06-22  Carl Love  <cel@us.ibm.com>
+
+       * gcc.target/powerpc/altivec-7.c: Add qualifiers for counts on AIX
+       versus Linux.  Change checks for xxlnor, xxland and xxlxor to also look
+       for the vnor, vand and vxor instructions.
+       * gcc.target/powerpc/builtins-1.c: Move vec_or tests to a new file.
+       Remove counts for xxlor. Fix match on bl __divdi3 and bl __udivdi3.
+       * gcc.target/powerpc/builtins-4.c: Fix matching for vsl instructions.
+       * gcc.target/powerpc/builtins-5.c: New test file for vec_or test cases.
+       * gcc.target/powerpc/vsx-vector-6.p7.c: Fix xxlnor BE expected count.
+       Add -dp to dg-options, update expected counts.
+
 2018-06-22  Paul Koning  <ni1d@arrl.net>
 
        * gcc.c-torture/execute/builtins/lib/chk.c: Use smaller alignment

diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-7.c b/gcc/testsuite/gcc.target/powerpc/altivec-7.c
index b61092cec67c5951c03a972bdc93c8bc6ebdc42d..ebc4a85ed8bb102536f179d56963453d6a8dd126 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/altivec-7.c
+++ b/gcc/testsuite/gcc.target/powerpc/altivec-7.c
@@ -73,8 +73,8 @@ int main ()
      vec_unpackl                    vupkhsh
      vec_unpackl                    vupkhpx
      vec_unpackl                    vupkhsb
-     vec_andc                       xxnor
-                                    xxland
+     vec_andc                       xxlnor (vnor AIX)
+                                    xxland (vand AIX)
      vec_vxor                       xxlxor
      vec_vmsumubm                   vmsumubm
      vec_vmulesb                    vmulosb
@@ -85,17 +85,16 @@ int main ()
 /* { dg-final { scan-assembler-times "vpkpx" 2 } } */
 /* { dg-final { scan-assembler-times "vmulesb" 1 } } */
 /* { dg-final { scan-assembler-times "vmulosb" 1 } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M} 42 { target le } } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M} 4 { target be } } } */
+/* { dg-final { scan-assembler-times {\mlvx\M} 0 { target { powerpc*-*-linux* } } } } */
+/* { dg-final { scan-assembler-times {\mlvx\M} 42 { target { powerpc*-*-aix* } } } } */
 /* { dg-final { scan-assembler-times "lvewx" 2 } } */
 /* { dg-final { scan-assembler-times "lvxl" 1 } } */
 /* { dg-final { scan-assembler-times "vupklsh" 2 } } */
 /* { dg-final { scan-assembler-times "vupkhsh" 2 } } */
-/* { dg-final { scan-assembler-times "xxlnor" 4 } } */
-/* { dg-final { scan-assembler-times "xxland" 4 } } */
-/* { dg-final { scan-assembler-times "xxlxor" 5 } } */
+/* { dg-final { scan-assembler-times {\mxxlnor\M|\mvnor\M} 4 } } */
+/* { dg-final { scan-assembler-times {\mxxland\M|\mvand\M} 4 } } */
+/* { dg-final { scan-assembler-times {\mxxlxor\M|\mvxor\M} 5 } } */
 /* { dg-final { scan-assembler-times "xxlandc" 0 } } */
-/* { dg-final { scan-assembler-times "lvx" 1 } } */
 /* { dg-final { scan-assembler-times "vmsumubm" 1 } } */
 /* { dg-final { scan-assembler-times "vupklpx" 1 } } */
 /* { dg-final { scan-assembler-times "vupklsx" 0 } } */

diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-1.c b/gcc/testsuite/gcc.target/powerpc/builtins-1.c
index 8baa8029bd3911e8597a6a4dadf818593155c474..2b81dac260a3f34fe6bd8719f4dea578ddfd831e 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/builtins-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-1.c
@@ -81,14 +81,6 @@ int main ()
   vector unsigned long long uq = vec_nor (ua, ud);
   vector unsigned long long ur = vec_nor (ud, ua);
 
-  vector long long ls = vec_or (la, lb);
-  vector long long lt = vec_or (la, ld);
-  vector long long lu = vec_or (ld, la);
-
-  vector unsigned long long us = vec_or (ua, ub);
-  vector unsigned long long ut = vec_or (ua, ud);
-  vector unsigned long long uu = vec_or (ud, ua);
-
   vector unsigned char ca = {0,4,8,1,5,9,2,6,10,3,7,11,15,12,14,13};
   vector unsigned char cbb = {5,4,8,3,1,9,2,6,10,3,7,11,15,12,14,13};
 
@@ -267,7 +259,6 @@ int main ()
   vector short signed int z_vss1 = vec_splat (ssa, 2);
   vector unsigned short int z_vuss1 = vec_splat (usa, 1);
 
-
   return 0;
 }
 
@@ -343,8 +334,8 @@ int main ()
 /* { dg-final { scan-assembler-times "divd" 8  { target lp64 } } } */
 /* { dg-final { scan-assembler-times "divdu" 2  { target lp64 } } } */
 /* { dg-final { scan-assembler-times "mulld" 4  { target lp64 } } } */
-/* { dg-final { scan-assembler-times "bl __divdi3" 3  { target ilp32 } } } */
-/* { dg-final { scan-assembler-times "bl __udivdi3" 3  { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mbl __divdi3\M} 2  { target { ilp32 } } } } */
+/* { dg-final { scan-assembler-times {\mbl __udivdi3\M} 2  { target {ilp32 } } } } */
 /* { dg-final { scan-assembler-times "mullw" 12  { target ilp32 } } } */
 /* { dg-final { scan-assembler-times "mulhwu" 4  { target ilp32 } } } */
 /* { dg-final { scan-assembler-times "xxmrgld" 0 } } */

diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-4.c b/gcc/testsuite/gcc.target/powerpc/builtins-4.c
index c5249fe8a028ac94dd0bf8effce65d64d58d43d5..66bfaf1210fb5a62441ecaea6c58ec866fb6f912 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/builtins-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-4.c
@@ -162,6 +162,5 @@ test_sll_vuill_vuill_vuc (vector unsigned long long int x,
 /* { dg-final { scan-assembler-times "xvnabsdp"  1 } } */
 /* { dg-final { scan-assembler-times "vslo"      4 } } */
 /* { dg-final { scan-assembler-times "xxlor"     30 } } */
-/* { dg-final { scan-assembler-times "vsl"     45 { target le } } } */
-/* { dg-final { scan-assembler-times "vsl"     45 { target { be && ilp32 } } } } */
-/* { dg-final { scan-assembler-times "vsl"     59 { target { be && lp64  } } } } */
+/* { dg-final { scan-assembler-times {\mvsl\M}   5 } } */
+

diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-5.c b/gcc/testsuite/gcc.target/powerpc/builtins-5.c
new file mode 100644 (file)
index 0000000..a4bb8fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-5.c
@@ -0,0 +1,40 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O0 -mno-fold-gimple -dp" } */
+/* { dg-prune-output "gimple folding of rs6000 builtins has been disabled." } */
+
+#include <altivec.h>
+
+
+int main ()
+{
+  vector long long la = {5L, 14L};
+  vector long long lb = {3L, 86L};
+  vector bool long long ld = {0, -1};
+
+  vector unsigned long long ua = {5L, 14L};
+  vector unsigned long long ub = {3L, 86L};
+  vector bool long long ud = {0, -1};
+
+  /*  vec_or tests generate an xxlor instruction when compiled with -O0.  The xxlor
+      instructions get optimized away with higher optimization levels.
+      When compiling on Linux we see the xxlor instruction used as a move in various
+      places.  When compiling on AIX, a move instruction is used instead of the xxlor
+      instruction.  So, these tests have been isolated into a different file to limit
+      the xxlor instruction use to just the vex_or builtin tests.  */      
+      
+  vector long long ls = vec_or (la, lb);
+  vector long long lt = vec_or (la, ld);
+  vector long long lu = vec_or (ld, la);
+
+  vector unsigned long long us = vec_or (ua, ub);
+  vector unsigned long long ut = vec_or (ua, ud);
+  vector unsigned long long uu = vec_or (ud, ua);
+
+  return 0;
+}
+
+/* Expected results:
+   vec_or              xxlor    */
+
+/* { dg-final { scan-assembler-times "xxlor" 6 } } */

diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c
index 66ec064dbffac57a0c46ce53321b61ec76ac4d3c..ab6e5573aa19b71f181e59bcd85aecaf86babfb3 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c
@@ -1,7 +1,7 @@
 /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-mvsx -O2 -mcpu=power7" } */
+/* { dg-options "-mvsx -O2 -mcpu=power7 -dp" } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
 
 
@@ -10,7 +10,7 @@
 /* { dg-final { scan-assembler-times "xvabsdp" 1 } } */
 /* { dg-final { scan-assembler-times "xvadddp" 1 } } */
 /* { dg-final { scan-assembler-times "xxlnor" 8 { target le } } } */
-/* { dg-final { scan-assembler-times "xxlnor" 8 { target be } } } */
+/* { dg-final { scan-assembler-times "xxlnor" 7 { target be } } } */
 /* { dg-final { scan-assembler-times "xvcmpeqdp" 5 { target le } } } */
 /* { dg-final { scan-assembler-times "xvcmpeqdp" 6 { target be }} } */
 /* { dg-final { scan-assembler-times "xvcmpeqdp." 5 { target le } } } */
@@ -30,21 +30,21 @@
 /* { dg-final { scan-assembler-times "xvmaxdp" 1 } } */
 /* { dg-final { scan-assembler-times "xvmindp" 1 } } */
 /* { dg-final { scan-assembler-times "xvmuldp" 1 } } */
-/* { dg-final { scan-assembler-times "vperm" 1 } } */
-/* { dg-final { scan-assembler-times "xvrdpic" 1 } } */
+/* { dg-final { scan-assembler-times "vperm" 2 } } */
+/* { dg-final { scan-assembler-times "xvrdpic" 2 } } */
 /* { dg-final { scan-assembler-times "xvsqrtdp" 1 } } */
 /* { dg-final { scan-assembler-times "xvrdpiz" 1 } } */
 /* { dg-final { scan-assembler-times "xvmsubasp" 1 } } */
 /* { dg-final { scan-assembler-times "xvnmaddasp" 1 } } */
 /* { dg-final { scan-assembler-times "xvnmaddadp" 1 } } */
 /* { dg-final { scan-assembler-times "xvnmsubadp" 1 } } */
-/* { dg-final { scan-assembler-times "vmsumshs" 1 } } */
+/* { dg-final { scan-assembler-times "vmsumshs" 2 } } */
 /* { dg-final { scan-assembler-times "xxland" 13 } } */
 /* { dg-final { scan-assembler-times "xxlxor" 2 } } */
-/* { dg-final { scan-assembler-times "xxsel" 2 } } */
+/* { dg-final { scan-assembler-times "xxsel" 4 } } */
 /* { dg-final { scan-assembler-times "xvrdpip" 1 } } */
 /* { dg-final { scan-assembler-times "xvdivdp" 1 } } */
-/* { dg-final { scan-assembler-times "xvrdpi" 5 } } */
+/* { dg-final { scan-assembler-times "xvrdpi" 7 } } */
 
 /* Source code for the test in vsx-vector-6.h */
 #include "vsx-vector-6.h"