genlib/CRG: fix variable name conflict
authorSebastien Bourdeauducq <sb@m-labs.hk>
Sat, 19 Sep 2015 03:18:44 +0000 (11:18 +0800)
committerSebastien Bourdeauducq <sb@m-labs.hk>
Sat, 19 Sep 2015 03:18:44 +0000 (11:18 +0800)
migen/genlib/io.py

index 3439f08832a1ab8c42b3caba267777538bf31878..12d8b0a11a69f782012b0eebbd43461f51bd78c0 100644 (file)
@@ -48,12 +48,12 @@ class CRG(Module):
             clk = clk_se
 
         # Power on Reset (vendor agnostic)
-        rst = Signal(reset=1)
-        self.sync.por += rst.eq(rst)
+        int_rst = Signal(reset=1)
+        self.sync.por += int_rst.eq(rst)
         self.comb += [
             self.cd_sys.clk.eq(clk),
             self.cd_por.clk.eq(clk),
-            self.cd_sys.rst.eq(rst)
+            self.cd_sys.rst.eq(int_rst)
         ]