Example Design:
-de0_nano : Generate Signals in FPGA and probe them with migScope : [Wip]
Toolchain [Ok]
--de1 : Generate Signals in FPGA and probe them with migScope : [Wip]
+-de1 : Generate Signals in FPGA and probe them with migScope : [Wip]
Toolchain [Ok]
+ - test_MigIo : Led & Switch Test controlled by Python [Ok]
+ - test_MigLa : Logic Analyzer controlled by Python [Wip]
+ (Still some glitches in received Data, let's use
+ migScope to debug itself :))
[> Contact
E-mail: florent@enjoy-digital.fr
# migIo
migIo0 = migIo.MigIo(MIGIO0_ADDR, 8, "IO", csr)
+def led_anim0():
+ for i in range(10):
+ migIo0.write(0xA5)
+ time.sleep(0.1)
+ migIo0.write(0x5A)
+ time.sleep(0.1)
+
+def led_anim1():
+ #Led <<
+ for j in range(4):
+ ledData = 1
+ for i in range(8):
+ migIo0.write(ledData)
+ time.sleep(i*i*0.0020)
+ ledData = (ledData<<1)
+ #Led >>
+ ledData = 128
+ for i in range(8):
+ migIo0.write(ledData)
+ time.sleep(i*i*0.0020)
+ ledData = (ledData>>1)
+
#==============================================================================
# T E S T M I G I O
#==============================================================================
-print("1) Write Led Reg")
-for i in range(10):
- migIo0.write(0xA5)
- time.sleep(0.1)
- migIo0.write(0x5A)
- time.sleep(0.1)
-
-print("2) Read Switch Reg")
-print(migIo0.read())
\ No newline at end of file
+print("- Small Led Animation...")
+led_anim0()
+time.sleep(1)
+led_anim1()
+time.sleep(1)
+
+print("- Read Switch: ",end=' ')
+print(migIo0.read())
+
+
from migScope import trigger, recorder, migIo
from migScope.tools.truthtable import *
+from migScope.tools.vcd import *
import spi2Csr
from spi2Csr.tools.uart2Spi import *
# Trigger
term0 = trigger.Term(trig_width)
-term1 = trigger.Term(trig_width)
-term2 = trigger.Term(trig_width)
-term3 = trigger.Term(trig_width)
-trigger0 = trigger.Trigger(TRIGGER_ADDR, trig_width, dat_width, [term0, term1, term2, term3], csr)
+trigger0 = trigger.Trigger(TRIGGER_ADDR, trig_width, dat_width, [term0], csr)
# Recorder
recorder0 = recorder.Recorder(RECORDER_ADDR, dat_width, record_size, csr)
#==============================================================================
# T E S T M I G L A
#==============================================================================
+term0.write(0x005A)
-term0.write(0x5A)
-term1.write(0x5A)
-term2.write(0x5A)
-term3.write(0x5A)
-sum_tt = gen_truth_table("term0 & term1 & term2 & term3")
-print(sum_tt)
+sum_tt = gen_truth_table("term0")
trigger0.sum.write(sum_tt)
-migIo0.write(0x5A)
-
recorder0.reset()
recorder0.size(256)
recorder0.offset(0)
recorder0.arm()
-
+print("-Recorder [Armed]")
+print("-Waiting Trigger...", end = ' ')
while(not recorder0.is_done()):
- print(".")
- time.sleep(1)
+ time.sleep(0.1)
+print("[Done]")
+
+print("-Receiving Data...", end = ' ')
+sys.stdout.flush()
+dat_vcd = recorder0.read(256)
+print("[Done]")
+myvcd = Vcd()
+myvcd.add(Var("wire", 32, "trig_dat", dat_vcd))
+myvcd.write("test_MigLa.vcd")
\ No newline at end of file
# Trigger
term0 = trigger.Term(trig_width)
- term1 = trigger.Term(trig_width)
- term2 = trigger.Term(trig_width)
- term3 = trigger.Term(trig_width)
- trigger0 = trigger.Trigger(TRIGGER_ADDR, trig_width, dat_width, [term0, term1, term2, term3])
+ trigger0 = trigger.Trigger(TRIGGER_ADDR, trig_width, dat_width, [term0])
# Recorder
recorder0 = recorder.Recorder(RECORDER_ADDR, dat_width, record_size)
# Signal Generator
sig_gen = Signal(BV(trig_width))
- #sync += [
- # sig_gen.eq(sig_gen+1)
- #]
+ sync += [
+ sig_gen.eq(sig_gen+1)
+ ]
+ #comb += [sig_gen.eq(migIo0.o)]
# Led
led0 = Signal(BV(8))
- #comb += [led0.eq(migIo0.o[:8])]
+ comb += [led0.eq(migIo0.o[:8])]
#Switch
sw0 = Signal(BV(8))
comb += [migIo0.i.eq(sw0)]
- sync += [
- sig_gen.eq(migIo0.o)
- ]
-
# Dat / Trig Bus
comb += [
trigger0.in_trig.eq(sig_gen),
trigger0.in_dat.eq(sig_gen)
]
- comb += [led0[7].eq(trigger0.sum.i)]
- comb += [led0[6].eq(trigger0.sum.o)]
-
- comb += [led0[3].eq(term3.o)]
- comb += [led0[2].eq(term2.o)]
- comb += [led0[1].eq(term1.o)]
- comb += [led0[0].eq(term0.o)]
# Trigger --> Recorder
comb += [
return self.interface.read(self.address + 0x02) == 1
def size(self, dat):
+ self.size = dat
self.interface.write_n(self.address + 0x03, dat, 16)
def offset(self, dat):
self.interface.write_n(self.address + 0x05, dat, 16)
-
+
+ def read(self, size):
+ r = []
+ for i in range(size):
+ self.interface.write(self.address+7, 1)
+ self.interface.write(self.address+7, 0)
+ r.append(self.interface.read_n(self.address+8,self.width))
+ return r
+
def get_fragment(self):
comb = []
sync = []
+
+ _get_d = Signal()
+ _get_rising = Signal()
+
+ sync += [
+ _get_d.eq(self._get.field.r),
+ _get_rising.eq(self._get.field.r & ~_get_d)
+ ]
#Bank <--> Storage / Sequencer
comb += [
self.sequencer.ctl_size.eq(self._size.field.r),
self.sequencer.ctl_arm.eq(self._arm.field.r),
self._done.field.w.eq(self.sequencer.ctl_done),
- self.storage.get.eq(self._get.field.r),
+ self.storage.get.eq(_get_rising),
self._get_dat.field.w.eq(self.storage.get_dat)
]
r += self.p_dumpvars()
r += self.p_valuechange()
return r
-
+
+ def write(self, filename):
+ f = open(filename, "w")
+ f.write(str(self))
+ f.close()
def main():
myvcd = Vcd()
dat = val<<16
addr = i
self.interface.write_n(self.reg_base, we + dat + addr,self.reg_size)
- self.interface.write_n(self.reg_base, 0, self.reg_size)
+ self.interface.write_n(self.reg_base, dat + addr, self.reg_size)
def get_fragment(self):
comb = []
uart.write(pack('B',data))
class Uart2Spi:
- def __init__(self, port, baudrate):
+ def __init__(self, port, baudrate, debug = False):
self.port = port
self.baudrate = baudrate
+ self.debug = debug
self.uart = serial.Serial(port, baudrate, timeout=0.01)
def read(self, addr):
write_b(self.uart, (addr>>8)&0xFF)
write_b(self.uart, (addr&0xFF))
write_b(self.uart, data)
- print("WR %02X @ %04X" %(data, addr))
+ if self.debug:
+ print("WR %02X @ %04X" %(data, addr))
def write_n(self, addr, data, n, endianess = "LE"):
words = int(2**bits_for(n-1)/8)
self.write(addr+i, (data>>(8*i)) & 0xFF)
elif endianess == "LE":
self.write(addr+words-1-i, (data>>(8*i)) & 0xFF)
- print("WR %08X @ %04X" %(data, addr))
+ if self.debug:
+ print("WR %08X @ %04X" %(data, addr))
def main():
csr = Uart2Spi(1,115200)
+++ /dev/null
-from fractions import Fraction
-from math import ceil
-
-from migen.fhdl.structure import *
-from migen.fhdl import verilog, autofragment
-from migen.bus import csr
-
-from migScope import trigger
-from migScope import recorder
-
-import spi2Csr
-
-from migScope.tools.truthtable import *
-
-#
-#Test Term
-#
-#term = trigger.Term(32,True)
-#v = verilog.convert(term.get_fragment())
-#print(v)
-
-#
-#Test RangeDetector
-#
-#rangeDetector = trigger.RangeDetector (32,True)
-#v = verilog.convert(rangeDetector.get_fragment())
-#print(v)
-
-#
-#Test EdgeDetector
-#
-#edgeDetector = trigger.EdgeDetector (32,True,"RFB")
-#v = verilog.convert(edgeDetector.get_fragment())
-#print(v)
-
-#
-#Test Timer
-#
-#timer = trigger.Timer(32)
-#v = verilog.convert(timer.get_fragment())
-#print(v)
-
-#
-#Test Sum
-#
-#sum = trigger.Sum(4,pipe=False)
-#v = verilog.convert(sum.get_fragment())
-#print(v)
-
-#
-#Test Storage
-#
-#storage = recorder.Storage(32,1024)
-#v = verilog.convert(storage.get_fragment())
-#print(v)
-
-#
-#Test Sequencer
-#
-#sequencer = recorder.Sequencer(1024)
-#v = verilog.convert(sequencer.get_fragment())
-#print(v)
-
-#
-#Test Recorder
-#
-#recorder = recorder.Recorder(0,32,1024)
-#v = verilog.convert(recorder.get_fragment())
-#print(v)
-
-#
-#Test Trigger
-#
-term0 = trigger.Term(32)
-term1 = trigger.RangeDetector(32)
-term2 = trigger.EdgeDetector(32)
-term3 = trigger.Term(32)
-
-trigger0 = trigger.Trigger(0,32,64,[term0, term1, term2, term3])
-recorder0 = recorder.Recorder(0,32,1024)
-v = verilog.convert(trigger0.get_fragment()+recorder0.get_fragment())
-print(v)
-
-#
-#Test spi2Csr
-#
-#spi2csr0 = spi2Csr.Spi2Csr(16,8)
-#v = verilog.convert(spi2csr0.get_fragment())
-#print(v)
-
-print(gen_truth_table("A&B&C"))
-
-
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