ruby: correct errors in changeset 4eec7bdde5b0

Couple of errors were discovered in 4eec7bdde5b0 which necessitated this patch.
Firstly, we create interrupt controllers in the se mode, but no piobus was
being created.  RubyPort, which earlier used to ignore range changes now
forwards those to the piobus.  The lack of piobus resulted in segmentation
fault.  This patch creates a piobus even in se mode.  It is not created only
when some tester is running.  Secondly,  I had missed out on modifying port
connections for other coherence protocols.

diff --git a/configs/example/se.py b/configs/example/se.py
index d4f3e2dd934c85301c157f08d2cdaf7a4f4d19d9..d390fbad004a5032243a5740a7a36b01dc503940 100644 (file)
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -231,9 +231,10 @@ if options.ruby:
     # Set the option for physmem so that it is not allocated any space
     system.physmem = MemClass(range=AddrRange(options.mem_size),
                               null = True)
-
     options.use_map = True
-    Ruby.create_system(options, system)
+
+    system.piobus = NoncoherentBus()
+    Ruby.create_system(options, system, system.piobus)
     assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
 
     for i in xrange(np):

diff --git a/configs/ruby/MESI_Three_Level.py b/configs/ruby/MESI_Three_Level.py
index f9435a1e4349beb783aec9b20aedc81dc3c7e251..67ed9af7493a146f3ea57271ea2e0a1ffa3f8a21 100644 (file)
--- a/configs/ruby/MESI_Three_Level.py
+++ b/configs/ruby/MESI_Three_Level.py
@@ -117,7 +117,9 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
                           cluster_id = i, ruby_system = ruby_system)
 
             if piobus != None:
-                cpu_seq.pio_port = piobus.slave
+                cpu_seq.pio_master_port = piobus.slave
+                cpu_seq.mem_master_port = piobus.slave
+                cpu_seq.pio_slave_port = piobus.master
 
             exec("ruby_system.l0_cntrl%d = l0_cntrl" % (
                         i*num_cpus_per_cluster+j))

diff --git a/configs/ruby/MI_example.py b/configs/ruby/MI_example.py
index 8f6c6e49031f6a4b2c05efd452f6a454df72123e..ed18c14cbe4d25ab2ea134f34931cfbc516c25d8 100644 (file)
--- a/configs/ruby/MI_example.py
+++ b/configs/ruby/MI_example.py
@@ -92,7 +92,9 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
         l1_cntrl.sequencer = cpu_seq
 
         if piobus != None:
-            cpu_seq.pio_port = piobus.slave
+            cpu_seq.pio_master_port = piobus.slave
+            cpu_seq.mem_master_port = piobus.slave
+            cpu_seq.pio_slave_port = piobus.master
 
         exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
         #

diff --git a/configs/ruby/MOESI_CMP_directory.py b/configs/ruby/MOESI_CMP_directory.py
index 9ebee8952d1dd7bd14c60b1e28976692ac34e6c8..0af4643afcef442f06f0dcd763c64db727aa1ed6 100644 (file)
--- a/configs/ruby/MOESI_CMP_directory.py
+++ b/configs/ruby/MOESI_CMP_directory.py
@@ -102,7 +102,9 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
         l1_cntrl.sequencer = cpu_seq
 
         if piobus != None:
-            cpu_seq.pio_port = piobus.slave
+            cpu_seq.pio_master_port = piobus.slave
+            cpu_seq.mem_master_port = piobus.slave
+            cpu_seq.pio_slave_port = piobus.master
 
         exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
         #

diff --git a/configs/ruby/MOESI_CMP_token.py b/configs/ruby/MOESI_CMP_token.py
index 699f159f8e6361c9187a1801b3caac2bdfa39caf..78ccef71ab82d6f18939b36aaa075fda640cf09c 100644 (file)
--- a/configs/ruby/MOESI_CMP_token.py
+++ b/configs/ruby/MOESI_CMP_token.py
@@ -122,7 +122,9 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
         l1_cntrl.sequencer = cpu_seq
 
         if piobus != None:
-            cpu_seq.pio_port = piobus.slave
+            cpu_seq.pio_master_port = piobus.slave
+            cpu_seq.mem_master_port = piobus.slave
+            cpu_seq.pio_slave_port = piobus.master
 
         exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
         #

diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py
index 47e37de301b9137c7d55c2e004cbf5e643735785..d716aba7aec6f08a87da454aade1991acc801c4d 100644 (file)
--- a/configs/ruby/MOESI_hammer.py
+++ b/configs/ruby/MOESI_hammer.py
@@ -115,7 +115,9 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
         l1_cntrl.sequencer = cpu_seq
 
         if piobus != None:
-            cpu_seq.pio_port = piobus.slave
+            cpu_seq.pio_master_port = piobus.slave
+            cpu_seq.mem_master_port = piobus.slave
+            cpu_seq.pio_slave_port = piobus.master
 
         if options.recycle_latency:
             l1_cntrl.recycle_latency = options.recycle_latency

diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py
index df8fdf2be837fb697a143d996a2bf5ccf0aa02c3..d3f4ad2ae93a18394bde39cb066fcb1eebe01772 100644 (file)
--- a/tests/configs/simple-timing-ruby.py
+++ b/tests/configs/simple-timing-ruby.py
@@ -79,8 +79,8 @@ system.cpu.clk_domain = SrcClockDomain(clock = '2GHz',
                                        voltage_domain = system.voltage_domain)
 
 system.mem_ranges = AddrRange('256MB')
-
-Ruby.create_system(options, system)
+system.piobus = NoncoherentBus()
+Ruby.create_system(options, system, system.piobus)
 
 # Create a separate clock for Ruby
 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,