bank: remove RE signal for field registers

diff --git a/migen/bank/csrgen.py b/migen/bank/csrgen.py
index 140e9baa09c866cb5f82651b8aed16af89f5aa23..b49ea56a84949fa33f445a9addd1893e95e5e64b 100644 (file)
--- a/migen/bank/csrgen.py
+++ b/migen/bank/csrgen.py
@@ -29,7 +29,6 @@ class Bank:
                                        self.interface.we & \
                                        (self.interface.adr[:nbits] == Constant(i, BV(nbits)))))
                        elif isinstance(reg, RegisterFields):
-                               sync.append(reg.re.eq(0))
                                bwra = [Constant(i, BV(nbits))]
                                offset = 0
                                for field in reg.fields:
@@ -37,7 +36,6 @@ class Bank:
                                                bwra.append(field.storage.eq(self.interface.dat_w[offset:offset+field.size]))
                                        offset += field.size
                                if len(bwra) > 1:
-                                       bwra.append(reg.re.eq(1))
                                        bwcases.append(bwra)
                                # commit atomic writes
                                for field in reg.fields:

diff --git a/migen/bank/description.py b/migen/bank/description.py
index 854e19d61ed2a16c676c56bd3bbe55d1011b1709..a83d87d63562cb0263eb99a2851cddd874e08155 100644 (file)
--- a/migen/bank/description.py
+++ b/migen/bank/description.py
@@ -28,13 +28,9 @@ class Field:
                                self.we = Signal()
 
 class RegisterFields:
-       def __init__(self, name, fields, re=None):
+       def __init__(self, name, fields):
                self.name = name
                self.fields = fields
-               if re is None:
-                       self.re = Signal()
-               else:
-                       self.re = re
 
 class RegisterField(RegisterFields):
        def __init__(self, name, size=1, access_bus=READ_WRITE, access_dev=READ_ONLY, reset=0, atomic_write=False):
@@ -111,7 +107,7 @@ def expand_description(description, busword):
                                else:
                                        f.append(field)
                        if f:
-                               d.append(RegisterFields(reg.name, f, reg.re))
+                               d.append(RegisterFields(reg.name, f))
                else:
                        raise TypeError
        return d