rs6000: Delete the "wy" constraint

This replaces the "wy" constraint by "wa", with isa "p8v".  It also
creates a new attribute <Fisa>, used together with all <Fv2>.

	* config/rs6000/constraints.md (define_register_constraint "wy"):
	Delete.
	* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
	RS6000_CONSTRAINT_wy.
	* config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
	(rs6000_init_hard_regno_mode_ok): Adjust.
	* config/rs6000/rs6000.md: Replace "wy" constraint by "wa" with "p8v".
	Use "<Fisa>" as "isa" in all alternatives that use "<Fv2>".
	(define_mode_attr Fisa): New.
	* config/rs6000/vsx.md: Replace "wy" constraint by "wa" with "p8v".
	* doc/md.texi (Machine Constraints): Adjust.

From-SVN: r271389

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e9bbedb26f5485ecb09f11460625136eadb71f9b..06c4f4449466c73c084b6c20697c893f300ddca4 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,17 @@
+2019-05-19  Segher Boessenkool  <segher@kernel.crashing.org>
+
+       * config/rs6000/constraints.md (define_register_constraint "wy"):
+       Delete.
+       * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
+       RS6000_CONSTRAINT_wy.
+       * config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
+       (rs6000_init_hard_regno_mode_ok): Adjust.
+       * config/rs6000/rs6000.md: Replace "wy" constraint by "wa" with "p8v".
+       Use "<Fisa>" as "isa" in all alternatives that use "<Fv2>".
+       (define_mode_attr Fisa): New.
+       * config/rs6000/vsx.md: Replace "wy" constraint by "wa" with "p8v".
+       * doc/md.texi (Machine Constraints): Adjust.
+
 2019-05-19  Segher Boessenkool  <segher@kernel.crashing.org>
 
        * config/rs6000/constraints.md (define_register_constraint "wu"):

diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index f9bbb7fbec030d6190db28adde99245698c041c3..58394eaaa8a6fb68f5f8c1e8ceebc315aca79797 100644 (file)
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -118,9 +118,6 @@
 (define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]"
   "Floating point register if the STFIWX instruction is enabled or NO_REGS.")
 
-(define_register_constraint "wy" "rs6000_constraints[RS6000_CONSTRAINT_wy]"
-  "FP or VSX register to perform ISA 2.07 float ops or NO_REGS.")
-
 (define_register_constraint "wz" "rs6000_constraints[RS6000_CONSTRAINT_wz]"
   "Floating point register if the LFIWZX instruction is enabled or NO_REGS.")
 

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 7e2dbf98f5f4aa48bcff1fc294dead1c0b422534..ee5bb7f2f03551dcf63508c8fc19cb3c688bac72 100644 (file)
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -2526,7 +2526,6 @@ rs6000_debug_reg_global (void)
           "wv reg_class = %s\n"
           "ww reg_class = %s\n"
           "wx reg_class = %s\n"
-          "wy reg_class = %s\n"
           "wz reg_class = %s\n"
           "wA reg_class = %s\n"
           "wH reg_class = %s\n"
@@ -2554,7 +2553,6 @@ rs6000_debug_reg_global (void)
           reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wv]],
           reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]],
           reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
-          reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wy]],
           reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wz]],
           reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]],
           reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wH]],
@@ -3182,7 +3180,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
        wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
        ww - Register class to do SF conversions in with VSX operations.
        wx - Float register if we can do 32-bit int stores.
-       wy - Register class to do ISA 2.07 SF operations.
        wz - Float register if we can do 32-bit unsigned int loads.
        wH - Altivec register if SImode is allowed in VSX registers.
        wI - Float register if SImode is allowed in VSX registers.  */
@@ -3232,10 +3229,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
     }
 
   if (TARGET_P8_VECTOR)                                                /* SFmode  */
-    {
-      rs6000_constraints[RS6000_CONSTRAINT_wy] = VSX_REGS;
-      rs6000_constraints[RS6000_CONSTRAINT_ww] = VSX_REGS;
-    }
+    rs6000_constraints[RS6000_CONSTRAINT_ww] = VSX_REGS;
   else if (TARGET_VSX)
     rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS;
 

diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 6d3056139bec8a1c65eb9ea0000f2b5ebcaad444..96471d79488fad094fa11035f076eca45ad86233 100644 (file)
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1267,7 +1267,6 @@ enum r6000_reg_class_enum {
   RS6000_CONSTRAINT_wv,                /* Altivec register for double load/stores.  */
   RS6000_CONSTRAINT_ww,                /* FP or VSX register for vsx float ops.  */
   RS6000_CONSTRAINT_wx,                /* FPR register for STFIWX */
-  RS6000_CONSTRAINT_wy,                /* VSX register for SF */
   RS6000_CONSTRAINT_wz,                /* FPR register for LFIWZX */
   RS6000_CONSTRAINT_wA,                /* BASE_REGS if 64-bit.  */
   RS6000_CONSTRAINT_wH,                /* Altivec register for 32-bit integers.  */

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index c5def7480d917094c9ddf43ff403e3e613f2923a..984fe9ee40c1928e4c7d1b619f326894245fffe4 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -530,7 +530,10 @@
 ; SF/DF constraint for arithmetic on VSX registers.  This is intended to be
 ; used for DFmode instructions added in ISA 2.06 (power7) and SFmode
 ; instructions added in ISA 2.07 (power8)
-(define_mode_attr Fv2          [(SF "wy") (DF "ws") (DI "wi")])
+(define_mode_attr Fv2          [(SF "wa") (DF "ws") (DI "wi")])
+
+; Which isa is needed for those float instructions?
+(define_mode_attr Fisa         [(SF "p8v")  (DF "*") (DI "*")])
 
 ; s/d suffix for things like sdiv/ddiv
 (define_mode_attr Fs           [(SF "s")  (DF "d")])
@@ -4641,7 +4644,8 @@
   "@
    fadd<Ftrad> %0,%1,%2
    xsadd<Fvsx> %x0,%x1,%x2"
-  [(set_attr "type" "fp")])
+  [(set_attr "type" "fp")
+   (set_attr "isa" "*,<Fisa>")])
 
 (define_expand "sub<mode>3"
   [(set (match_operand:SFDF 0 "gpc_reg_operand")
@@ -4658,7 +4662,8 @@
   "@
    fsub<Ftrad> %0,%1,%2
    xssub<Fvsx> %x0,%x1,%x2"
-  [(set_attr "type" "fp")])
+  [(set_attr "type" "fp")
+   (set_attr "isa" "*,<Fisa>")])
 
 (define_expand "mul<mode>3"
   [(set (match_operand:SFDF 0 "gpc_reg_operand")
@@ -4675,7 +4680,8 @@
   "@
    fmul<Ftrad> %0,%1,%2
    xsmul<Fvsx> %x0,%x1,%x2"
-  [(set_attr "type" "dmul")])
+  [(set_attr "type" "dmul")
+   (set_attr "isa" "*,<Fisa>")])
 
 (define_expand "div<mode>3"
   [(set (match_operand:SFDF 0 "gpc_reg_operand")
@@ -4700,7 +4706,8 @@
   "@
    fdiv<Ftrad> %0,%1,%2
    xsdiv<Fvsx> %x0,%x1,%x2"
-  [(set_attr "type" "<Fs>div")])
+  [(set_attr "type" "<Fs>div")
+   (set_attr "isa" "*,<Fisa>")])
 
 (define_insn "*sqrt<mode>2_internal"
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
@@ -4709,7 +4716,8 @@
   "@
    fsqrt<Ftrad> %0,%1
    xssqrt<Fvsx> %x0,%x1"
-  [(set_attr "type" "<Fs>sqrt")])
+  [(set_attr "type" "<Fs>sqrt")
+   (set_attr "isa" "*,<Fisa>")])
 
 (define_expand "sqrt<mode>2"
   [(set (match_operand:SFDF 0 "gpc_reg_operand")
@@ -4737,7 +4745,8 @@
   "@
    fre<Ftrad> %0,%1
    xsre<Fvsx> %x0,%x1"
-  [(set_attr "type" "fp")])
+  [(set_attr "type" "fp")
+   (set_attr "isa" "*,<Fisa>")])
 
 (define_insn "*rsqrt<mode>2"
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
@@ -4747,7 +4756,8 @@
   "@
    frsqrte<Ftrad> %0,%1
    xsrsqrte<Fvsx> %x0,%x1"
-  [(set_attr "type" "fp")])
+  [(set_attr "type" "fp")
+   (set_attr "isa" "*,<Fisa>")])
 
 ;; Floating point comparisons
 (define_insn "*cmp<mode>_fpr"
@@ -4758,7 +4768,8 @@
   "@
    fcmpu %0,%1,%2
    xscmpudp %0,%x1,%x2"
-  [(set_attr "type" "fpcompare")])
+  [(set_attr "type" "fpcompare")
+   (set_attr "isa" "*,<Fisa>")])
 
 ;; Floating point conversions
 (define_expand "extendsfdf2"
@@ -4772,7 +4783,7 @@
 
 (define_insn_and_split "*extendsfdf2_fpr"
   [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wa,v")
-       (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wy,Z,wY")))]
+       (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wa,Z,wY")))]
   "TARGET_HARD_FLOAT && !HONOR_SNANS (SFmode)"
   "@
    #
@@ -4789,16 +4800,17 @@
   DONE;
 }
   [(set_attr "type" "fp,fpsimple,fpload,fp,fpsimple,fpload,fpload")
-   (set_attr "isa" "*,*,*,*,*,p8v,p9v")])
+   (set_attr "isa" "*,*,*,*,p8v,p8v,p9v")])
 
 (define_insn "*extendsfdf2_snan"
   [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
-       (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f,wy")))]
+       (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f,wa")))]
   "TARGET_HARD_FLOAT && HONOR_SNANS (SFmode)"
   "@
    frsp %0,%1
    xsrsp %x0,%x1"
-  [(set_attr "type" "fp")])
+  [(set_attr "type" "fp")
+   (set_attr "isa" "*,p8v")])
 
 (define_expand "truncdfsf2"
   [(set (match_operand:SF 0 "gpc_reg_operand")
@@ -4807,13 +4819,14 @@
   "")
 
 (define_insn "*truncdfsf2_fpr"
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy")
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wa")
        (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d,ws")))]
   "TARGET_HARD_FLOAT"
   "@
    frsp %0,%1
    xsrsp %x0,%x1"
-  [(set_attr "type" "fp")])
+  [(set_attr "type" "fp")
+   (set_attr "isa" "*,p8v")])
 
 ;; This expander is here to avoid FLOAT_WORDS_BIGENDIAN tests in
 ;; builtins.c and optabs.c that are not correct for IBM long double
@@ -6288,16 +6301,17 @@
 })
 
 (define_insn "floatdisf2_fcfids"
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy")
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wa")
        (float:SF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
   "TARGET_HARD_FLOAT && TARGET_FCFIDS"
   "@
    fcfids %0,%1
    xscvsxdsp %x0,%x1"
-  [(set_attr "type" "fp")])
+  [(set_attr "type" "fp")
+   (set_attr "isa" "*,p8v")])
 
 (define_insn_and_split "*floatdisf2_mem"
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy,wy")
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wa,wa")
        (float:SF (match_operand:DI 1 "memory_operand" "m,m,Z")))
    (clobber (match_scratch:DI 2 "=d,d,wi"))]
   "TARGET_HARD_FLOAT && TARGET_FCFIDS"
@@ -6309,7 +6323,8 @@
   emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
   DONE;
 }
-  [(set_attr "length" "8")])
+  [(set_attr "length" "8")
+   (set_attr "isa" "*,p8v,p8v")])
 
 ;; This is not IEEE compliant if rounding mode is "round to nearest".
 ;; If the DI->DF conversion is inexact, then it's possible to suffer
@@ -6377,7 +6392,7 @@
    (set_attr "isa" "*,p8v")])
 
 (define_insn_and_split "*floatunsdisf2_mem"
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy,wy")
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wa,wa")
        (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m,m,Z")))
    (clobber (match_scratch:DI 2 "=d,d,wi"))]
   "TARGET_HARD_FLOAT && TARGET_FCFIDUS"
@@ -6389,8 +6404,9 @@
   emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
   DONE;
 }
-  [(set_attr "length" "8")
-   (set_attr "type" "fpload")])
+  [(set_attr "type" "fpload")
+   (set_attr "length" "8")
+   (set_attr "isa" "*,p8v,p8v")])
 \f
 ;; Define the TImode operations that can be done in a small number
 ;; of instructions.  The & constraints are to prevent the register
@@ -7410,10 +7426,10 @@
 (define_insn_and_split "movsf_from_si"
   [(set (match_operand:SF 0 "nonimmediate_operand"
            "=!r,       f,         v,         wa,        m,         Z,
-            Z,         wy,        ?r,        !r")
+            Z,         wa,        ?r,        !r")
        (unspec:SF [(match_operand:SI 1 "input_operand" 
            "m,         m,         wY,        Z,         r,         f,
-            wa,        r,         wy,        r")]
+            wa,        r,         wa,        r")]
                   UNSPEC_SF_FROM_SI))
    (clobber (match_scratch:DI 2
            "=X,        X,         X,         X,         X,         X,
@@ -7457,7 +7473,7 @@
             fpstore,    vecfloat,  mffgpr,    *")
    (set_attr "isa"
            "*,          *,         p9v,       p8v,       *,         *,
-            p8v,        *,         *,         *")])
+            p8v,        p8v,       p8v,       *")])
 
 \f
 ;; Move 64-bit binary/decimal floating point
@@ -13301,7 +13317,8 @@
    fmadd<Ftrad> %0,%1,%2,%3
    xsmadda<Fvsx> %x0,%x1,%x2
    xsmaddm<Fvsx> %x0,%x1,%x3"
-  [(set_attr "type" "fp")])
+  [(set_attr "type" "fp")
+   (set_attr "isa" "*,<Fisa>,<Fisa>")])
 
 ; Altivec only has fma and nfms.
 (define_expand "fms<mode>4"
@@ -13324,7 +13341,8 @@
    fmsub<Ftrad> %0,%1,%2,%3
    xsmsuba<Fvsx> %x0,%x1,%x2
    xsmsubm<Fvsx> %x0,%x1,%x3"
-  [(set_attr "type" "fp")])
+  [(set_attr "type" "fp")
+   (set_attr "isa" "*,<Fisa>,<Fisa>")])
 
 ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
 (define_expand "fnma<mode>4"
@@ -13371,7 +13389,8 @@
    fnmadd<Ftrad> %0,%1,%2,%3
    xsnmadda<Fvsx> %x0,%x1,%x2
    xsnmaddm<Fvsx> %x0,%x1,%x3"
-  [(set_attr "type" "fp")])
+  [(set_attr "type" "fp")
+   (set_attr "isa" "*,<Fisa>,<Fisa>")])
 
 ; Not an official optab name, but used from builtins.
 (define_expand "nfms<mode>4"
@@ -13397,8 +13416,8 @@
    fnmsub<Ftrad> %0,%1,%2,%3
    xsnmsuba<Fvsx> %x0,%x1,%x2
    xsnmsubm<Fvsx> %x0,%x1,%x3"
-  [(set_attr "type" "fp")])
-
+  [(set_attr "type" "fp")
+   (set_attr "isa" "*,<Fisa>,<Fisa>")])
 \f
 (define_expand "rs6000_get_timebase"
   [(use (match_operand:DI 0 "gpc_reg_operand"))]
@@ -14022,7 +14041,7 @@
 ;; the KFmode -> DFmode conversion using round to odd rather than the normal
 ;; conversion
 (define_insn_and_split "trunc<mode>sf2_hw"
-  [(set (match_operand:SF 0 "vsx_register_operand" "=wy")
+  [(set (match_operand:SF 0 "vsx_register_operand" "=wa")
        (float_truncate:SF
         (match_operand:IEEE128 1 "altivec_register_operand" "v")))
    (clobber (match_scratch:DF 2 "=v"))]
@@ -14039,7 +14058,8 @@
     operands[2] = gen_reg_rtx (DFmode);
 }
   [(set_attr "type" "vecfloat")
-   (set_attr "length" "8")])
+   (set_attr "length" "8")
+   (set_attr "isa" "p8v")])
 
 ;; Conversion between IEEE 128-bit and integer types
 

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 7c89ad8ad3a086af9dadfb100c1f0afc0a8aa28f..49601f8c74051f5e85a3be28a047669aa662b397 100644 (file)
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4168,7 +4168,7 @@
 (define_insn_and_split "vsx_splat_v4sf"
   [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa,wa")
        (vec_duplicate:V4SF
-        (match_operand:SF 1 "splat_input_operand" "Z,wy,r")))]
+        (match_operand:SF 1 "splat_input_operand" "Z,wa,r")))]
   "TARGET_P9_VECTOR"
   "@
    lxvwsx %x0,%y1
@@ -4182,7 +4182,8 @@
                      (const_int 0)] UNSPEC_VSX_XXSPLTW))]
   ""
   [(set_attr "type" "vecload,vecperm,mftgpr")
-   (set_attr "length" "4,8,4")])
+   (set_attr "length" "4,8,4")
+   (set_attr "isa" "*,p8v,*")])
 
 ;; V4SF/V4SI splat from a vector element
 (define_insn "vsx_xxspltw_<mode>"

diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index fd92704b3c47e5e4447e3538d80d11f7d7a1022a..f542872a2353fddb52164d6e1b12793d6272472d 100644 (file)
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3199,7 +3199,7 @@ Any VSX register if the @option{-mvsx} option was used or NO_REGS.
 When using any of the register constraints (@code{wa}, @code{wd},
 @code{wf}, @code{wg}, @code{wh}, @code{wi}, @code{wj}, @code{wk},
 @code{wl}, @code{wm}, @code{wp}, @code{wq}, @code{ws},
-@code{wt}, @code{wv}, @code{ww}, or @code{wy})
+@code{wt}, @code{wv}, or @code{ww})
 that take VSX registers, you must use @code{%x<n>} in the template so
 that the correct register is used.  Otherwise the register number
 output in the assembly file will be incorrect if an Altivec register
@@ -3304,9 +3304,6 @@ FP or VSX register to perform float operations under @option{-mvsx} or NO_REGS.
 @item wx
 Floating point register if the STFIWX instruction is enabled or NO_REGS.
 
-@item wy
-FP or VSX register to perform ISA 2.07 float ops or NO_REGS.
-
 @item wz
 Floating point register if the LFIWZX instruction is enabled or NO_REGS.