cpu/vexriscv: update submodule

diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog
index c6dfccaaa3c830b8c9c5037bbd4e1a8d43ca5bf0..4b5a515d4bbb22df0eb44a6e53cc76b3da1ff470 160000 (submodule)
--- a/litex/soc/cores/cpu/vexriscv/verilog
+++ b/litex/soc/cores/cpu/vexriscv/verilog
@@ -1 +1 @@
-Subproject commit c6dfccaaa3c830b8c9c5037bbd4e1a8d43ca5bf0
+Subproject commit 4b5a515d4bbb22df0eb44a6e53cc76b3da1ff470