add isvec to reg_spec_t, bit of cleanup

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index cc61aded0ee39cde03249b91ec489c431dc55f45..f49d2c733ce3d12ba14d02bff10fb03cf111d141 100644 (file)
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -77,7 +77,7 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
   reg_t _target_reg = 0;
   reg_t *target_reg = NULL;
 #endif
-  reg_spec_t sp = {0, insn.get_sp_offs()};
+  reg_spec_t sp = {0, NULL};
   if (vlen > 0)
   {
     fprintf(stderr, "pre-ex reg %s %x %ld rd %ld rs1 %ld rs2 %ld vlen %d\n",

diff --git a/riscv/sv.cc b/riscv/sv.cc
index 16bcba54df4c773d71e13f05b3348d2e75cce1d8..151c8fc8d22bade832864beae477181bdcdaabbf 100644 (file)
--- a/riscv/sv.cc
+++ b/riscv/sv.cc
@@ -164,6 +164,7 @@ reg_spec_t sv_insn_t::remap(uint64_t reg, bool intreg, int *voffs)
   // aaand now, as it's a "vector", FINALLY we can pass the loop-offset
   spec.reg = reg; //+ *voffs;
   spec.offset = voffs;
+  spec.isvec = r->isvec;
   return spec;
 }
 
@@ -229,6 +230,7 @@ reg_spec_t sv_insn_t::predicated(reg_spec_t const& spec, uint64_t pred)
     fprintf(stderr, "predication %ld %d %lx\n", spec.reg, (*spec.offset), pred);
     res.reg = 0;
     res.offset = 0;
+    res.isvec = false;
     return res;
 }
 

diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h
index 5c30429340627c1d490265093efd1b9f11101c6d..a36421169c4db42eec89732e2be70f62bc08f562 100644 (file)
--- a/riscv/sv_decode.h
+++ b/riscv/sv_decode.h
@@ -30,6 +30,7 @@ struct reg_spec_t
 {
     reg_t reg;
     int *offset;
+    bool isvec;
 };
 
 class sv_insn_t: public insn_t

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 6cd844358d611288da10251bcde444be4e1f1c78..e674ab75cba5d60708a7c09b5e07b30679a52050 100644 (file)
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -79,6 +79,8 @@ void (sv_proc_t::WRITE_RD)(sv_reg_t const& value)
 //    STATE.XPR.write(reg, value);
 //}
 
+//#define OFFSDIV
+
 void (sv_proc_t::DO_WRITE_FREG)(reg_spec_t const& spec, freg_t const& value)
 {
     //WRITE_REG( reg, value ); // XXX TODO: replace properly
@@ -100,29 +102,11 @@ void (sv_proc_t::WRITE_REG)(reg_spec_t const& spec, sv_reg_t const& value)
     STATE.XPR.write(reg, value);
 }
 
-//void (sv_proc_t::WRITE_REG)(reg_t reg, uint64_t value)
-//{
-//    //WRITE_REG( reg, value ); // XXX TODO: replace properly
-//    STATE.XPR.write(reg, value);
-//}
-
-/*
-void (sv_proc_t::WRITE_RD)(int_fast64_t value)
-{
-    WRITE_REG( _insn->rd(), value ); // XXX TODO: replace properly
-}
-
-void (sv_proc_t::WRITE_RD)(uint_fast64_t value)
-{
-    WRITE_REG( _insn->rd(), value ); // XXX TODO: replace properly
-}
-*/
-
 freg_t (sv_proc_t::READ_FREG)(reg_spec_t const& spec)
 {
     reg_t reg = spec.reg;
     uint8_t elwidth = _insn->reg_elwidth(reg, true);
-    if (spec.offset && spec.reg != 2) {
+    if (spec.offset) {
         reg += *spec.offset;
     }
     return _insn->p->get_state()->FPR[reg]; // XXX TODO: offset
@@ -132,7 +116,7 @@ reg_t (sv_proc_t::READ_REG)(reg_spec_t const& spec)
 {
     reg_t reg = spec.reg;
     uint8_t elwidth = _insn->reg_elwidth(reg, true);
-    if (spec.offset && spec.reg != 2) {
+    if (spec.offset && spec.reg != 2) { // XXX HACK on spec.reg != 2
         reg += *spec.offset;
     }
     return _insn->p->get_state()->XPR[reg]; // XXX TODO: offset