Fixed cellaigs port extending

diff --git a/kernel/cellaigs.cc b/kernel/cellaigs.cc
index b738b9dbaa26b111a4730cba12d9412383207a2c..483aa7d577c7f1fc9c0444adf6271fe6af5d4b08 100644 (file)
--- a/kernel/cellaigs.cc
+++ b/kernel/cellaigs.cc
@@ -77,7 +77,7 @@ struct AigMaker
                if (portbit >= GetSize(cell->getPort(portname))) {
                        if (cell->parameters.count(portname.str() + "_SIGNED") && cell->getParam(portname.str() + "_SIGNED").as_bool())
                                return inport(portname, GetSize(cell->getPort(portname))-1, inverter);
-                       return bool_node(!inverter);
+                       return bool_node(inverter);
                }
 
                AigNode node;

diff --git a/passes/techmap/aig.cc b/passes/techmap/aig.cc
index 0c0f0b13077ba7730e3cd8875025789b4b2cb3d8..3bd078537b76f8a9d7ec8eae0ab791b198200c0e 100644 (file)
--- a/passes/techmap/aig.cc
+++ b/passes/techmap/aig.cc
@@ -90,12 +90,13 @@ struct AigPass : public Pass {
                                                bit = cell->getPort(node.portname)[node.portbit];
                                        } else if (node.left_parent < 0 && node.right_parent < 0) {
                                                bit = node.inverter ? State::S0 : State::S1;
+                                               goto skip_inverter;
                                        } else {
                                                SigBit A = sigs.at(node.left_parent);
                                                SigBit B = sigs.at(node.right_parent);
                                                if (nand_mode && node.inverter) {
                                                        bit = module->NandGate(NEW_ID, A, B);
-                                                       goto nand_inverter;
+                                                       goto skip_inverter;
                                                } else {
                                                        pair<int, int> key(node.left_parent, node.right_parent);
                                                        if (and_cache.count(key))
@@ -108,7 +109,7 @@ struct AigPass : public Pass {
                                        if (node.inverter)
                                                bit = module->NotGate(NEW_ID, bit);
                                
-                               nand_inverter:
+                               skip_inverter:
                                        for (auto &op : node.outports)
                                                module->connect(cell->getPort(op.first)[op.second], bit);
 

diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index 268f255981ceabb505e34081781401673b337f33..9a7934f55496422f19bc148ce4a91fcd7faf89ec 100644 (file)
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -536,6 +536,9 @@ struct TestCellPass : public Pass {
                log("    -simlib\n");
                log("        use \"techmap -map +/simlib.v -max_iter 2 -autoproc\"\n");
                log("\n");
+               log("    -aig\n");
+               log("        instead of calling \"techmap\", call \"aig\"\n");
+               log("\n");
                log("    -muxdiv\n");
                log("        when creating test benches with dividers, create an additional mux\n");
                log("        to mask out the division-by-zero case\n");
@@ -600,6 +603,10 @@ struct TestCellPass : public Pass {
                                techmap_cmd = "techmap -map +/simlib.v -max_iter 2 -autoproc";
                                continue;
                        }
+                       if (args[argidx] == "-aig") {
+                               techmap_cmd = "aig";
+                               continue;
+                       }
                        if (args[argidx] == "-muxdiv") {
                                muxdiv = true;
                                continue;