Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell()

diff --git a/kernel/celledges.cc b/kernel/celledges.cc
index 430425ea829b94d9292aeff79d439ad1ec8f05c4..556e8b826f4ee92fec8a9757d268cf1d6b17f28a 100644 (file)
--- a/kernel/celledges.cc
+++ b/kernel/celledges.cc
@@ -158,7 +158,7 @@ void mux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 
 PRIVATE_NAMESPACE_END
 
-bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_cell(RTLIL::Cell *cell)
+bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL::Cell *cell)
 {
        if (cell->type.in("$not", "$pos")) {
                bitwise_unary_op(this, cell);

diff --git a/kernel/celledges.h b/kernel/celledges.h
index e2cc408d7bcf62df8b65f7a6b948746879df608b..6aab9ed43b44899ff1da6bbacb139e8d68493570 100644 (file)
--- a/kernel/celledges.h
+++ b/kernel/celledges.h
@@ -29,7 +29,7 @@ struct AbstractCellEdgesDatabase
 {
        virtual ~AbstractCellEdgesDatabase() { }
        virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int delay) = 0;
-       bool add_cell(RTLIL::Cell *cell);
+       bool add_edges_from_cell(RTLIL::Cell *cell);
 };
 
 struct FwdCellEdgesDatabase : AbstractCellEdgesDatabase

diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index 8e9dc3112fe3c61e852cfcd34790f87b6cb9cd97..19fad01ef6813381989906a00cd44f95386f40bb 100644 (file)
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -344,7 +344,7 @@ static void run_edges_test(RTLIL::Design *design, bool verbose)
        SatGen satgen(&ez, &sigmap);
 
        FwdCellEdgesDatabase edges_db(sigmap);
-       if (!edges_db.add_cell(cell))
+       if (!edges_db.add_edges_from_cell(cell))
                log_error("Creating edge database failed for this cell!\n");
 
        dict<SigBit, pool<SigBit>> satgen_db;