litex/build/altera/common: added reset synchronizer

diff --git a/litex/build/altera/common.py b/litex/build/altera/common.py
index fafb4983796d4054374df9379dbe1037732e5fde..5d57391008b73425559749521854aacc1b5bc4c3 100644 (file)
--- a/litex/build/altera/common.py
+++ b/litex/build/altera/common.py
@@ -1,6 +1,9 @@
 from migen.fhdl.module import Module
 from migen.fhdl.specials import Instance
 from migen.genlib.io import DifferentialInput, DifferentialOutput
+from migen.genlib.resetsync import AsyncResetSynchronizer
+
+from migen.fhdl.structure import *
 
 
 class AlteraDifferentialInputImpl(Module):
@@ -32,8 +35,29 @@ class AlteraDifferentialOutput:
     def lower(dr):
         return AlteraDifferentialOutputImpl(dr.i, dr.o_p, dr.o_n)
 
+class AlteraAsyncResetSynchronizerImpl(Module):
+    def __init__(self, cd, async_reset):
+        if not hasattr(async_reset, "attr"):
+            i, async_reset = async_reset, Signal()
+            self.comb += async_reset.eq(i)
+        rst_meta = Signal()
+        self.specials += [
+            Instance("DFF", i_d=0, i_clk=cd.clk, i_clrn=1,
+                     i_prn=async_reset, o_q=rst_meta,
+                     attr={"async_reg", "ars_ff1"}),
+            Instance("DFF", i_d=rst_meta, i_clk=cd.clk, i_clrn=1,
+                     i_prn=async_reset,  o_q=cd.rst,
+                     attr={"async_reg", "ars_ff2"})
+        ]
+
+class AlteraAsyncResetSynchronizer:
+    @staticmethod
+    def lower(dr):
+        return AlteraAsyncResetSynchronizerImpl(dr.cd, dr.async_reset)
+
 
 altera_special_overrides = {
     DifferentialInput: AlteraDifferentialInput,
-    DifferentialOutput: AlteraDifferentialOutput
+    DifferentialOutput: AlteraDifferentialOutput,
+    AsyncResetSynchronizer: AlteraAsyncResetSynchronizer
 }