Re: [libre-riscv-dev] minimum viable ASIC

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+From: Staf Verhaegen <staf@fibraservi.eu>
+To: libre-riscv-dev@lists.libre-riscv.org
+Date: Fri, 08 May 2020 13:10:52 +0200
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+Luke Kenneth Casson Leighton schreef op vr 08-05-2020 om 11:42 [+0100]:
+> On Friday, May 8, 2020, Staf Verhaegen <staf@fibraservi.eu> wrote:
+> > Why only 24MHz without PLL ? You should have problems getting externalc=
+lock frequencies up to 100MHz without a problem inside a chip.
+>=20
+> really? great!  and that's driven from an external 100mhz clock?  it seem=
+sa little high, i guess i am used to SoCs which all run from a 24mhz XTAL.
+
+There exist clock generator chips, some of them even programmable over a se=
+rial bus interface. In the retro world amiga 75MHz accelerator cards or abo=
+ve are not unheard of.
+greets,Staf.
+
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