}")
(define_expand "modsi3"
- [(set (match_dup 3)
- (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" "")))
- (parallel [(set (match_dup 4) (ashift:SI (match_dup 3) (match_dup 5)))
- (clobber (scratch:SI))])
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (minus:SI (match_dup 1) (match_dup 4)))]
+ [(use (match_operand:SI 0 "gpc_reg_operand" ""))
+ (use (match_operand:SI 1 "gpc_reg_operand" ""))
+ (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
""
"
{
int i = exact_log2 (INTVAL (operands[2]));
+ rtx temp1 = gen_reg_rtx (SImode);
+ rtx temp2 = gen_reg_rtx (SImode);
if (GET_CODE (operands[2]) != CONST_INT || i < 0)
FAIL;
- operands[3] = gen_reg_rtx (SImode);
- operands[4] = gen_reg_rtx (SImode);
- operands[5] = gen_rtx (CONST_INT, VOIDmode, i);
+ emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
+ emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
+ emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
+ DONE;
+
}")
(define_insn ""