update comments

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index d93cb8266218d9a5a6c435f46292f033602022c0..730b00a271754bfff1832eb79128fb9239e65ba1 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -660,12 +660,14 @@ class SVP64Asm:
         else:
             v30b_op = v30b_op_orig
 
+        # look up the 32-bit op (original, with "," if it has it)
         if v30b_op_orig not in isa.instr:
             raise Exception("opcode %s of '%s' not supported" %
                             (v30b_op_orig, insn))
         else:
             isa_instr = isa.instr[v30b_op_orig]
 
+        # look up the svp64 op
         if v30b_op_orig not in svp64.instrs:
             if v30b_op in svp64.instrs:
                 rm = svp64.instrs[v30b_op]  # one row of the svp64 RM CSV
@@ -674,7 +676,9 @@ class SVP64Asm:
                                 f"{insn!r} not an svp64 instruction")
         else:
             rm = svp64.instrs[v30b_op_orig]  # one row of the svp64 RM CSV
-        v30b_regs = isa_instr.regs[0]  # get regs info "RT, RA, RB"
+
+        # get regs info e.g. "RT,RA,RB"
+        v30b_regs = isa_instr.regs[0]
         log("v3.0B op", v30b_op, "Rc=1" if rc_mode else '')
         log("v3.0B regs", opcode, v30b_regs)
         log("RM", rm)