csr/sram: fix reads on high addresses when word_bits != 0

diff --git a/migen/bus/csr.py b/migen/bus/csr.py
index fd812e9abee825b4c7bd768d04f193cc0edebff2..b0ed1966b202c868a0d9eda89c3fffdbd5a66b8d 100644 (file)
--- a/migen/bus/csr.py
+++ b/migen/bus/csr.py
@@ -107,10 +107,10 @@ class SRAM(Module):
                                ]
                
                if self._page is None:
-                       self.comb += port.adr.eq(self.bus.adr[word_bits:flen(port.adr)])
+                       self.comb += port.adr.eq(self.bus.adr[word_bits:word_bits+flen(port.adr)])
                else:
                        pv = self._page.storage
-                       self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:flen(port.adr)-flen(pv)], pv))
+                       self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:word_bits+flen(port.adr)-flen(pv)], pv))
 
        def get_csrs(self):
                if self._page is None: