This is similar to clflush_range except that it puts the mfence on the
other side to ensure caches are flushed prior to reading.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
}
}
+static inline void
+anv_invalidate_range(void *start, size_t size)
+{
+ void *p = (void *) (((uintptr_t) start) & ~CACHELINE_MASK);
+ void *end = start + size;
+
+ while (p < end) {
+ __builtin_ia32_clflush(p);
+ p += CACHELINE_SIZE;
+ }
+ __builtin_ia32_mfence();
+}
+
static void inline
anv_state_clflush(struct anv_state state)
{