(no commit message)

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index f8d5cbb950f14439001da09773ba77b7ac7eed52..47414bce783aa798b212490b0160de1daad3ba00 100644 (file)
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -287,6 +287,11 @@ required.
 useful, because it can be used to truncate VL to the first predicated
 (non-masked-out) element.
 
+*Programming note: One important point is that SVP64 instructions are 64 bit.
+(8 bytes not 4). This needs to be taken into consideration when computing
+branch offsets: the offset is relative to the start of the instruction,
+which includes the SVP64 Prefix*
+
 Available options to combine:
 
 * `BO[0]` to make an unconditional branch would seem irrelevant if
@@ -303,11 +308,6 @@ In addition to the above, it is necessary to select whether, in `svstep`
 mode, the Vector CR Field is to be overwritten or not: in some cases it
 is useful to know but in others all that is needed is the branch itself.
 
-*Programming note: One important point is that SVP64 instructions are 64 bit.
-(8 bytes not 4). This needs to be taken into consideration when computing
-branch offsets: the offset is relative to the start of the instruction,
-which includes the SVP64 Prefix*
-
 # Pseudocode and examples
 
 Pseudocode for Horizontal-First Mode: