add overview to requirements spec

diff --git a/3d_gpu/requirements_specification.mdwn b/3d_gpu/requirements_specification.mdwn
index 3430d260dc7b15542f04256297805f3b74f299df..d37a4249f82431e9f1438c7c127eb705e46b9750 100644 (file)
--- a/3d_gpu/requirements_specification.mdwn
+++ b/3d_gpu/requirements_specification.mdwn
@@ -29,7 +29,7 @@ An overview of the design is as follows:
   file.  The instruction will be scalar and will inherently and
   automatically parallelised by SV, just like all other scalar opcodes.
 * The register files will be stratified into 4-way 2R1W banks,
-  with byte-level write-enable on all banks.
+  with *separate* and distinct byte-level write-enable lines on all banks.
 * 6600-style scoreboards will be augmented with "shadow" wires
   and write hazard capability on exceptions, branch speculation,
   LD/ST and predication.