ffmuls test, had to add to b not a in expected results

diff --git a/src/openpower/decoder/isa/test_caller_svp64_fft.py b/src/openpower/decoder/isa/test_caller_svp64_fft.py
index 3001050b244619ae996690190eeecad1101b096d..181de64396407d2576b8aafba27d08a7e5f01441 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_fft.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_fft.py
@@ -185,7 +185,7 @@ class DecoderTestCase(FHDLTestCase):
             fprs[i+6] = fp64toselectable(b)
             fprs[i+10] = fp64toselectable(c)
             mul = a * c
-            t = a + mul
+            t = b + mul
             u = b - mul
             t = DOUBLE2SINGLE(fp64toselectable(t)) # convert to Power single
             u = DOUBLE2SINGLE(fp64toselectable(u)) # from double