sim_ticks 1907083088000 # Number of ticks simulated
final_tick 1907083088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 20329 # Simulator instruction rate (inst/s)
-host_op_rate 20329 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 690572794 # Simulator tick rate (ticks/s)
-host_mem_usage 384580 # Number of bytes of host memory used
-host_seconds 2761.60 # Real time elapsed on the host
+host_inst_rate 17729 # Simulator instruction rate (inst/s)
+host_op_rate 17729 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 602270723 # Simulator tick rate (ticks/s)
+host_mem_usage 432228 # Number of bytes of host memory used
+host_seconds 3166.49 # Real time elapsed on the host
sim_insts 56139550 # Number of instructions simulated
sim_ops 56139550 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 1045632 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24852608 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 40135521250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 15213605 # Number of BP lookups
system.cpu.branchPred.condPredicted 13089935 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 512661 # Number of conditional branches incorrect
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.numPwrStateTransitions 12752 # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples 6376 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean 281609048.541405 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev 439540029.573258 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10 6376 100.00% 100.00% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::min_value 10500 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::total 6376 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::ON 111543794500 # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 1795539293500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 223105667 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.kern.swap_context 4178 # number of times the context was actually changed
system.cpu.tickCycles 85299333 # Number of cycles that the object actually ticked
system.cpu.idleCycles 137806334 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 1394573 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.976747 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 13828974 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 63880747 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 63880747 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 7869575 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 7869575 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 5576818 # number of WriteReq hits
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220578.354978 # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92346.281641 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92346.281641 # average overall mshr uncacheable latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 1471396 # number of replacements
system.cpu.icache.tags.tagsinuse 508.107952 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 19138982 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 22083145 # Number of tag accesses
system.cpu.icache.tags.data_accesses 22083145 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 19138985 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 19138985 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 19138985 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 13369.070974 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13369.070974 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13369.070974 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 339491 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65257.604073 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 5020229 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 46558497 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 46558497 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 837991 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 837991 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1470820 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 1250 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1250 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2570147 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 9623 # Transaction distribution
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
+system.iobus.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
system.iobus.trans_dist::WriteReq 51175 # Transaction distribution
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 41685 # number of replacements
system.iocache.tags.tagsinuse 1.298739 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 375525 # Number of tag accesses
system.iocache.tags.data_accesses 375525 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
system.iocache.demand_avg_mshr_miss_latency::total 76193.945261 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76193.945261 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 76193.945261 # average overall mshr miss latency
+system.membus.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 6930 # Transaction distribution
system.membus.trans_dist::ReadResp 295608 # Transaction distribution
system.membus.trans_dist::WriteReq 9623 # Transaction distribution
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
system.membus.respLayer2.occupancy 943117 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
+system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
+system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
+system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
+system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
+system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
+system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
+system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states
---------- End Simulation Statistics ----------
sim_ticks 1908652088000 # Number of ticks simulated
final_tick 1908652088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 169428 # Simulator instruction rate (inst/s)
-host_op_rate 169428 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5757307258 # Simulator tick rate (ticks/s)
-host_mem_usage 336708 # Number of bytes of host memory used
-host_seconds 331.52 # Real time elapsed on the host
+host_inst_rate 205918 # Simulator instruction rate (inst/s)
+host_op_rate 205918 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6997264233 # Simulator tick rate (ticks/s)
+host_mem_usage 384940 # Number of bytes of host memory used
+host_seconds 272.77 # Real time elapsed on the host
sim_insts 56168509 # Number of instructions simulated
sim_ops 56168509 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.inst 873216 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 24648192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 103232 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 23527607250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
system.cpu0.branchPred.lookups 18555851 # Number of BP lookups
system.cpu0.branchPred.condPredicted 15805635 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 543843 # Number of conditional branches incorrect
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
+system.cpu0.numPwrStateTransitions 12751 # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples 6376 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean 289891468.868256 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev 443092480.248663 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows 4 0.06% 0.06% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10 6372 99.94% 100.00% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total 6376 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON 60304082496 # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 1848348005504 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 120614537 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.fp_regfile_writes 153221 # number of floating regfile writes
system.cpu0.misc_regfile_reads 1866400 # number of misc regfile reads
system.cpu0.misc_regfile_writes 877434 # number of misc regfile writes
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 1337856 # number of replacements
system.cpu0.dcache.tags.tagsinuse 505.906059 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 11855471 # Total number of references to valid blocks.
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 62973100 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 62973100 # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 7528886 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 7528886 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3919891 # number of WriteReq hits
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222625.620303 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93130.397390 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93130.397390 # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 1021310 # number of replacements
system.cpu0.icache.tags.tagsinuse 509.519684 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 8197716 # Total number of references to valid blocks.
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 10303980 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 10303980 # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 8197716 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 8197716 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 8197716 # number of demand (read+write) hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
+system.cpu1.numPwrStateTransitions 4618 # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples 2309 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean 824384353.183196 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev 333980461.680684 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10 2309 100.00% 100.00% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::min_value 88500 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::max_value 975572500 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total 2309 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON 5148616500 # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 1903503471500 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 10299543 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.fp_regfile_writes 25344 # number of floating regfile writes
system.cpu1.misc_regfile_reads 302216 # number of misc regfile reads
system.cpu1.misc_regfile_writes 137559 # number of misc regfile writes
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements 64410 # number of replacements
system.cpu1.dcache.tags.tagsinuse 463.614906 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 1794834 # Total number of references to valid blocks.
system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 8336582 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 8336582 # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data 1188882 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 1188882 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 570377 # number of WriteReq hits
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202982.876712 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 10855.494505 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 10855.494505 # average overall mshr uncacheable latency
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements 125381 # number of replacements
system.cpu1.icache.tags.tagsinuse 466.454678 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 1056750 # Total number of references to valid blocks.
system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 1315314 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 1315314 # Number of data accesses
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst 1056751 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 1056751 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 1056751 # number of demand (read+write) hits
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
+system.iobus.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 7381 # Transaction distribution
system.iobus.trans_dist::ReadResp 7381 # Transaction distribution
system.iobus.trans_dist::WriteReq 53943 # Transaction distribution
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 41964000 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 41702 # number of replacements
system.iocache.tags.tagsinuse 0.516326 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 375606 # Number of tag accesses
system.iocache.tags.data_accesses 375606 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::tsunami.ide 182 # number of ReadReq misses
system.iocache.ReadReq_misses::total 182 # number of ReadReq misses
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
system.iocache.demand_avg_mshr_miss_latency::total 66945.590885 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66945.590885 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 66945.590885 # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 344399 # number of replacements
system.l2c.tags.tagsinuse 65257.528904 # Cycle average of tags in use
system.l2c.tags.total_refs 4049043 # Total number of references to valid blocks.
system.l2c.tags.occ_task_id_percent::1024 0.991791 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 38854214 # Number of tag accesses
system.l2c.tags.data_accesses 38854214 # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 830750 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 830750 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 873391 # number of WritebackClean hits
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 7199 # Transaction distribution
system.membus.trans_dist::ReadResp 297053 # Transaction distribution
system.membus.trans_dist::WriteReq 12391 # Transaction distribution
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
system.membus.respLayer2.occupancy 976613 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 5115302 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 2557070 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 337938 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 1067 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 999 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2263337 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 12391 # Transaction distribution
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 107558787 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
+system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
+system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
+system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
+system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
+system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
+system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
+system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 6376 # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei 198541 # number of hwrei instructions executed
sim_ticks 1876794488000 # Number of ticks simulated
final_tick 1876794488000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 156335 # Simulator instruction rate (inst/s)
-host_op_rate 156335 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5537786455 # Simulator tick rate (ticks/s)
-host_mem_usage 329540 # Number of bytes of host memory used
-host_seconds 338.91 # Real time elapsed on the host
+host_inst_rate 191271 # Simulator instruction rate (inst/s)
+host_op_rate 191271 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6775305946 # Simulator tick rate (ticks/s)
+host_mem_usage 377772 # Number of bytes of host memory used
+host_seconds 277.01 # Real time elapsed on the host
sim_insts 52982943 # Number of instructions simulated
sim_ops 52982943 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 961728 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24880448 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 30709733500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 19569408 # Number of BP lookups
system.cpu.branchPred.condPredicted 16632311 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 593173 # Number of conditional branches incorrect
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.numPwrStateTransitions 12876 # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples 6438 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean 279467835.818577 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev 439243252.658256 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10 6438 100.00% 100.00% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::min_value 81000 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::total 6438 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::ON 77580561000 # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 1799213927000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 155167561 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fp_regfile_writes 175794 # number of floating regfile writes
system.cpu.misc_regfile_reads 2001927 # number of misc regfile reads
system.cpu.misc_regfile_writes 939529 # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 1405900 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.992670 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 12627832 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 67144149 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 67144149 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 8017767 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 8017767 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4181578 # number of WriteReq hits
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220582.828283 # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92482.243330 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92482.243330 # average overall mshr uncacheable latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 1074186 # number of replacements
system.cpu.icache.tags.tagsinuse 507.868793 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 8786985 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 11005600 # Number of tag accesses
system.cpu.icache.tags.data_accesses 11005600 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 8786985 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 8786985 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 8786985 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 13860.792543 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13860.792543 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13860.792543 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 338591 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65285.567334 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 4253578 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994385 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 40379667 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 40379667 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 843569 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 843569 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1073682 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 1198 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1198 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2188672 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 9599 # Transaction distribution
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
+system.iobus.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
system.iobus.trans_dist::WriteReq 51151 # Transaction distribution
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 41685 # number of replacements
system.iocache.tags.tagsinuse 1.249213 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 375525 # Number of tag accesses
system.iocache.tags.data_accesses 375525 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
system.iocache.demand_avg_mshr_miss_latency::total 76218.750246 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76218.750246 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 76218.750246 # average overall mshr miss latency
+system.membus.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 6930 # Transaction distribution
system.membus.trans_dist::ReadResp 296606 # Transaction distribution
system.membus.trans_dist::WriteReq 9599 # Transaction distribution
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
system.membus.respLayer2.occupancy 918617 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
+system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
+system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
+system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
+system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
+system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
+system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
+system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
+system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 6438 # number of quiesce instructions executed
system.cpu.kern.inst.hwrei 211036 # number of hwrei instructions executed
sim_ticks 1841599161000 # Number of ticks simulated
final_tick 1841599161000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 245408 # Simulator instruction rate (inst/s)
-host_op_rate 245408 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6773643024 # Simulator tick rate (ticks/s)
-host_mem_usage 331844 # Number of bytes of host memory used
-host_seconds 271.88 # Real time elapsed on the host
+host_inst_rate 307539 # Simulator instruction rate (inst/s)
+host_op_rate 307539 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 8488565495 # Simulator tick rate (ticks/s)
+host_mem_usage 380848 # Number of bytes of host memory used
+host_seconds 216.95 # Real time elapsed on the host
sim_insts 66720805 # Number of instructions simulated
sim_ops 66720805 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.inst 472448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 20115392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 147008 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 8896844750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
+system.cpu0.numPwrStateTransitions 6508 # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples 3254 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean 553026714.363860 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev 1352809149.832599 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10 3254 100.00% 100.00% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::min_value 213500 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::max_value 3905515000 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total 3254 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON 42050232460 # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 1799548928540 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 928788202 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.op_class::IprAccess 516318 1.72% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 30035361 # Class of executed instruction
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 1394566 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.997816 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 13521910 # Total number of references to valid blocks.
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 64423039 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 64423039 # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 3984765 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 1069804 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 2772856 # number of ReadReq hits
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 97107.965638 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 99971.120575 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 98810.541311 # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 969876 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.205246 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 39683030 # Total number of references to valid blocks.
system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 41646260 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 41646260 # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 29526010 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 7417850 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 2739170 # number of ReadReq hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
+system.cpu1.numPwrStateTransitions 2293 # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples 1147 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean 1553407081.081081 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev 1902806399.455202 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10 1147 100.00% 100.00% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::min_value 400000 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::max_value 6635637500 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total 1147 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON 59841239000 # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 1781757922000 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 953375365 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.itb.data_misses 0 # DTB misses
system.cpu2.itb.data_acv 0 # DTB access violations
system.cpu2.itb.data_accesses 0 # DTB accesses
+system.cpu2.numPwrStateTransitions 3116 # Number of power state transitions
+system.cpu2.pwrStateClkGateDist::samples 1558 # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::mean 289379505.134788 # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::stdev 445107312.150922 # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::1000-5e+10 1558 100.00% 100.00% # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::min_value 3000 # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::total 1558 # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateResidencyTicks::ON 1390745892000 # Cumulative time (in ticks) in various power states
+system.cpu2.pwrStateResidencyTicks::CLK_GATED 450853269000 # Cumulative time (in ticks) in various power states
system.cpu2.numCycles 30327275 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
+system.iobus.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 7317 # Transaction distribution
system.iobus.trans_dist::ReadResp 7317 # Transaction distribution
system.iobus.trans_dist::WriteReq 51362 # Transaction distribution
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 17468000 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 41685 # number of replacements
system.iocache.tags.tagsinuse 1.254561 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 375525 # Number of tag accesses
system.iocache.tags.data_accesses 375525 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
system.iocache.demand_avg_mshr_miss_latency::total 66910.723631 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66910.723631 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 66910.723631 # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 337756 # number of replacements
system.l2c.tags.tagsinuse 65421.322565 # Cycle average of tags in use
system.l2c.tags.total_refs 4020988 # Total number of references to valid blocks.
system.l2c.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 38533534 # Number of tag accesses
system.l2c.tags.data_accesses 38533534 # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 836681 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 836681 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 969577 # number of WritebackClean hits
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 7144 # Transaction distribution
system.membus.trans_dist::ReadResp 295138 # Transaction distribution
system.membus.trans_dist::WriteReq 9810 # Transaction distribution
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 370538 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 4730181 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 2364664 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 1672 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 1038 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 1038 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 7144 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2070392 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 9810 # Transaction distribution
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 770446828 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
+system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
+system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
+system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
+system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
+system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
+system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
+system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed
sim_ticks 2847227406000 # Number of ticks simulated
final_tick 2847227406000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 111277 # Simulator instruction rate (inst/s)
-host_op_rate 134747 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2488466073 # Simulator tick rate (ticks/s)
-host_mem_usage 617520 # Number of bytes of host memory used
-host_seconds 1144.17 # Real time elapsed on the host
+host_inst_rate 262523 # Simulator instruction rate (inst/s)
+host_op_rate 317894 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5870765699 # Simulator tick rate (ticks/s)
+host_mem_usage 664268 # Number of bytes of host memory used
+host_seconds 484.98 # Real time elapsed on the host
sim_insts 127319545 # Number of instructions simulated
sim_ops 154173476 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker 7488 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 1647744 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 31288281989 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory
system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cpu0.branchPred.indirectMisses 178910 # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted 99353 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks 68420 # Table walker walks requested
system.cpu0.dtb.walker.walksShort 68420 # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46092 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.hits 31880381 # DTB hits
system.cpu0.dtb.misses 68420 # DTB misses
system.cpu0.dtb.accesses 31948801 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks 3977 # Table walker walks requested
system.cpu0.itb.walker.walksShort 3977 # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1 304 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.hits 38606266 # DTB hits
system.cpu0.itb.misses 3977 # DTB misses
system.cpu0.itb.accesses 38610243 # DTB accesses
+system.cpu0.numPwrStateTransitions 3704 # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples 1852 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean 1492233091.644168 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev 23940880637.068275 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows 1073 57.94% 57.94% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10 772 41.68% 99.62% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.68% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.05% 99.73% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::max_value 499965331660 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total 1852 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON 83611720275 # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 2763615685725 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 167224982 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.kern.inst.quiesce 1852 # number of quiesce instructions executed
system.cpu0.tickCycles 128530134 # Number of cycles that the object actually ticked
system.cpu0.idleCycles 38694848 # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 715130 # number of replacements
system.cpu0.dcache.tags.tagsinuse 500.249385 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 30394670 # Total number of references to valid blocks.
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 63780153 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 63780153 # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 15810332 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 15810332 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 13424812 # number of WriteReq hits
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 224330.935601 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115836.194348 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115836.194348 # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 1962004 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.774944 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 36636559 # Total number of references to valid blocks.
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 79160710 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 79160710 # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 36636559 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 36636559 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 36636559 # number of demand (read+write) hits
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92626.848362 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92626.848362 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92626.848362 # average overall mshr uncacheable latency
+system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued 1841200 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 1841258 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 51 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 233630 # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements 298119 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 16125.660847 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 4682482 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.922546 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 89320549 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 89320549 # Number of data accesses
+system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 82730 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5417 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 88147 # number of ReadReq hits
system.cpu0.toL2Bus.snoop_filter.tot_snoops 346625 # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 340732 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5893 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq 122459 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 2635557 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 19271 # Transaction distribution
system.cpu1.branchPred.indirectHits 3516137 # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses 62926 # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted 23615 # Number of mispredicted indirect branches.
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks 26974 # Table walker walks requested
system.cpu1.dtb.walker.walksShort 26974 # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 20087 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.hits 18177508 # DTB hits
system.cpu1.dtb.misses 26974 # DTB misses
system.cpu1.dtb.accesses 18204482 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks 2420 # Table walker walks requested
system.cpu1.itb.walker.walksShort 2420 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.hits 39602800 # DTB hits
system.cpu1.itb.misses 2420 # DTB misses
system.cpu1.itb.accesses 39605220 # DTB accesses
+system.cpu1.numPwrStateTransitions 5553 # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples 2777 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean 1004505001.039251 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev 25654466824.490025 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows 1974 71.08% 71.08% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10 799 28.77% 99.86% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::max_value 949981296504 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total 2777 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON 57717018114 # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 2789510387886 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 115435582 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.kern.inst.quiesce 2777 # number of quiesce instructions executed
system.cpu1.tickCycles 97896037 # Number of cycles that the object actually ticked
system.cpu1.idleCycles 17539545 # Total number of cycles that the object has spent stopped
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements 196286 # number of replacements
system.cpu1.dcache.tags.tagsinuse 471.109798 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 17737294 # Total number of references to valid blocks.
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.669922 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 36398755 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 36398755 # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data 10795076 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 10795076 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 6704752 # number of WriteReq hits
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171920.653078 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 94713.295394 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 94713.295394 # average overall mshr uncacheable latency
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements 946364 # number of replacements
system.cpu1.icache.tags.tagsinuse 499.210861 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 38654025 # Total number of references to valid blocks.
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 80148678 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 80148678 # Number of data accesses
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst 38654025 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 38654025 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 38654025 # number of demand (read+write) hits
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 93522.321429 # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93522.321429 # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 93522.321429 # average overall mshr uncacheable latency
+system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued 199879 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 199934 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 48 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 58626 # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements 53638 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 15286.424872 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 2058198 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.840820 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 38543839 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 38543839 # Number of data accesses
+system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 30076 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 3135 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 33211 # number of ReadReq hits
system.cpu1.toL2Bus.snoop_filter.tot_snoops 192169 # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 190372 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1797 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq 53056 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 1216172 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 11758 # Transaction distribution
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy 33872477 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 31003 # Transaction distribution
system.iobus.trans_dist::ReadResp 31003 # Transaction distribution
system.iobus.trans_dist::WriteReq 59422 # Transaction distribution
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 36449 # number of replacements
system.iocache.tags.tagsinuse 14.476064 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328203 # Number of tag accesses
system.iocache.tags.data_accesses 328203 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses
system.iocache.ReadReq_misses::total 243 # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.demand_avg_mshr_miss_latency::total 68759.610031 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 68759.610031 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 68759.610031 # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 131721 # number of replacements
system.l2c.tags.tagsinuse 63119.316885 # Cycle average of tags in use
system.l2c.tags.total_refs 480965 # Total number of references to valid blocks.
system.l2c.tags.occ_task_id_percent::1024 0.554291 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 6440622 # Number of tag accesses
system.l2c.tags.data_accesses 6440622 # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 269250 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 269250 # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data 33826 # number of UpgradeReq hits
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 38557 # Transaction distribution
system.membus.trans_dist::ReadResp 213679 # Transaction distribution
system.membus.trans_dist::WriteReq 31029 # Transaction distribution
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 1318131 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 1068358 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 578478 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 169754 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 19773 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 18732 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 1041 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 38560 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 513452 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 31029 # Transaction distribution
sim_ticks 2858505242500 # Number of ticks simulated
final_tick 2858505242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 125507 # Simulator instruction rate (inst/s)
-host_op_rate 151748 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3206183180 # Simulator tick rate (ticks/s)
-host_mem_usage 578080 # Number of bytes of host memory used
-host_seconds 891.56 # Real time elapsed on the host
+host_inst_rate 258042 # Simulator instruction rate (inst/s)
+host_op_rate 311992 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6591883972 # Simulator tick rate (ticks/s)
+host_mem_usage 625700 # Number of bytes of host memory used
+host_seconds 433.64 # Real time elapsed on the host
sim_insts 111897168 # Number of instructions simulated
sim_ops 135292215 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.dtb.walker 7872 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 1705984 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 34173617000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 512 # Number of instructions bytes read from this memory
system.realview.nvmem.bw_inst_read::total 179 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 179 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 179 # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cpu.branchPred.indirectMisses 187135 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 108257 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 66151 # Table walker walks requested
system.cpu.dtb.walker.walksShort 66151 # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43510 # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.hits 44135237 # DTB hits
system.cpu.dtb.misses 66151 # DTB misses
system.cpu.dtb.accesses 44201388 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 5761 # Table walker walks requested
system.cpu.itb.walker.walksShort 5761 # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walksShortTerminationLevel::Level1 327 # Level at which table walker walks with short descriptors terminate
system.cpu.itb.hits 57333922 # DTB hits
system.cpu.itb.misses 5761 # DTB misses
system.cpu.itb.accesses 57339683 # DTB accesses
+system.cpu.numPwrStateTransitions 6066 # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples 3033 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean 887601126.287174 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev 17445279478.153702 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::underflows 2969 97.89% 97.89% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10 58 1.91% 99.80% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::max_value 499966497156 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::total 3033 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::ON 166411026471 # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 2692094216029 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 332822103 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed
system.cpu.tickCycles 228131430 # Number of cycles that the object actually ticked
system.cpu.idleCycles 104690673 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 842468 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.899803 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 42541759 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 175934555 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 175934555 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 23016255 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 23016255 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 18262413 # number of WriteReq hits
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201679.548959 # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106928.531280 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106928.531280 # average overall mshr uncacheable latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 2894371 # number of replacements
system.cpu.icache.tags.tagsinuse 511.208818 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 54430342 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 60220131 # Number of tag accesses
system.cpu.icache.tags.data_accesses 60220131 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 54430342 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 54430342 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 54430342 # number of demand (read+write) hits
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 129131.411108 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 129131.411108 # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 129131.411108 # average overall mshr uncacheable latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 96490 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65016.669962 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 7024998 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994766 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 60430282 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 60430282 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 71969 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4812 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 76781 # number of ReadReq hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 592 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 592 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq 134878 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 3577264 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy 88824919 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 30183 # Transaction distribution
system.iobus.trans_dist::ReadResp 30183 # Transaction distribution
system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 36424 # number of replacements
system.iocache.tags.tagsinuse 1.037066 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328122 # Number of tag accesses
system.iocache.tags.data_accesses 328122 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses
system.iocache.ReadReq_misses::total 234 # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.demand_avg_mshr_miss_latency::total 75531.049344 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 75531.049344 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 75531.049344 # average overall mshr miss latency
+system.membus.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 34891 # Transaction distribution
system.membus.trans_dist::ReadResp 72400 # Transaction distribution
system.membus.trans_dist::WriteReq 27583 # Transaction distribution
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 1263123 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states
---------- End Simulation Statistics ----------
sim_ticks 2832862976500 # Number of ticks simulated
final_tick 2832862976500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 104475 # Simulator instruction rate (inst/s)
-host_op_rate 126719 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2616817312 # Simulator tick rate (ticks/s)
-host_mem_usage 625044 # Number of bytes of host memory used
-host_seconds 1082.56 # Real time elapsed on the host
+host_inst_rate 118022 # Simulator instruction rate (inst/s)
+host_op_rate 143150 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2956132692 # Simulator tick rate (ticks/s)
+host_mem_usage 626728 # Number of bytes of host memory used
+host_seconds 958.30 # Real time elapsed on the host
sim_insts 113100501 # Number of instructions simulated
sim_ops 137180951 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 1320384 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 30651593250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu.inst 112 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 112 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 112 # Number of instructions bytes read from this memory
system.realview.nvmem.bw_inst_read::total 40 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 40 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 40 # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cpu.branchPred.indirectMisses 146221 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 60350 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.cpu.checker.dtb.walker.walks 9708 # Table walker walks requested
system.cpu.checker.dtb.walker.walksShort 9708 # Table walker walks initiated with short descriptors
system.cpu.checker.dtb.walker.walkWaitTime::samples 9708 # Table walker wait (enqueue to first request) latency
system.cpu.checker.dtb.hits 44208974 # DTB hits
system.cpu.checker.dtb.misses 9708 # DTB misses
system.cpu.checker.dtb.accesses 44218682 # DTB accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.cpu.checker.itb.walker.walks 4825 # Table walker walks requested
system.cpu.checker.itb.walker.walksShort 4825 # Table walker walks initiated with short descriptors
system.cpu.checker.itb.walker.walkWaitTime::samples 4825 # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.hits 115798779 # DTB hits
system.cpu.checker.itb.misses 4825 # DTB misses
system.cpu.checker.itb.accesses 115803604 # DTB accesses
+system.cpu.checker.pwrStateResidencyTicks::ON 2832862976500 # Cumulative time (in ticks) in various power states
system.cpu.checker.numCycles 139031272 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 72368 # Table walker walks requested
system.cpu.dtb.walker.walksShort 72368 # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29394 # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.hits 45276053 # DTB hits
system.cpu.dtb.misses 72368 # DTB misses
system.cpu.dtb.accesses 45348421 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 12817 # Table walker walks requested
system.cpu.itb.walker.walksShort 12817 # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walksShortTerminationLevel::Level1 3368 # Level at which table walker walks with short descriptors terminate
system.cpu.itb.hits 65995629 # DTB hits
system.cpu.itb.misses 12817 # DTB misses
system.cpu.itb.accesses 66008446 # DTB accesses
+system.cpu.numPwrStateTransitions 6074 # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples 3037 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean 886944690.993085 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev 17421692807.288013 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::underflows 2966 97.66% 97.66% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10 65 2.14% 99.80% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.07% 99.90% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::max_value 499972175752 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::total 3037 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::ON 139211949954 # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 2693651026546 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 278423951 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.cc_regfile_writes 53129749 # number of cc regfile writes
system.cpu.misc_regfile_reads 459440694 # number of misc regfile reads
system.cpu.misc_regfile_writes 1521708 # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 838747 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.925928 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 40056711 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 179125109 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 179125109 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 23264148 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 23264148 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 15542286 # number of WriteReq hits
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201621.381991 # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106895.663726 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106895.663726 # average overall mshr uncacheable latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 1886245 # number of replacements
system.cpu.icache.tags.tagsinuse 511.154077 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 64013417 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 67878198 # Number of tag accesses
system.cpu.icache.tags.data_accesses 67878198 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 64013417 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 64013417 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 64013417 # number of demand (read+write) hits
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125742.757243 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125742.757243 # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125742.757243 # average overall mshr uncacheable latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 96776 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65028.780058 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 5006507 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996582 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 44296182 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 44296182 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 58073 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12060 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 70133 # number of ReadReq hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 378 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 378 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq 128774 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2557731 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy 75872379 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 30172 # Transaction distribution
system.iobus.trans_dist::ReadResp 30172 # Transaction distribution
system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 36718000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 36413 # number of replacements
system.iocache.tags.tagsinuse 1.005739 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328023 # Number of tag accesses
system.iocache.tags.data_accesses 328023 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide 223 # number of ReadReq misses
system.iocache.ReadReq_misses::total 223 # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.demand_avg_mshr_miss_latency::total 75607.319560 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 75607.319560 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 75607.319560 # average overall mshr miss latency
+system.membus.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 34132 # Transaction distribution
system.membus.trans_dist::ReadResp 67490 # Transaction distribution
system.membus.trans_dist::WriteReq 27585 # Transaction distribution
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 1182123 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed
sim_ticks 2825959731500 # Number of ticks simulated
final_tick 2825959731500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 152939 # Simulator instruction rate (inst/s)
-host_op_rate 185526 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3598106166 # Simulator tick rate (ticks/s)
-host_mem_usage 665816 # Number of bytes of host memory used
-host_seconds 785.40 # Real time elapsed on the host
+host_inst_rate 153141 # Simulator instruction rate (inst/s)
+host_op_rate 185771 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3602870624 # Simulator tick rate (ticks/s)
+host_mem_usage 666712 # Number of bytes of host memory used
+host_seconds 784.36 # Real time elapsed on the host
sim_insts 120118276 # Number of instructions simulated
sim_ops 145712235 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 1306176 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 26750317702 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 288 # Number of bytes read from this memory
system.realview.nvmem.bw_total::cpu0.inst 40 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 62 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 102 # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cpu0.branchPred.indirectMisses 155489 # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted 48572 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks 67255 # Table walker walks requested
system.cpu0.dtb.walker.walksShort 67255 # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25406 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.hits 41220590 # DTB hits
system.cpu0.dtb.misses 67255 # DTB misses
system.cpu0.dtb.accesses 41287845 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks 10944 # Table walker walks requested
system.cpu0.itb.walker.walksShort 10944 # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3906 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.hits 72708872 # DTB hits
system.cpu0.itb.misses 10944 # DTB misses
system.cpu0.itb.accesses 72719816 # DTB accesses
+system.cpu0.numPwrStateTransitions 3656 # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples 1828 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean 1490596475.785011 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev 23949118810.105305 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows 1055 57.71% 57.71% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10 768 42.01% 99.73% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::max_value 499973380096 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total 1828 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON 101149373765 # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 2724810357735 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 202299816 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.cc_regfile_writes 49725456 # number of cc regfile writes
system.cpu0.misc_regfile_reads 388373326 # number of misc regfile reads
system.cpu0.misc_regfile_writes 1224889 # number of misc regfile writes
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 709828 # number of replacements
system.cpu0.dcache.tags.tagsinuse 497.174198 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 37665141 # Total number of references to valid blocks.
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 81170296 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 81170296 # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 21454849 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 21454849 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 14988122 # number of WriteReq hits
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208398.429385 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109945.475831 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109945.475831 # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 1253795 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.762128 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 71396857 # Total number of references to valid blocks.
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 146664376 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 146664376 # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 71396857 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 71396857 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 71396857 # number of demand (read+write) hits
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89625.540460 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89625.540460 # average overall mshr uncacheable latency
+system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued 1837870 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 1840472 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 2353 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 236752 # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements 276743 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 16098.325627 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 3280707 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.921692 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 66287217 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 66287217 # Number of data accesses
+system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 55484 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 13243 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 68727 # number of ReadReq hits
system.cpu0.toL2Bus.snoop_filter.tot_snoops 323545 # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 318913 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4632 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq 114042 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 1911688 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 28450 # Transaction distribution
system.cpu1.branchPred.indirectHits 213575 # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses 35567 # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted 10613 # Number of mispredicted indirect branches.
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks 21410 # Table walker walks requested
system.cpu1.dtb.walker.walksShort 21410 # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8641 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.hits 7689335 # DTB hits
system.cpu1.dtb.misses 21410 # DTB misses
system.cpu1.dtb.accesses 7710745 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks 5994 # Table walker walks requested
system.cpu1.itb.walker.walksShort 5994 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2734 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.hits 8253439 # DTB hits
system.cpu1.itb.misses 5994 # DTB misses
system.cpu1.itb.accesses 8259433 # DTB accesses
+system.cpu1.numPwrStateTransitions 5525 # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples 2763 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean 1016473602.620702 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev 25821981878.711128 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows 1969 71.26% 71.26% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10 788 28.52% 99.78% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.86% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::max_value 959984667908 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total 2763 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON 17443167459 # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 2808516564041 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 34887121 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.cc_regfile_writes 6816973 # number of cc regfile writes
system.cpu1.misc_regfile_reads 66091366 # number of misc regfile reads
system.cpu1.misc_regfile_writes 387254 # number of misc regfile writes
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements 189214 # number of replacements
system.cpu1.dcache.tags.tagsinuse 472.223119 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 6799121 # Total number of references to valid blocks.
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.654297 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 15096738 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 15096738 # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data 3630827 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 3630827 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 2915447 # number of WriteReq hits
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143594.866797 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 80171.413024 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 80171.413024 # average overall mshr uncacheable latency
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements 585593 # number of replacements
system.cpu1.icache.tags.tagsinuse 499.448296 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 7643805 # Total number of references to valid blocks.
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 17090093 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 17090093 # Number of data accesses
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst 7643805 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 7643805 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 7643805 # number of demand (read+write) hits
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90480.392157 # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90480.392157 # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90480.392157 # average overall mshr uncacheable latency
+system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued 204984 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 205710 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 651 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 59802 # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements 51951 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 15270.218898 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 1330892 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.826477 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 26699823 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 26699823 # Number of data accesses
+system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 16755 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 6229 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 22984 # number of ReadReq hits
system.cpu1.toL2Bus.snoop_filter.tot_snoops 183176 # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 180762 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2414 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq 31669 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 826741 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 2435 # Transaction distribution
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy 20485966 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 31012 # Transaction distribution
system.iobus.trans_dist::ReadResp 31012 # Transaction distribution
system.iobus.trans_dist::WriteReq 59421 # Transaction distribution
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 36458 # number of replacements
system.iocache.tags.tagsinuse 14.555465 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328284 # Number of tag accesses
system.iocache.tags.data_accesses 328284 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.demand_avg_mshr_miss_latency::total 68813.138529 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 68813.138529 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 68813.138529 # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 132778 # number of replacements
system.l2c.tags.tagsinuse 63203.828730 # Cycle average of tags in use
system.l2c.tags.total_refs 444088 # Total number of references to valid blocks.
system.l2c.tags.occ_task_id_percent::1024 0.527679 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 6131058 # Number of tag accesses
system.l2c.tags.data_accesses 6131058 # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 266860 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 266860 # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data 32430 # number of UpgradeReq hits
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 37951 # Transaction distribution
system.membus.trans_dist::ReadResp 212466 # Transaction distribution
system.membus.trans_dist::WriteReq 30885 # Transaction distribution
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 1360881 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 1012829 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 548493 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 154614 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 20965 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 19995 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 970 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 37954 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 485832 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 30885 # Transaction distribution
sim_ticks 2832862976500 # Number of ticks simulated
final_tick 2832862976500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 159961 # Simulator instruction rate (inst/s)
-host_op_rate 194019 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4006592882 # Simulator tick rate (ticks/s)
-host_mem_usage 625056 # Number of bytes of host memory used
-host_seconds 707.05 # Real time elapsed on the host
+host_inst_rate 159277 # Simulator instruction rate (inst/s)
+host_op_rate 193189 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3989457396 # Simulator tick rate (ticks/s)
+host_mem_usage 626716 # Number of bytes of host memory used
+host_seconds 710.09 # Real time elapsed on the host
sim_insts 113100501 # Number of instructions simulated
sim_ops 137180951 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 1320384 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 30651593250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu.inst 112 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 112 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 112 # Number of instructions bytes read from this memory
system.realview.nvmem.bw_inst_read::total 40 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 40 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 40 # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cpu.branchPred.indirectMisses 146221 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 60350 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 72368 # Table walker walks requested
system.cpu.dtb.walker.walksShort 72368 # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29394 # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.hits 45276053 # DTB hits
system.cpu.dtb.misses 72368 # DTB misses
system.cpu.dtb.accesses 45348421 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 12817 # Table walker walks requested
system.cpu.itb.walker.walksShort 12817 # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walksShortTerminationLevel::Level1 3368 # Level at which table walker walks with short descriptors terminate
system.cpu.itb.hits 65995629 # DTB hits
system.cpu.itb.misses 12817 # DTB misses
system.cpu.itb.accesses 66008446 # DTB accesses
+system.cpu.numPwrStateTransitions 6074 # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples 3037 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean 886944690.993085 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev 17421692807.288013 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::underflows 2966 97.66% 97.66% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10 65 2.14% 99.80% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.07% 99.90% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::max_value 499972175752 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::total 3037 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::ON 139211949954 # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 2693651026546 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 278423951 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.cc_regfile_writes 53129749 # number of cc regfile writes
system.cpu.misc_regfile_reads 459440694 # number of misc regfile reads
system.cpu.misc_regfile_writes 1521708 # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 838747 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.925928 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 40056711 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 179125109 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 179125109 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 23264148 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 23264148 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 15542286 # number of WriteReq hits
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201621.381991 # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106895.663726 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106895.663726 # average overall mshr uncacheable latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 1886245 # number of replacements
system.cpu.icache.tags.tagsinuse 511.154077 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 64013417 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 67878198 # Number of tag accesses
system.cpu.icache.tags.data_accesses 67878198 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 64013417 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 64013417 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 64013417 # number of demand (read+write) hits
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125742.757243 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125742.757243 # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125742.757243 # average overall mshr uncacheable latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 96776 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65028.780058 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 5006507 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996582 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 44296182 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 44296182 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 58073 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12060 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 70133 # number of ReadReq hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 378 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 378 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq 128774 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2557731 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy 75872379 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 30172 # Transaction distribution
system.iobus.trans_dist::ReadResp 30172 # Transaction distribution
system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 36718000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 36413 # number of replacements
system.iocache.tags.tagsinuse 1.005739 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328023 # Number of tag accesses
system.iocache.tags.data_accesses 328023 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide 223 # number of ReadReq misses
system.iocache.ReadReq_misses::total 223 # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.demand_avg_mshr_miss_latency::total 75607.319560 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 75607.319560 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 75607.319560 # average overall mshr miss latency
+system.membus.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 34132 # Transaction distribution
system.membus.trans_dist::ReadResp 67490 # Transaction distribution
system.membus.trans_dist::WriteReq 27585 # Transaction distribution
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 1182123 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed
sim_ticks 2823728611500 # Number of ticks simulated
final_tick 2823728611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 406612 # Simulator instruction rate (inst/s)
-host_op_rate 493225 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 9343639540 # Simulator tick rate (ticks/s)
-host_mem_usage 632204 # Number of bytes of host memory used
-host_seconds 302.21 # Real time elapsed on the host
+host_inst_rate 403127 # Simulator instruction rate (inst/s)
+host_op_rate 488997 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 9263554618 # Simulator tick rate (ticks/s)
+host_mem_usage 632872 # Number of bytes of host memory used
+host_seconds 304.82 # Real time elapsed on the host
sim_insts 122881667 # Number of instructions simulated
sim_ops 149056790 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 538276 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 17119309500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks 4971 # Table walker walks requested
system.cpu0.dtb.walker.walksShort 4971 # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walkWaitTime::samples 4971 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.hits 21242670 # DTB hits
system.cpu0.dtb.misses 4971 # DTB misses
system.cpu0.dtb.accesses 21247641 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks 2431 # Table walker walks requested
system.cpu0.itb.walker.walksShort 2431 # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walkWaitTime::samples 2431 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.hits 56920666 # DTB hits
system.cpu0.itb.misses 2431 # DTB misses
system.cpu0.itb.accesses 56923097 # DTB accesses
+system.cpu0.numPwrStateTransitions 2544 # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples 1272 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean 2140717570.690252 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev 53412982832.831551 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows 1258 98.90% 98.90% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10 10 0.79% 99.69% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.08% 99.76% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.08% 99.84% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.08% 99.92% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::overflows 1 0.08% 100.00% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::max_value 1799910941001 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total 1272 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON 100735861582 # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 2722992749918 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 68768248 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 68312506 # Class of executed instruction
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 833701 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.996712 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 45908569 # Total number of references to valid blocks.
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 193086189 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 193086189 # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 11466814 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 3604015 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 4048059 # number of ReadReq hits
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 120633.235844 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 119318.443907 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115384.311080 # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 1971000 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.470268 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 93100004 # Total number of references to valid blocks.
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 97085384 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 97085384 # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 56179314 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 17648655 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 9977787 # number of ReadReq hits
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12829.404359 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12937.655406 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12853.021015 # average overall mshr miss latency
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks 2016 # Table walker walks requested
system.cpu1.dtb.walker.walksShort 2016 # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 564 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.hits 6609204 # DTB hits
system.cpu1.dtb.misses 2016 # DTB misses
system.cpu1.dtb.accesses 6611220 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks 1033 # Table walker walks requested
system.cpu1.itb.walker.walksShort 1033 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 205 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.hits 17860427 # DTB hits
system.cpu1.itb.misses 1033 # DTB misses
system.cpu1.itb.accesses 17861460 # DTB accesses
+system.cpu1.numPwrStateTransitions 700 # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples 350 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean 887126528.134286 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev 11718884453.100866 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows 345 98.57% 98.57% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10 3 0.86% 99.43% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 2 0.57% 100.00% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::max_value 156797355001 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total 350 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON 2513234326653 # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 310494284847 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 143797366 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.branchPred.indirectHits 638941 # Number of indirect target hits.
system.cpu2.branchPred.indirectMisses 32957 # Number of indirect misses.
system.cpu2.branchPredindirectMispredicted 21982 # Number of mispredicted indirect branches.
+system.cpu2.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu2.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.cpu2.dtb.walker.walks 11822 # Table walker walks requested
system.cpu2.dtb.walker.walksShort 11822 # Table walker walks initiated with short descriptors
system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 7337 # Level at which table walker walks with short descriptors terminate
system.cpu2.dtb.hits 7691653 # DTB hits
system.cpu2.dtb.misses 11822 # DTB misses
system.cpu2.dtb.accesses 7703475 # DTB accesses
+system.cpu2.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu2.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.cpu2.itb.walker.walks 1331 # Table walker walks requested
system.cpu2.itb.walker.walksShort 1331 # Table walker walks initiated with short descriptors
system.cpu2.itb.walker.walksShortTerminationLevel::Level1 253 # Level at which table walker walks with short descriptors terminate
system.cpu2.itb.hits 10452986 # DTB hits
system.cpu2.itb.misses 1331 # DTB misses
system.cpu2.itb.accesses 10454317 # DTB accesses
+system.cpu2.numPwrStateTransitions 1086 # Number of power state transitions
+system.cpu2.pwrStateClkGateDist::samples 543 # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::mean 5039016894.569060 # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::stdev 41056292942.981247 # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::underflows 498 91.71% 91.71% # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::1000-5e+10 38 7.00% 98.71% # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::5e+10-1e+11 1 0.18% 98.90% # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::1.5e+11-2e+11 1 0.18% 99.08% # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::2e+11-2.5e+11 1 0.18% 99.26% # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::2.5e+11-3e+11 1 0.18% 99.45% # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::4.5e+11-5e+11 2 0.37% 99.82% # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::5e+11-5.5e+11 1 0.18% 100.00% # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::max_value 500052575501 # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::total 543 # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateResidencyTicks::ON 87542437749 # Cumulative time (in ticks) in various power states
+system.cpu2.pwrStateResidencyTicks::CLK_GATED 2736186173751 # Cumulative time (in ticks) in various power states
system.cpu2.numCycles 141973763 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu3.branchPred.indirectHits 1952666 # Number of indirect target hits.
system.cpu3.branchPred.indirectMisses 61689 # Number of indirect misses.
system.cpu3.branchPredindirectMispredicted 18072 # Number of mispredicted indirect branches.
+system.cpu3.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu3.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.cpu3.dtb.walker.walks 34281 # Table walker walks requested
system.cpu3.dtb.walker.walksShort 34281 # Table walker walks initiated with short descriptors
system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 10962 # Level at which table walker walks with short descriptors terminate
system.cpu3.dtb.hits 13165199 # DTB hits
system.cpu3.dtb.misses 34281 # DTB misses
system.cpu3.dtb.accesses 13199480 # DTB accesses
+system.cpu3.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu3.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.cpu3.itb.walker.walks 4255 # Table walker walks requested
system.cpu3.itb.walker.walksShort 4255 # Table walker walks initiated with short descriptors
system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1348 # Level at which table walker walks with short descriptors terminate
system.cpu3.itb.hits 9881127 # DTB hits
system.cpu3.itb.misses 4255 # DTB misses
system.cpu3.itb.accesses 9885382 # DTB accesses
+system.cpu3.numPwrStateTransitions 1752 # Number of power state transitions
+system.cpu3.pwrStateClkGateDist::samples 876 # Distribution of time spent in the clock gated state
+system.cpu3.pwrStateClkGateDist::mean 24094343.119863 # Distribution of time spent in the clock gated state
+system.cpu3.pwrStateClkGateDist::stdev 642903034.341614 # Distribution of time spent in the clock gated state
+system.cpu3.pwrStateClkGateDist::underflows 861 98.29% 98.29% # Distribution of time spent in the clock gated state
+system.cpu3.pwrStateClkGateDist::1000-5e+10 15 1.71% 100.00% # Distribution of time spent in the clock gated state
+system.cpu3.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu3.pwrStateClkGateDist::max_value 18909601804 # Distribution of time spent in the clock gated state
+system.cpu3.pwrStateClkGateDist::total 876 # Distribution of time spent in the clock gated state
+system.cpu3.pwrStateResidencyTicks::ON 2802621966927 # Cumulative time (in ticks) in various power states
+system.cpu3.pwrStateResidencyTicks::CLK_GATED 21106644573 # Cumulative time (in ticks) in various power states
system.cpu3.numCycles 55785273 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu3.cc_regfile_writes 15932581 # number of cc regfile writes
system.cpu3.misc_regfile_reads 98044086 # number of misc regfile reads
system.cpu3.misc_regfile_writes 343753 # number of misc regfile writes
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 30152 # Transaction distribution
system.iobus.trans_dist::ReadResp 30152 # Transaction distribution
system.iobus.trans_dist::WriteReq 59010 # Transaction distribution
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 14254000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 36410 # number of replacements
system.iocache.tags.tagsinuse 1.002475 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 327996 # Number of tag accesses
system.iocache.tags.data_accesses 327996 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses
system.iocache.ReadReq_misses::total 220 # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.demand_avg_mshr_miss_latency::total 70054.816134 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 70054.816134 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 70054.816134 # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 100820 # number of replacements
system.l2c.tags.tagsinuse 65104.875407 # Cycle average of tags in use
system.l2c.tags.total_refs 5136845 # Total number of references to valid blocks.
system.l2c.tags.occ_task_id_percent::1024 0.993515 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 45392022 # Number of tag accesses
system.l2c.tags.data_accesses 45392022 # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.l2c.ReadReq_hits::cpu0.dtb.walker 4238 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 2128 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 1538 # number of ReadReq hits
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 40114 # Transaction distribution
system.membus.trans_dist::ReadResp 75609 # Transaction distribution
system.membus.trans_dist::WriteReq 27565 # Transaction distribution
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 721087 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 5640723 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 2834949 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 44718 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 306 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 306 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 110707 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2619793 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 27565 # Transaction distribution
sim_ticks 2804582834000 # Number of ticks simulated
final_tick 2804582834000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 167374 # Simulator instruction rate (inst/s)
-host_op_rate 203147 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4015325540 # Simulator tick rate (ticks/s)
-host_mem_usage 633236 # Number of bytes of host memory used
-host_seconds 698.47 # Real time elapsed on the host
+host_inst_rate 172391 # Simulator instruction rate (inst/s)
+host_op_rate 209235 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4135673798 # Simulator tick rate (ticks/s)
+host_mem_usage 633896 # Number of bytes of host memory used
+host_seconds 678.14 # Real time elapsed on the host
sim_insts 116905819 # Number of instructions simulated
sim_ops 141891765 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker 3968 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 685504 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 24067808750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst 768 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 768 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 768 # Number of instructions bytes read from this memory
system.realview.nvmem.bw_inst_read::total 274 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 274 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 274 # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cpu0.branchPred.indirectMisses 111638 # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted 31883 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks 59132 # Table walker walks requested
system.cpu0.dtb.walker.walksShort 59132 # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 17796 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.hits 24015751 # DTB hits
system.cpu0.dtb.misses 59132 # DTB misses
system.cpu0.dtb.accesses 24074883 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks 7852 # Table walker walks requested
system.cpu0.itb.walker.walksShort 7852 # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1 2338 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.hits 19905461 # DTB hits
system.cpu0.itb.misses 7852 # DTB misses
system.cpu0.itb.accesses 19913313 # DTB accesses
+system.cpu0.numPwrStateTransitions 3146 # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples 1573 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean 939647394.777495 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev 18797497095.969948 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows 1537 97.71% 97.71% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10 33 2.10% 99.81% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.06% 99.87% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 2 0.13% 100.00% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::max_value 499976908600 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total 1573 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON 1326517482015 # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 1478065351985 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 106457732 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.cc_regfile_writes 27226302 # number of cc regfile writes
system.cpu0.misc_regfile_reads 188101438 # number of misc regfile reads
system.cpu0.misc_regfile_writes 725062 # number of misc regfile writes
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 852281 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.984445 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 42339308 # Total number of references to valid blocks.
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 189174355 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 189174355 # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 12233622 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 12935174 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 25168796 # number of ReadReq hits
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 102368.142579 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 113511.329191 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 107377.271721 # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 1934770 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.556955 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 38706180 # Total number of references to valid blocks.
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 42724671 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 42724671 # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 18869611 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 19836569 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 38706180 # number of ReadReq hits
system.cpu1.branchPred.indirectHits 4505317 # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses 110432 # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted 32773 # Number of mispredicted indirect branches.
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks 58704 # Table walker walks requested
system.cpu1.dtb.walker.walksShort 58704 # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 18787 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.hits 25209314 # DTB hits
system.cpu1.dtb.misses 58704 # DTB misses
system.cpu1.dtb.accesses 25268018 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks 7547 # Table walker walks requested
system.cpu1.itb.walker.walksShort 7547 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2262 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.hits 20888873 # DTB hits
system.cpu1.itb.misses 7547 # DTB misses
system.cpu1.itb.accesses 20896420 # DTB accesses
+system.cpu1.numPwrStateTransitions 2930 # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples 1465 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean 831651178.963822 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev 15817593716.503048 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows 1430 97.61% 97.61% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10 32 2.18% 99.80% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.07% 99.86% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11 1 0.07% 99.93% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 1 0.07% 100.00% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::max_value 499953823748 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total 1465 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON 1586213856818 # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 1218368977182 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 109807766 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.cc_regfile_writes 29716175 # number of cc regfile writes
system.cpu1.misc_regfile_reads 196047925 # number of misc regfile reads
system.cpu1.misc_regfile_writes 794523 # number of misc regfile writes
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 30198 # Transaction distribution
system.iobus.trans_dist::ReadResp 30198 # Transaction distribution
system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 36770000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 36409 # number of replacements
system.iocache.tags.tagsinuse 0.981814 # Cycle average of tags in use
system.iocache.tags.total_refs 30 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328227 # Number of tag accesses
system.iocache.tags.data_accesses 328227 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
system.iocache.WriteLineReq_hits::realview.ide 29 # number of WriteLineReq hits
system.iocache.WriteLineReq_hits::total 29 # number of WriteLineReq hits
system.iocache.demand_hits::realview.ide 29 # number of demand (read+write) hits
system.iocache.demand_avg_mshr_miss_latency::total 68271.921222 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 68271.921222 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 68271.921222 # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 104354 # number of replacements
system.l2c.tags.tagsinuse 65128.327411 # Cycle average of tags in use
system.l2c.tags.total_refs 5134678 # Total number of references to valid blocks.
system.l2c.tags.occ_task_id_percent::1024 0.994522 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 45398834 # Number of tag accesses
system.l2c.tags.data_accesses 45398834 # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
system.l2c.ReadReq_hits::cpu0.dtb.walker 35730 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 6852 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 36375 # number of ReadReq hits
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 31794 # Transaction distribution
system.membus.trans_dist::ReadResp 68215 # Transaction distribution
system.membus.trans_dist::WriteReq 27584 # Transaction distribution
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 1321623 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 5615551 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 2827345 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 47668 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 189 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 189 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 149135 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2640787 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution
sim_ticks 47355903328000 # Number of ticks simulated
final_tick 47355903328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 234942 # Simulator instruction rate (inst/s)
-host_op_rate 276333 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 12593783431 # Simulator tick rate (ticks/s)
-host_mem_usage 765460 # Number of bytes of host memory used
-host_seconds 3760.26 # Real time elapsed on the host
+host_inst_rate 277163 # Simulator instruction rate (inst/s)
+host_op_rate 325991 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 14856975599 # Simulator tick rate (ticks/s)
+host_mem_usage 813232 # Number of bytes of host memory used
+host_seconds 3187.45 # Real time elapsed on the host
sim_insts 883443630 # Number of instructions simulated
sim_ops 1039082168 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker 131584 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 123776 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 7567040 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 225268560933 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory
system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cpu0.branchPred.indirectMisses 1176677 # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted 420775 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks 298304 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 298304 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10716 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.hits 176008306 # DTB hits
system.cpu0.dtb.misses 298304 # DTB misses
system.cpu0.dtb.accesses 176306610 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks 65048 # Table walker walks requested
system.cpu0.itb.walker.walksLong 65048 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2 515 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.hits 259203584 # DTB hits
system.cpu0.itb.misses 65048 # DTB misses
system.cpu0.itb.accesses 259268632 # DTB accesses
+system.cpu0.numPwrStateTransitions 26040 # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples 13020 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean 3597852748.702535 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev 96451622625.318069 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows 3172 24.36% 24.36% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10 9818 75.41% 99.77% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5e+10-1e+11 12 0.09% 99.86% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::overflows 13 0.10% 100.00% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::max_value 7033291450000 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total 13020 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON 511860539893 # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 46844042788107 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 1023758481 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.kern.inst.quiesce 13020 # number of quiesce instructions executed
system.cpu0.tickCycles 768761843 # Number of cycles that the object actually ticked
system.cpu0.idleCycles 254996638 # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 6026209 # number of replacements
system.cpu0.dcache.tags.tagsinuse 478.505782 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 166971566 # Total number of references to valid blocks.
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 355154483 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 355154483 # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 85976696 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 85976696 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 76051356 # number of WriteReq hits
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193581.572141 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97524.480748 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 97524.480748 # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 9817579 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.932451 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 249208397 # Total number of references to valid blocks.
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 527871096 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 527871096 # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 249208397 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 249208397 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 249208397 # number of demand (read+write) hits
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92491.166179 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92491.166179 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92491.166179 # average overall mshr uncacheable latency
+system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued 8242304 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 8243665 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 1198 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 1073071 # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements 2829183 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 16163.343057 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 24764914 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.900146 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 533961635 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 533961635 # Number of data accesses
+system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 561309 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 167224 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 728533 # number of ReadReq hits
system.cpu0.toL2Bus.snoop_filter.tot_snoops 2229520 # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2229086 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 434 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq 913111 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 14927613 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
system.cpu1.branchPred.indirectHits 2135700 # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses 1155063 # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted 419705 # Number of mispredicted indirect branches.
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks 255224 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 255224 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8861 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.hits 148139102 # DTB hits
system.cpu1.dtb.misses 255224 # DTB misses
system.cpu1.dtb.accesses 148394326 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks 62177 # Table walker walks requested
system.cpu1.itb.walker.walksLong 62177 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 630 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.hits 219337574 # DTB hits
system.cpu1.itb.misses 62177 # DTB misses
system.cpu1.itb.accesses 219399751 # DTB accesses
+system.cpu1.numPwrStateTransitions 10996 # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples 5498 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean 8537078490.682248 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev 139542991677.263855 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows 3923 71.35% 71.35% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10 1550 28.19% 99.55% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.02% 99.56% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 5 0.09% 99.65% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 2 0.04% 99.69% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.71% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::6e+11-6.5e+11 1 0.02% 99.73% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.02% 99.75% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::overflows 14 0.25% 100.00% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::max_value 7470355729396 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total 5498 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON 419045786229 # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 46936857541771 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 838096745 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.kern.inst.quiesce 5498 # number of quiesce instructions executed
system.cpu1.tickCycles 657140254 # Number of cycles that the object actually ticked
system.cpu1.idleCycles 180956491 # Total number of cycles that the object has spent stopped
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements 4810857 # number of replacements
system.cpu1.dcache.tags.tagsinuse 458.623346 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 140763490 # Total number of references to valid blocks.
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 298669128 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 298669128 # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data 72030058 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 72030058 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 64877267 # number of WriteReq hits
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 120622.748883 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 58873.672738 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 58873.672738 # average overall mshr uncacheable latency
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements 8744967 # number of replacements
system.cpu1.icache.tags.tagsinuse 507.224680 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 210419103 # Total number of references to valid blocks.
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 447074643 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 447074643 # Number of data accesses
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst 210419103 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 210419103 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 210419103 # number of demand (read+write) hits
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90860.215054 # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90860.215054 # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90860.215054 # average overall mshr uncacheable latency
+system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued 6641051 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 6641093 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 36 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 796339 # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements 2218428 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 13419.558556 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 21617433 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.864502 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 457671450 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 457671450 # Number of data accesses
+system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 494400 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 160613 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 655013 # number of ReadReq hits
system.cpu1.toL2Bus.snoop_filter.tot_snoops 2035614 # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2035313 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 301 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq 755700 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 13030335 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 7280 # Transaction distribution
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy 563017795 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 40337 # Transaction distribution
system.iobus.trans_dist::ReadResp 40337 # Transaction distribution
system.iobus.trans_dist::WriteReq 136616 # Transaction distribution
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 115611 # number of replacements
system.iocache.tags.tagsinuse 11.284790 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1040883 # Number of tag accesses
system.iocache.tags.data_accesses 1040883 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8886 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8923 # number of ReadReq misses
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 75572.715701 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 75577.420176 # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 1371243 # number of replacements
system.l2c.tags.tagsinuse 63411.869664 # Cycle average of tags in use
system.l2c.tags.total_refs 6460055 # Total number of references to valid blocks.
system.l2c.tags.occ_task_id_percent::1024 0.765335 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 79235647 # Number of tag accesses
system.l2c.tags.data_accesses 79235647 # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 2747527 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 2747527 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 1 # number of WritebackClean hits
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 91033 # Transaction distribution
system.membus.trans_dist::ReadResp 892432 # Transaction distribution
system.membus.trans_dist::WriteReq 38505 # Transaction distribution
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 45499333 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 12326432 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 6670511 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 2086069 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 130580 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 118652 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 11928 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 91035 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 4782322 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 38505 # Transaction distribution
sim_ticks 51660652947000 # Number of ticks simulated
final_tick 51660652947000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 260799 # Simulator instruction rate (inst/s)
-host_op_rate 306450 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 14496494193 # Simulator tick rate (ticks/s)
-host_mem_usage 677256 # Number of bytes of host memory used
-host_seconds 3563.67 # Real time elapsed on the host
+host_inst_rate 288085 # Simulator instruction rate (inst/s)
+host_op_rate 338513 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 16013200726 # Simulator tick rate (ticks/s)
+host_mem_usage 724944 # Number of bytes of host memory used
+host_seconds 3226.13 # Real time elapsed on the host
sim_insts 929398934 # Number of instructions simulated
sim_ops 1092086880 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.dtb.walker 378560 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 313536 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 10229888 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 292938700991 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory
system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cpu.branchPred.indirectMisses 2055396 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 841768 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 561578 # Table walker walks requested
system.cpu.dtb.walker.walksLong 561578 # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20867 # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.hits 338792432 # DTB hits
system.cpu.dtb.misses 561578 # DTB misses
system.cpu.dtb.accesses 339354010 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 133823 # Table walker walks requested
system.cpu.itb.walker.walksLong 133823 # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walksLongTerminationLevel::Level2 1057 # Level at which table walker walks with long descriptors terminate
system.cpu.itb.hits 442793055 # DTB hits
system.cpu.itb.misses 133823 # DTB misses
system.cpu.itb.accesses 442926878 # DTB accesses
+system.cpu.numPwrStateTransitions 33032 # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples 16516 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean 3050356912.427888 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev 59773934276.156128 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::underflows 7219 43.71% 43.71% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10 9262 56.08% 99.79% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.83% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::max_value 1988777743356 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::total 16516 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::ON 1280958181341 # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 50379694765659 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 2561963341 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.kern.inst.quiesce 16516 # number of quiesce instructions executed
system.cpu.tickCycles 1757425284 # Number of cycles that the object actually ticked
system.cpu.idleCycles 804538057 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 10826762 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.930071 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 322795140 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1356106386 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1356106386 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 165131668 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 165131668 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 148654336 # number of WriteReq hits
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183922.263109 # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91948.852425 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91948.852425 # average overall mshr uncacheable latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 24339101 # number of replacements
system.cpu.icache.tags.tagsinuse 511.885333 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 418129059 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 466808304 # Number of tag accesses
system.cpu.icache.tags.data_accesses 466808304 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 418129059 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 418129059 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 418129059 # number of demand (read+write) hits
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 128980.940182 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 128980.940182 # average overall mshr uncacheable latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 1529682 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65330.827855 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 66339690 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.958176 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 577322417 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 577322417 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 919591 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 277608 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1197199 # number of ReadReq hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 2287 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2287 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq 1731601 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 33371848 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 33706 # Transaction distribution
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy 1245546930 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 40324 # Transaction distribution
system.iobus.trans_dist::ReadResp 40324 # Transaction distribution
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 115484 # number of replacements
system.iocache.tags.tagsinuse 10.441254 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1039884 # Number of tag accesses
system.iocache.tags.data_accesses 1039884 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8839 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8876 # number of ReadReq misses
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 80307.212471 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 80309.018824 # average overall mshr miss latency
+system.membus.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 86006 # Transaction distribution
system.membus.trans_dist::ReadResp 535040 # Transaction distribution
system.membus.trans_dist::WriteReq 33706 # Transaction distribution
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 44857615 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states
---------- End Simulation Statistics ----------
sim_ticks 51327139864000 # Number of ticks simulated
final_tick 51327139864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 134762 # Simulator instruction rate (inst/s)
-host_op_rate 158348 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 8155197699 # Simulator tick rate (ticks/s)
-host_mem_usage 681612 # Number of bytes of host memory used
-host_seconds 6293.79 # Real time elapsed on the host
+host_inst_rate 139208 # Simulator instruction rate (inst/s)
+host_op_rate 163572 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 8424230073 # Simulator tick rate (ticks/s)
+host_mem_usage 729304 # Number of bytes of host memory used
+host_seconds 6092.80 # Real time elapsed on the host
sim_insts 848164321 # Number of instructions simulated
sim_ops 996610207 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.dtb.walker 227712 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 216512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 5661728 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 183585648673 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory
system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cpu.branchPred.indirectMisses 1985028 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 766036 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.cpu.checker.dtb.walker.walks 197728 # Table walker walks requested
system.cpu.checker.dtb.walker.walksLong 197728 # Table walker walks initiated with long descriptors
system.cpu.checker.dtb.walker.walkWaitTime::samples 197728 # Table walker wait (enqueue to first request) latency
system.cpu.checker.dtb.hits 304308457 # DTB hits
system.cpu.checker.dtb.misses 197728 # DTB misses
system.cpu.checker.dtb.accesses 304506185 # DTB accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.cpu.checker.itb.walker.walks 119805 # Table walker walks requested
system.cpu.checker.itb.walker.walksLong 119805 # Table walker walks initiated with long descriptors
system.cpu.checker.itb.walker.walkWaitTime::samples 119805 # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.hits 848570685 # DTB hits
system.cpu.checker.itb.misses 119805 # DTB misses
system.cpu.checker.itb.accesses 848690490 # DTB accesses
+system.cpu.checker.pwrStateResidencyTicks::ON 51327139864000 # Cumulative time (in ticks) in various power states
system.cpu.checker.numCycles 997179501 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 947007 # Table walker walks requested
system.cpu.dtb.walker.walksLong 947007 # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15816 # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.hits 316731789 # DTB hits
system.cpu.dtb.misses 947007 # DTB misses
system.cpu.dtb.accesses 317678796 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 162102 # Table walker walks requested
system.cpu.itb.walker.walksLong 162102 # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walksLongTerminationLevel::Level2 1483 # Level at which table walker walks with long descriptors terminate
system.cpu.itb.hits 357007788 # DTB hits
system.cpu.itb.misses 162102 # DTB misses
system.cpu.itb.accesses 357169890 # DTB accesses
+system.cpu.numPwrStateTransitions 32228 # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples 16114 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean 3134638980.534008 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev 60494100077.253059 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::underflows 6793 42.16% 42.16% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10 9285 57.62% 99.78% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.83% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::max_value 1988780762168 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::total 16114 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::ON 815567331675 # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 50511572532325 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 1631144067 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.cc_regfile_writes 225673032 # number of cc regfile writes
system.cpu.misc_regfile_reads 2558050117 # number of misc regfile reads
system.cpu.misc_regfile_writes 26930699 # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 9706309 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.972800 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 283158526 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1236907465 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1236907465 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 147182281 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 147182281 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 128244124 # number of WriteReq hits
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183859.552230 # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91905.215662 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91905.215662 # average overall mshr uncacheable latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 15141033 # number of replacements
system.cpu.icache.tags.tagsinuse 511.928986 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 340718799 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 371754919 # Number of tag accesses
system.cpu.icache.tags.data_accesses 371754919 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 340718799 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 340718799 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 340718799 # number of demand (read+write) hits
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.968724 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.968724 # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.968724 # average overall mshr uncacheable latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 1146896 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65342.232394 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 46291207 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.946854 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 410454205 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 410454205 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 776137 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 292808 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1068945 # number of ReadReq hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 2189 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2189 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq 1620273 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 23279411 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy 1139764793 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 40299 # Transaction distribution
system.iobus.trans_dist::ReadResp 40299 # Transaction distribution
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 115459 # number of replacements
system.iocache.tags.tagsinuse 10.423130 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1039659 # Number of tag accesses
system.iocache.tags.data_accesses 1039659 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8814 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8851 # number of ReadReq misses
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85575 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 80668.859410 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 80670.558242 # average overall mshr miss latency
+system.membus.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 54972 # Transaction distribution
system.membus.trans_dist::ReadResp 410008 # Transaction distribution
system.membus.trans_dist::WriteReq 33696 # Transaction distribution
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 44815639 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 16114 # number of quiesce instructions executed
sim_ticks 47384315163000 # Number of ticks simulated
final_tick 47384315163000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 172390 # Simulator instruction rate (inst/s)
-host_op_rate 202727 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 9043218476 # Simulator tick rate (ticks/s)
-host_mem_usage 765852 # Number of bytes of host memory used
-host_seconds 5239.76 # Real time elapsed on the host
+host_inst_rate 162093 # Simulator instruction rate (inst/s)
+host_op_rate 190619 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 8503081814 # Simulator tick rate (ticks/s)
+host_mem_usage 814268 # Number of bytes of host memory used
+host_seconds 5572.60 # Real time elapsed on the host
sim_insts 903281747 # Number of instructions simulated
sim_ops 1062243320 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker 88320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 58304 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 4233376 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 193128558366 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory
system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cpu0.branchPred.indirectMisses 1641263 # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted 409141 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks 530338 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 530338 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10426 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.hits 182736783 # DTB hits
system.cpu0.dtb.misses 530338 # DTB misses
system.cpu0.dtb.accesses 183267121 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks 81834 # Table walker walks requested
system.cpu0.itb.walker.walksLong 81834 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1030 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.hits 216521473 # DTB hits
system.cpu0.itb.misses 81834 # DTB misses
system.cpu0.itb.accesses 216603307 # DTB accesses
+system.cpu0.numPwrStateTransitions 26480 # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples 13240 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean 3550703383.143278 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev 88629328460.442917 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows 3078 23.25% 23.25% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10 10135 76.55% 99.80% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5e+10-1e+11 4 0.03% 99.83% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::8e+11-8.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::overflows 14 0.11% 100.00% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::max_value 7390881192332 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total 13240 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON 373002370183 # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 47011312792817 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 746014900 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.cc_regfile_writes 128742208 # number of cc regfile writes
system.cpu0.misc_regfile_reads 1288788249 # number of misc regfile reads
system.cpu0.misc_regfile_writes 14832406 # number of misc regfile writes
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 5793916 # number of replacements
system.cpu0.dcache.tags.tagsinuse 505.305765 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 157106373 # Total number of references to valid blocks.
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 349540400 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 349540400 # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 81616032 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 81616032 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 70522769 # number of WriteReq hits
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190877.363421 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95697.586239 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95697.586239 # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 6136519 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.962391 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 209807209 # Total number of references to valid blocks.
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 438728804 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 438728804 # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 209807209 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 209807209 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 209807209 # number of demand (read+write) hits
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88558.563753 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88558.563753 # average overall mshr uncacheable latency
+system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued 7743703 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 7754051 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 9277 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 1008365 # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements 2565485 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 15956.741738 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 17408441 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.889221 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 408243228 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 408243228 # Number of data accesses
+system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 539952 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 183800 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 723752 # number of ReadReq hits
system.cpu0.toL2Bus.snoop_filter.tot_snoops 1997962 # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1997498 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 464 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq 885324 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 11040535 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 32352 # Transaction distribution
system.cpu1.branchPred.indirectHits 2495247 # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses 1540837 # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted 386993 # Number of mispredicted indirect branches.
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks 579824 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 579824 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 12232 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.hits 169832161 # DTB hits
system.cpu1.dtb.misses 579824 # DTB misses
system.cpu1.dtb.accesses 170411985 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks 86146 # Table walker walks requested
system.cpu1.itb.walker.walksLong 86146 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 983 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.hits 200179962 # DTB hits
system.cpu1.itb.misses 86146 # DTB misses
system.cpu1.itb.accesses 200266108 # DTB accesses
+system.cpu1.numPwrStateTransitions 11252 # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples 5626 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean 8361647359.894774 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev 196584250353.907135 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows 4008 71.24% 71.24% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10 1597 28.39% 99.63% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+10-1e+11 6 0.11% 99.73% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.75% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.77% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11 1 0.02% 99.79% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.80% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.82% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::overflows 10 0.18% 100.00% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::max_value 11813562713000 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total 5626 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON 341687116232 # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 47042628046768 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 683375860 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.cc_regfile_writes 115917819 # number of cc regfile writes
system.cpu1.misc_regfile_reads 1185795918 # number of misc regfile reads
system.cpu1.misc_regfile_writes 15045931 # number of misc regfile writes
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements 5420466 # number of replacements
system.cpu1.dcache.tags.tagsinuse 437.277482 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 144971712 # Total number of references to valid blocks.
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 323922794 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 323922794 # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data 76466425 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 76466425 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 64110613 # number of WriteReq hits
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 122572.491010 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 60962.401431 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 60962.401431 # average overall mshr uncacheable latency
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements 5742782 # number of replacements
system.cpu1.icache.tags.tagsinuse 501.536552 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 193871102 # Total number of references to valid blocks.
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 405638078 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 405638078 # Number of data accesses
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst 193871102 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 193871102 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 193871102 # number of demand (read+write) hits
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 101335.791045 # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 101335.791045 # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 101335.791045 # average overall mshr uncacheable latency
+system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued 7416585 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 7422175 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 5069 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 930081 # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements 2216875 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 13443.573819 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 16807540 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.886658 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 383680582 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 383680582 # Number of data accesses
+system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 591753 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 193382 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 785135 # number of ReadReq hits
system.cpu1.toL2Bus.snoop_filter.tot_snoops 1942556 # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1942287 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 269 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq 900600 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 10671947 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy 672656647 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 40341 # Transaction distribution
system.iobus.trans_dist::ReadResp 40341 # Transaction distribution
system.iobus.trans_dist::WriteReq 136646 # Transaction distribution
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 115592 # number of replacements
system.iocache.tags.tagsinuse 11.302694 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1040856 # Number of tag accesses
system.iocache.tags.data_accesses 1040856 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8883 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8920 # number of ReadReq misses
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 90375 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 76420.229883 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 76425.056394 # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 1423185 # number of replacements
system.l2c.tags.tagsinuse 63448.336905 # Cycle average of tags in use
system.l2c.tags.total_refs 6060449 # Total number of references to valid blocks.
system.l2c.tags.occ_task_id_percent::1024 0.739914 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 76659871 # Number of tag accesses
system.l2c.tags.data_accesses 76659871 # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 2799563 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 2799563 # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data 175772 # number of UpgradeReq hits
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 60003 # Transaction distribution
system.membus.trans_dist::ReadResp 904829 # Transaction distribution
system.membus.trans_dist::WriteReq 38534 # Transaction distribution
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 45514707 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 11842018 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 6441759 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 1913591 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 133722 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 121814 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 11908 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 60005 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 4492996 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 38534 # Transaction distribution
sim_ticks 51327139864000 # Number of ticks simulated
final_tick 51327139864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 181298 # Simulator instruction rate (inst/s)
-host_op_rate 213029 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 10971364807 # Simulator tick rate (ticks/s)
-host_mem_usage 680328 # Number of bytes of host memory used
-host_seconds 4678.28 # Real time elapsed on the host
+host_inst_rate 184861 # Simulator instruction rate (inst/s)
+host_op_rate 217215 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 11186950873 # Simulator tick rate (ticks/s)
+host_mem_usage 729056 # Number of bytes of host memory used
+host_seconds 4588.13 # Real time elapsed on the host
sim_insts 848164321 # Number of instructions simulated
sim_ops 996610207 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.dtb.walker 227712 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 216512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 5661728 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 183585648673 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory
system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cpu.branchPred.indirectMisses 1985028 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 766036 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 947007 # Table walker walks requested
system.cpu.dtb.walker.walksLong 947007 # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15816 # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.hits 316731789 # DTB hits
system.cpu.dtb.misses 947007 # DTB misses
system.cpu.dtb.accesses 317678796 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 162102 # Table walker walks requested
system.cpu.itb.walker.walksLong 162102 # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walksLongTerminationLevel::Level2 1483 # Level at which table walker walks with long descriptors terminate
system.cpu.itb.hits 357007788 # DTB hits
system.cpu.itb.misses 162102 # DTB misses
system.cpu.itb.accesses 357169890 # DTB accesses
+system.cpu.numPwrStateTransitions 32228 # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples 16114 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean 3134638980.534008 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev 60494100077.253059 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::underflows 6793 42.16% 42.16% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10 9285 57.62% 99.78% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.83% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::max_value 1988780762168 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::total 16114 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::ON 815567331675 # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 50511572532325 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 1631144067 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.cc_regfile_writes 225673032 # number of cc regfile writes
system.cpu.misc_regfile_reads 2558050117 # number of misc regfile reads
system.cpu.misc_regfile_writes 26930699 # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 9706309 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.972800 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 283158526 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1236907465 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1236907465 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 147182281 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 147182281 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 128244124 # number of WriteReq hits
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183859.552230 # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91905.215662 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91905.215662 # average overall mshr uncacheable latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 15141033 # number of replacements
system.cpu.icache.tags.tagsinuse 511.928986 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 340718799 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 371754919 # Number of tag accesses
system.cpu.icache.tags.data_accesses 371754919 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 340718799 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 340718799 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 340718799 # number of demand (read+write) hits
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.968724 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.968724 # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.968724 # average overall mshr uncacheable latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 1146896 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65342.232394 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 46291207 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.946854 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 410454205 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 410454205 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 776137 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 292808 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1068945 # number of ReadReq hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 2189 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2189 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq 1620273 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 23279411 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy 1139764793 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 40299 # Transaction distribution
system.iobus.trans_dist::ReadResp 40299 # Transaction distribution
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 115459 # number of replacements
system.iocache.tags.tagsinuse 10.423130 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1039659 # Number of tag accesses
system.iocache.tags.data_accesses 1039659 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8814 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8851 # number of ReadReq misses
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85575 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 80668.859410 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 80670.558242 # average overall mshr miss latency
+system.membus.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 54972 # Transaction distribution
system.membus.trans_dist::ReadResp 410008 # Transaction distribution
system.membus.trans_dist::WriteReq 33696 # Transaction distribution
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 44815639 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 16114 # number of quiesce instructions executed
sim_ticks 51111167216500 # Number of ticks simulated
final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1222140 # Simulator instruction rate (inst/s)
-host_op_rate 1436279 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 63596815146 # Simulator tick rate (ticks/s)
-host_mem_usage 673192 # Number of bytes of host memory used
-host_seconds 803.68 # Real time elapsed on the host
+host_inst_rate 1565564 # Simulator instruction rate (inst/s)
+host_op_rate 1839875 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 81467630636 # Simulator tick rate (ticks/s)
+host_mem_usage 722252 # Number of bytes of host memory used
+host_seconds 627.38 # Real time elapsed on the host
sim_insts 982203438 # Number of instructions simulated
sim_ops 1154301153 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.dtb.walker 414464 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 373568 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 5483956 # Number of bytes read from this memory
system.physmem.bw_total::cpu.data 1466073 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 8546 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3617977 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 266586 # Table walker walks requested
system.cpu.dtb.walker.walksLong 266586 # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walkWaitTime::samples 266586 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.hits 351319901 # DTB hits
system.cpu.dtb.misses 266586 # DTB misses
system.cpu.dtb.accesses 351586487 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 126834 # Table walker walks requested
system.cpu.itb.walker.walksLong 126834 # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walkWaitTime::samples 126834 # Table walker wait (enqueue to first request) latency
system.cpu.itb.hits 982680284 # DTB hits
system.cpu.itb.misses 126834 # DTB misses
system.cpu.itb.accesses 982807118 # DTB accesses
+system.cpu.numPwrStateTransitions 33550 # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples 16775 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean 3012440740.999106 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev 59942517869.536507 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::underflows 7454 44.44% 44.44% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10 9286 55.36% 99.79% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::5e+10-1e+11 4 0.02% 99.82% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 3 0.02% 99.87% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::3.5e+11-4e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::max_value 1988782948204 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::total 16775 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::ON 577473786240 # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 50533693430260 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 102222351209 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1154935820 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 11606642 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 339855471 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1417457719 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1417457719 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 171110770 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 171110770 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 159073533 # number of WriteReq hits
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 8917390 # number of writebacks
system.cpu.dcache.writebacks::total 8917390 # number of writebacks
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 14265253 # number of replacements
system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 968529210 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 997060750 # Number of tag accesses
system.cpu.icache.tags.data_accesses 997060750 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 968529210 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 968529210 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 968529210 # number of demand (read+write) hits
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 14265253 # number of writebacks
system.cpu.icache.writebacks::total 14265253 # number of writebacks
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 1725806 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65319.576270 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 46897183 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.956711 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 425634048 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 425634048 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 509091 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255953 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 765044 # number of ReadReq hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 2693 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2693 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq 1229988 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 23339142 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 55016338 # Request fanout histogram
+system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 40242 # Transaction distribution
system.iobus.trans_dist::ReadResp 40242 # Transaction distribution
system.iobus.trans_dist::WriteReq 136515 # Transaction distribution
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 7491944 # Cumulative packet size per connected master and slave (bytes)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 115459 # number of replacements
system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1039650 # Number of tag accesses
system.iocache.tags.data_accesses 1039650 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.writebacks::writebacks 106631 # number of writebacks
system.iocache.writebacks::total 106631 # number of writebacks
+system.membus.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 76679 # Transaction distribution
system.membus.trans_dist::ReadResp 524946 # Transaction distribution
system.membus.trans_dist::WriteReq 33606 # Transaction distribution
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 3924997 # Request fanout histogram
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
---------- End Simulation Statistics ----------
sim_ticks 47216814802000 # Number of ticks simulated
final_tick 47216814802000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1112312 # Simulator instruction rate (inst/s)
-host_op_rate 1308465 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 53753255119 # Simulator tick rate (ticks/s)
-host_mem_usage 687512 # Number of bytes of host memory used
-host_seconds 878.40 # Real time elapsed on the host
+host_inst_rate 1563637 # Simulator instruction rate (inst/s)
+host_op_rate 1839381 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 75563871924 # Simulator tick rate (ticks/s)
+host_mem_usage 737620 # Number of bytes of host memory used
+host_seconds 624.86 # Real time elapsed on the host
sim_insts 977053655 # Number of instructions simulated
sim_ops 1149354696 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker 150336 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 124416 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 3895860 # Number of bytes read from this memory
system.physmem.bw_total::cpu1.data 820165 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 8847 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3870913 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks 124420 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 124420 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walkWaitTime::samples 124420 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.hits 176801329 # DTB hits
system.cpu0.dtb.misses 124420 # DTB misses
system.cpu0.dtb.accesses 176925749 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks 60852 # Table walker walks requested
system.cpu0.itb.walker.walksLong 60852 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walkWaitTime::samples 60852 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.hits 493637993 # DTB hits
system.cpu0.itb.misses 60852 # DTB misses
system.cpu0.itb.accesses 493698845 # DTB accesses
+system.cpu0.numPwrStateTransitions 26456 # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples 13226 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean 3548051502.510434 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev 89670925641.729767 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows 3168 23.95% 23.95% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10 10031 75.84% 99.80% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.82% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 2 0.02% 99.83% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 2 0.02% 99.89% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::overflows 14 0.11% 100.00% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::max_value 7470356053852 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total 13226 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON 290285629797 # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 46926529172203 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 94433642835 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 580566843 # Class of executed instruction
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 6218107 # number of replacements
system.cpu0.dcache.tags.tagsinuse 503.352532 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 170512705 # Total number of references to valid blocks.
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 359988587 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 359988587 # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 85387960 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 85387960 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 80242803 # number of WriteReq hits
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks 6218107 # number of writebacks
system.cpu0.dcache.writebacks::total 6218107 # number of writebacks
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 5488502 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 488204417 # Total number of references to valid blocks.
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 992875891 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 992875891 # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 488204417 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 488204417 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 488204417 # number of demand (read+write) hits
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks 5488502 # number of writebacks
system.cpu0.icache.writebacks::total 5488502 # number of writebacks
+system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements 2643580 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 16147.870386 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 15444293 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.973450 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 394033422 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 394033422 # Number of data accesses
+system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 293436 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 155846 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 449282 # number of ReadReq hits
system.cpu0.toL2Bus.snoop_filter.tot_snoops 1770017 # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1769681 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 336 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq 619965 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 10275461 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 33238 # Transaction distribution
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total 30354370 # Request fanout histogram
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks 144355 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 144355 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walkWaitTime::samples 144355 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.hits 173467628 # DTB hits
system.cpu1.dtb.misses 144355 # DTB misses
system.cpu1.dtb.accesses 173611983 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks 61638 # Table walker walks requested
system.cpu1.itb.walker.walksLong 61638 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walkWaitTime::samples 61638 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.hits 483902380 # DTB hits
system.cpu1.itb.misses 61638 # DTB misses
system.cpu1.itb.accesses 483964018 # DTB accesses
+system.cpu1.numPwrStateTransitions 12326 # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples 6163 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean 7615138435.844394 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev 188025849317.388916 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows 4489 72.84% 72.84% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10 1652 26.81% 99.64% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+10-1e+11 6 0.10% 99.74% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.03% 99.77% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.03% 99.81% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.82% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::3.5e+11-4e+11 1 0.02% 99.84% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::overflows 10 0.16% 100.00% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::max_value 11813542449500 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total 6163 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON 284716621891 # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 46932098180109 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 94433635768 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 569428445 # Class of executed instruction
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements 6003966 # number of replacements
system.cpu1.dcache.tags.tagsinuse 423.687505 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 167475451 # Total number of references to valid blocks.
system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 353236361 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 353236361 # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data 84832048 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 84832048 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 77963660 # number of WriteReq hits
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks 6003966 # number of writebacks
system.cpu1.dcache.writebacks::total 6003966 # number of writebacks
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements 4799154 # number of replacements
system.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 479157890 # Total number of references to valid blocks.
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 972714778 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 972714778 # Number of data accesses
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst 479157890 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 479157890 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 479157890 # number of demand (read+write) hits
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks 4799154 # number of writebacks
system.cpu1.icache.writebacks::total 4799154 # number of writebacks
+system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements 2283161 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 13345.955021 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 14389871 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.973938 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 365657601 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 365657601 # Number of data accesses
+system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 347777 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155733 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 503510 # number of ReadReq hits
system.cpu1.toL2Bus.snoop_filter.tot_snoops 1756231 # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1756065 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 166 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq 608590 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 9740544 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 5562 # Transaction distribution
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total 28144557 # Request fanout histogram
+system.iobus.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 40301 # Transaction distribution
system.iobus.trans_dist::ReadResp 40301 # Transaction distribution
system.iobus.trans_dist::WriteReq 136636 # Transaction distribution
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 7496657 # Cumulative packet size per connected master and slave (bytes)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 115590 # number of replacements
system.iocache.tags.tagsinuse 11.289214 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1040838 # Number of tag accesses
system.iocache.tags.data_accesses 1040838 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8881 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8918 # number of ReadReq misses
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.writebacks::writebacks 106694 # number of writebacks
system.iocache.writebacks::total 106694 # number of writebacks
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 1772279 # number of replacements
system.l2c.tags.tagsinuse 63191.056766 # Cycle average of tags in use
system.l2c.tags.total_refs 4630026 # Total number of references to valid blocks.
system.l2c.tags.occ_task_id_percent::1024 0.906433 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 73419992 # Number of tag accesses
system.l2c.tags.data_accesses 73419992 # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 2765418 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 2765418 # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data 17779 # number of UpgradeReq hits
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 82119 # Transaction distribution
system.membus.trans_dist::ReadResp 569484 # Transaction distribution
system.membus.trans_dist::WriteReq 38800 # Transaction distribution
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 4612344 # Request fanout histogram
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 11113814 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 5721773 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 1636305 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 133991 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 120343 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 13648 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 82121 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 3542094 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 38800 # Transaction distribution
sim_ticks 51111167216500 # Number of ticks simulated
final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1142928 # Simulator instruction rate (inst/s)
-host_op_rate 1343188 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 59474849541 # Simulator tick rate (ticks/s)
-host_mem_usage 670860 # Number of bytes of host memory used
-host_seconds 859.37 # Real time elapsed on the host
+host_inst_rate 1675396 # Simulator instruction rate (inst/s)
+host_op_rate 1968952 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 87182982694 # Simulator tick rate (ticks/s)
+host_mem_usage 718784 # Number of bytes of host memory used
+host_seconds 586.25 # Real time elapsed on the host
sim_insts 982203438 # Number of instructions simulated
sim_ops 1154301153 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.dtb.walker 414464 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 373568 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 5483956 # Number of bytes read from this memory
system.physmem.bw_total::cpu.data 1466073 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 8546 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3617977 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 266586 # Table walker walks requested
system.cpu.dtb.walker.walksLong 266586 # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walkWaitTime::samples 266586 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.hits 351319901 # DTB hits
system.cpu.dtb.misses 266586 # DTB misses
system.cpu.dtb.accesses 351586487 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 126834 # Table walker walks requested
system.cpu.itb.walker.walksLong 126834 # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walkWaitTime::samples 126834 # Table walker wait (enqueue to first request) latency
system.cpu.itb.hits 982680284 # DTB hits
system.cpu.itb.misses 126834 # DTB misses
system.cpu.itb.accesses 982807118 # DTB accesses
+system.cpu.numPwrStateTransitions 33550 # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples 16775 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean 3012440740.999106 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev 59942517869.536507 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::underflows 7454 44.44% 44.44% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10 9286 55.36% 99.79% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::5e+10-1e+11 4 0.02% 99.82% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 3 0.02% 99.87% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::3.5e+11-4e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::max_value 1988782948204 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::total 16775 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::ON 577473786240 # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 50533693430260 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 102222351209 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1154935820 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 11606642 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 339855471 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1417457719 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1417457719 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 171110770 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 171110770 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 159073533 # number of WriteReq hits
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 8917390 # number of writebacks
system.cpu.dcache.writebacks::total 8917390 # number of writebacks
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 14265253 # number of replacements
system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 968529210 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 997060750 # Number of tag accesses
system.cpu.icache.tags.data_accesses 997060750 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 968529210 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 968529210 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 968529210 # number of demand (read+write) hits
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 14265253 # number of writebacks
system.cpu.icache.writebacks::total 14265253 # number of writebacks
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 1725806 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65319.576270 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 46897183 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.956711 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 425634048 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 425634048 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 509091 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255953 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 765044 # number of ReadReq hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 2693 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2693 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq 1229988 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 23339142 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 55016338 # Request fanout histogram
+system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 40242 # Transaction distribution
system.iobus.trans_dist::ReadResp 40242 # Transaction distribution
system.iobus.trans_dist::WriteReq 136515 # Transaction distribution
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 7491944 # Cumulative packet size per connected master and slave (bytes)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 115459 # number of replacements
system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1039650 # Number of tag accesses
system.iocache.tags.data_accesses 1039650 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.writebacks::writebacks 106631 # number of writebacks
system.iocache.writebacks::total 106631 # number of writebacks
+system.membus.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 76679 # Transaction distribution
system.membus.trans_dist::ReadResp 524946 # Transaction distribution
system.membus.trans_dist::WriteReq 33606 # Transaction distribution
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 3924997 # Request fanout histogram
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
---------- End Simulation Statistics ----------
sim_ticks 47522770414500 # Number of ticks simulated
final_tick 47522770414500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 771698 # Simulator instruction rate (inst/s)
-host_op_rate 907739 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 41601502224 # Simulator tick rate (ticks/s)
-host_mem_usage 746908 # Number of bytes of host memory used
-host_seconds 1142.33 # Real time elapsed on the host
+host_inst_rate 967829 # Simulator instruction rate (inst/s)
+host_op_rate 1138446 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 52174728436 # Simulator tick rate (ticks/s)
+host_mem_usage 796444 # Number of bytes of host memory used
+host_seconds 910.84 # Real time elapsed on the host
sim_insts 881535802 # Number of instructions simulated
sim_ops 1036940641 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker 93760 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 96448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 3323828 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 244273354008 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks 111522 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 111522 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 12043 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.hits 165523016 # DTB hits
system.cpu0.dtb.misses 111522 # DTB misses
system.cpu0.dtb.accesses 165634538 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks 57441 # Table walker walks requested
system.cpu0.itb.walker.walksLong 57441 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2 633 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.hits 461199865 # DTB hits
system.cpu0.itb.misses 57441 # DTB misses
system.cpu0.itb.accesses 461257306 # DTB accesses
+system.cpu0.numPwrStateTransitions 27854 # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples 13927 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean 3371332712.012135 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev 65010943687.031532 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows 3873 27.81% 27.81% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10 10023 71.97% 99.78% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.80% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.81% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.81% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.83% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::overflows 18 0.13% 100.00% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::max_value 1988778348716 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total 13927 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON 570219734307 # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 46952550680193 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 95045540829 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 541493758 # Class of executed instruction
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 5689621 # number of replacements
system.cpu0.dcache.tags.tagsinuse 508.423656 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 159582136 # Total number of references to valid blocks.
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 336711039 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 336711039 # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 80892970 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 80892970 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 74279623 # number of WriteReq hits
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183661.313684 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93613.644753 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93613.644753 # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 5142905 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.908178 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 456056448 # Total number of references to valid blocks.
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 927543147 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 927543147 # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 456056448 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 456056448 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 456056448 # number of demand (read+write) hits
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88567.420290 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88567.420290 # average overall mshr uncacheable latency
+system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued 7619798 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 7619814 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 1013066 # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements 2348165 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 16134.688776 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 15333996 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.897705 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 367708056 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 367708056 # Number of data accesses
+system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 263860 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 148030 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 411890 # number of ReadReq hits
system.cpu0.toL2Bus.snoop_filter.tot_snoops 1820685 # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1820422 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 263 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq 564136 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 9642625 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 26565 # Transaction distribution
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy 321847000 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks 105013 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 105013 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10670 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.hits 151485069 # DTB hits
system.cpu1.dtb.misses 105013 # DTB misses
system.cpu1.dtb.accesses 151590082 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks 58945 # Table walker walks requested
system.cpu1.itb.walker.walksLong 58945 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 561 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.hits 420888418 # DTB hits
system.cpu1.itb.misses 58945 # DTB misses
system.cpu1.itb.accesses 420947363 # DTB accesses
+system.cpu1.numPwrStateTransitions 9975 # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples 4987 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean 9429340547.425106 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev 186307084392.504211 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows 3401 68.20% 68.20% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10 1566 31.40% 99.60% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+10-1e+11 7 0.14% 99.74% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 2 0.04% 99.78% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.80% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.02% 99.82% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.02% 99.84% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::overflows 8 0.16% 100.00% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::max_value 7390880609428 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total 4987 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON 498649104491 # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 47024121310009 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 95045540824 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 496042597 # Class of executed instruction
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements 5018466 # number of replacements
system.cpu1.dcache.tags.tagsinuse 434.493139 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 146277741 # Total number of references to valid blocks.
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 308017993 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 308017993 # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data 73753622 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 73753622 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 68485479 # number of WriteReq hits
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171657.272315 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 82415.506439 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 82415.506439 # average overall mshr uncacheable latency
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements 4797887 # number of replacements
system.cpu1.icache.tags.tagsinuse 496.259979 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 416090013 # Total number of references to valid blocks.
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 846575240 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 846575240 # Number of data accesses
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst 416090013 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 416090013 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 416090013 # number of demand (read+write) hits
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92968.181818 # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92968.181818 # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92968.181818 # average overall mshr uncacheable latency
+system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued 6995617 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 6995617 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 854583 # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements 1970256 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 13301.448664 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 14231615 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.847717 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 333785497 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 333785497 # Number of data accesses
+system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 241732 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 150683 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 392415 # number of ReadReq hits
system.cpu1.toL2Bus.snoop_filter.tot_snoops 1760623 # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1760449 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 174 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq 491097 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 8950741 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 11949 # Transaction distribution
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy 303810499 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 40346 # Transaction distribution
system.iobus.trans_dist::ReadResp 40346 # Transaction distribution
system.iobus.trans_dist::WriteReq 136634 # Transaction distribution
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 115585 # number of replacements
system.iocache.tags.tagsinuse 11.243817 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1040784 # Number of tag accesses
system.iocache.tags.data_accesses 1040784 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8875 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8912 # number of ReadReq misses
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 75598.897286 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 75603.606124 # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 1336257 # number of replacements
system.l2c.tags.tagsinuse 63239.486009 # Cycle average of tags in use
system.l2c.tags.total_refs 5390392 # Total number of references to valid blocks.
system.l2c.tags.occ_task_id_percent::1024 0.730392 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 69855982 # Number of tag accesses
system.l2c.tags.data_accesses 69855982 # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 2606701 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 2606701 # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data 157949 # number of UpgradeReq hits
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 81885 # Transaction distribution
system.membus.trans_dist::ReadResp 837971 # Transaction distribution
system.membus.trans_dist::WriteReq 38514 # Transaction distribution
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 45398182 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 10840157 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 5896724 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 1754214 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 132701 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 121224 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 11477 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 81887 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 4082535 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 38514 # Transaction distribution
sim_ticks 51759374264500 # Number of ticks simulated
final_tick 51759374264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 790659 # Simulator instruction rate (inst/s)
-host_op_rate 929140 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 48897567060 # Simulator tick rate (ticks/s)
-host_mem_usage 670860 # Number of bytes of host memory used
-host_seconds 1058.53 # Real time elapsed on the host
+host_inst_rate 1051370 # Simulator instruction rate (inst/s)
+host_op_rate 1235514 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 65021013988 # Simulator tick rate (ticks/s)
+host_mem_usage 718040 # Number of bytes of host memory used
+host_seconds 796.04 # Real time elapsed on the host
sim_insts 836933434 # Number of instructions simulated
sim_ops 983519389 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.dtb.walker 155264 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 159360 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 4743732 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 242783406787 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 187211 # Table walker walks requested
system.cpu.dtb.walker.walksLong 187211 # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2 12337 # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.hits 300492546 # DTB hits
system.cpu.dtb.misses 187211 # DTB misses
system.cpu.dtb.accesses 300679757 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 119486 # Table walker walks requested
system.cpu.itb.walker.walksLong 119486 # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walksLongTerminationLevel::Level2 1122 # Level at which table walker walks with long descriptors terminate
system.cpu.itb.hits 837449249 # DTB hits
system.cpu.itb.misses 119486 # DTB misses
system.cpu.itb.accesses 837568735 # DTB accesses
+system.cpu.numPwrStateTransitions 32056 # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples 16028 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean 3133737148.696906 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev 60742072610.602715 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::underflows 6738 42.04% 42.04% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10 9255 57.74% 99.78% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::8e+11-8.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::max_value 1988775138696 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::total 16028 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::ON 1531835245186 # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 50227539019314 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 103518748529 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 984078328 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 9381962 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.942718 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 290912714 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1211017846 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1211017846 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 147435449 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 147435449 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 135766146 # number of WriteReq hits
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183955.892825 # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91969.759680 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91969.759680 # average overall mshr uncacheable latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 13331164 # number of replacements
system.cpu.icache.tags.tagsinuse 511.820795 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 824117568 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 850780930 # Number of tag accesses
system.cpu.icache.tags.data_accesses 850780930 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 824117568 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 824117568 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 824117568 # number of demand (read+write) hits
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.423188 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126070.423188 # average overall mshr uncacheable latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 1036266 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65255.052774 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 41658706 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.946457 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 372058779 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 372058779 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 313678 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 242392 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 556070 # number of ReadReq hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 2704 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2704 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq 981994 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 20540984 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 33708 # Transaction distribution
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy 548107000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 40345 # Transaction distribution
system.iobus.trans_dist::ReadResp 40345 # Transaction distribution
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 115506 # number of replacements
system.iocache.tags.tagsinuse 10.446851 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1040073 # Number of tag accesses
system.iocache.tags.data_accesses 1040073 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8860 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8897 # number of ReadReq misses
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 80143.494053 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 80145.356746 # average overall mshr miss latency
+system.membus.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 76827 # Transaction distribution
system.membus.trans_dist::ReadResp 389416 # Transaction distribution
system.membus.trans_dist::WriteReq 33708 # Transaction distribution
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 44825406 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states
---------- End Simulation Statistics ----------
sim_ticks 51111166190000 # Number of ticks simulated
final_tick 51111166190000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1183514 # Simulator instruction rate (inst/s)
-host_op_rate 1390863 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 61528862033 # Simulator tick rate (ticks/s)
-host_mem_usage 673932 # Number of bytes of host memory used
-host_seconds 830.69 # Real time elapsed on the host
+host_inst_rate 1663860 # Simulator instruction rate (inst/s)
+host_op_rate 1955365 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 86501229007 # Simulator tick rate (ticks/s)
+host_mem_usage 721112 # Number of bytes of host memory used
+host_seconds 590.87 # Real time elapsed on the host
sim_insts 983128290 # Number of instructions simulated
sim_ops 1155370468 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker 206080 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 186880 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 3298228 # Number of bytes read from this memory
system.physmem.bw_total::cpu1.data 720807 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 8515 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3617200 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks 145178 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 145178 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walkWaitTime::samples 145178 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.hits 176040109 # DTB hits
system.cpu0.dtb.misses 145178 # DTB misses
system.cpu0.dtb.accesses 176185287 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks 70488 # Table walker walks requested
system.cpu0.itb.walker.walksLong 70488 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walkWaitTime::samples 70488 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.hits 493160707 # DTB hits
system.cpu0.itb.misses 70488 # DTB misses
system.cpu0.itb.accesses 493231195 # DTB accesses
+system.cpu0.numPwrStateTransitions 16910 # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples 8455 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean 5871638061.761680 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev 113702139546.283386 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows 3675 43.47% 43.47% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10 4716 55.78% 99.24% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.01% 99.25% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 45 0.53% 99.79% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 5 0.06% 99.85% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::overflows 12 0.14% 100.00% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::max_value 3977575082060 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total 8455 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON 1466466377805 # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 49644699812195 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 98036837820 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 579270629 # Class of executed instruction
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 11609443 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 340216355 # Total number of references to valid blocks.
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 1418915240 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 1418915240 # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 85703422 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 85585649 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 171289071 # number of ReadReq hits
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks 8920157 # number of writebacks
system.cpu0.dcache.writebacks::total 8920157 # number of writebacks
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 14275419 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 969443892 # Total number of references to valid blocks.
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 997995764 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 997995764 # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 486058611 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 483385281 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 969443892 # number of ReadReq hits
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks 14275419 # number of writebacks
system.cpu0.icache.writebacks::total 14275419 # number of writebacks
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks 143940 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 143940 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walkWaitTime::samples 143940 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.hits 175620938 # DTB hits
system.cpu1.dtb.misses 143940 # DTB misses
system.cpu1.dtb.accesses 175764878 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks 69853 # Table walker walks requested
system.cpu1.itb.walker.walksLong 69853 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walkWaitTime::samples 69853 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.hits 490430918 # DTB hits
system.cpu1.itb.misses 69853 # DTB misses
system.cpu1.itb.accesses 490500771 # DTB accesses
+system.cpu1.numPwrStateTransitions 16606 # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples 8303 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean 6010299946.497049 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev 129216116342.205185 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows 3765 45.35% 45.35% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10 4474 53.88% 99.23% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.02% 99.25% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 4 0.05% 99.30% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 44 0.53% 99.83% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 3 0.04% 99.88% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::overflows 10 0.12% 100.00% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::max_value 5966367262704 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total 8303 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON 1207645734235 # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 49903520455765 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 97462088232 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 576734502 # Class of executed instruction
+system.iobus.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 40249 # Transaction distribution
system.iobus.trans_dist::ReadResp 40249 # Transaction distribution
system.iobus.trans_dist::WriteReq 136515 # Transaction distribution
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 7492000 # Cumulative packet size per connected master and slave (bytes)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 115466 # number of replacements
system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1039713 # Number of tag accesses
system.iocache.tags.data_accesses 1039713 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8820 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8857 # number of ReadReq misses
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.writebacks::writebacks 106631 # number of writebacks
system.iocache.writebacks::total 106631 # number of writebacks
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 1725552 # number of replacements
system.l2c.tags.tagsinuse 65318.589868 # Cycle average of tags in use
system.l2c.tags.total_refs 46997821 # Total number of references to valid blocks.
system.l2c.tags.occ_task_id_percent::1024 0.953751 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 426507397 # Number of tag accesses
system.l2c.tags.data_accesses 426507397 # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
system.l2c.ReadReq_hits::cpu0.dtb.walker 281107 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 145752 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 278085 # number of ReadReq hits
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 76679 # Transaction distribution
system.membus.trans_dist::ReadResp 524759 # Transaction distribution
system.membus.trans_dist::WriteReq 33606 # Transaction distribution
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 3924516 # Request fanout histogram
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 52432480 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 26546586 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 1741 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 2697 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 2697 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 1321968 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 23443629 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution
sim_ticks 51316242679000 # Number of ticks simulated
final_tick 51316242679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 408194 # Simulator instruction rate (inst/s)
-host_op_rate 479646 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 24400273917 # Simulator tick rate (ticks/s)
-host_mem_usage 732460 # Number of bytes of host memory used
-host_seconds 2103.10 # Real time elapsed on the host
+host_inst_rate 414274 # Simulator instruction rate (inst/s)
+host_op_rate 486791 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 24763727262 # Simulator tick rate (ticks/s)
+host_mem_usage 734172 # Number of bytes of host memory used
+host_seconds 2072.23 # Real time elapsed on the host
sim_insts 858473131 # Number of instructions simulated
sim_ops 1008744567 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker 84032 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 93120 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 2529588 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 111730336352 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks 91119 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 91119 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walkWaitTime::samples 91119 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.hits 122862311 # DTB hits
system.cpu0.dtb.misses 91119 # DTB misses
system.cpu0.dtb.accesses 122953430 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks 53727 # Table walker walks requested
system.cpu0.itb.walker.walksLong 53727 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walkWaitTime::samples 53727 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.hits 342517055 # DTB hits
system.cpu0.itb.misses 53727 # DTB misses
system.cpu0.itb.accesses 342570782 # DTB accesses
+system.cpu0.numPwrStateTransitions 11952 # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples 5976 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean 8382866475.975402 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev 212039540044.688660 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows 2476 41.43% 41.43% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10 3476 58.17% 99.60% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5e+10-1e+11 5 0.08% 99.68% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.70% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 4 0.07% 99.77% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.03% 99.80% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.02% 99.82% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.83% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::8.5e+11-9e+11 1 0.02% 99.85% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::overflows 9 0.15% 100.00% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::max_value 7947193331000 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total 5976 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON 1220232618571 # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 50096010060429 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 413468946 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 402883218 # Class of executed instruction
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 9811129 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.999716 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 296592840 # Total number of references to valid blocks.
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 1256795104 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 1256795104 # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 60226997 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 19487622 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 26552483 # number of ReadReq hits
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 94386.906747 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 91781.767395 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 94095.700835 # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 15904025 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.975046 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 561201521 # Total number of references to valid blocks.
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 593375053 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 593375053 # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 337059836 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 108650316 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 66739589 # number of ReadReq hits
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12469.061371 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12491.012251 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12470.669511 # average overall mshr miss latency
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks 32054 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 32054 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4620 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.hits 39504156 # DTB hits
system.cpu1.dtb.misses 32054 # DTB misses
system.cpu1.dtb.accesses 39536210 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks 20183 # Table walker walks requested
system.cpu1.itb.walker.walksLong 20183 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 931 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.hits 110361810 # DTB hits
system.cpu1.itb.misses 20183 # DTB misses
system.cpu1.itb.accesses 110381993 # DTB accesses
+system.cpu1.numPwrStateTransitions 6152 # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples 3076 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean 3956828120.931729 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev 203372693587.464539 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows 983 31.96% 31.96% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10 2090 67.95% 99.90% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.03% 99.93% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 1 0.03% 99.97% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::overflows 1 0.03% 100.00% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::max_value 11261492307001 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total 3076 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON 39145039379014 # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 12171203299986 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 1184092485 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.branchPred.indirectHits 808792 # Number of indirect target hits.
system.cpu2.branchPred.indirectMisses 349462 # Number of indirect misses.
system.cpu2.branchPredindirectMispredicted 143811 # Number of mispredicted indirect branches.
+system.cpu2.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu2.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.cpu2.dtb.walker.walks 93613 # Table walker walks requested
system.cpu2.dtb.walker.walksLong 93613 # Table walker walks initiated with long descriptors
system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 7056 # Level at which table walker walks with long descriptors terminate
system.cpu2.dtb.hits 53956197 # DTB hits
system.cpu2.dtb.misses 93613 # DTB misses
system.cpu2.dtb.accesses 54049810 # DTB accesses
+system.cpu2.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu2.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.cpu2.itb.walker.walks 26529 # Table walker walks requested
system.cpu2.itb.walker.walksLong 26529 # Table walker walks initiated with long descriptors
system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1840 # Level at which table walker walks with long descriptors terminate
system.cpu2.itb.hits 70694439 # DTB hits
system.cpu2.itb.misses 26529 # DTB misses
system.cpu2.itb.accesses 70720968 # DTB accesses
+system.cpu2.numPwrStateTransitions 6922 # Number of power state transitions
+system.cpu2.pwrStateClkGateDist::samples 3461 # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::mean 14586648609.314360 # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::stdev 130413867074.756348 # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::underflows 1099 31.75% 31.75% # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::1000-5e+10 2325 67.18% 98.93% # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::5e+10-1e+11 6 0.17% 99.10% # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::1e+11-1.5e+11 4 0.12% 99.22% # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.25% # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::2e+11-2.5e+11 2 0.06% 99.31% # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::2.5e+11-3e+11 2 0.06% 99.36% # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::3e+11-3.5e+11 1 0.03% 99.39% # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::4.5e+11-5e+11 1 0.03% 99.42% # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::5e+11-5.5e+11 1 0.03% 99.45% # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::7e+11-7.5e+11 1 0.03% 99.48% # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::overflows 18 0.52% 100.00% # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::max_value 1988791943000 # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::total 3461 # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateResidencyTicks::ON 831851842163 # Cumulative time (in ticks) in various power states
+system.cpu2.pwrStateResidencyTicks::CLK_GATED 50484390836837 # Cumulative time (in ticks) in various power states
system.cpu2.numCycles 1178523145 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu3.branchPred.indirectHits 1551109 # Number of indirect target hits.
system.cpu3.branchPred.indirectMisses 1484372 # Number of indirect misses.
system.cpu3.branchPredindirectMispredicted 245540 # Number of mispredicted indirect branches.
+system.cpu3.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu3.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.cpu3.dtb.walker.walks 515601 # Table walker walks requested
system.cpu3.dtb.walker.walksLong 515601 # Table walker walks initiated with long descriptors
system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8515 # Level at which table walker walks with long descriptors terminate
system.cpu3.dtb.hits 106537507 # DTB hits
system.cpu3.dtb.misses 515601 # DTB misses
system.cpu3.dtb.accesses 107053108 # DTB accesses
+system.cpu3.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu3.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.cpu3.itb.walker.walks 59193 # Table walker walks requested
system.cpu3.itb.walker.walksLong 59193 # Table walker walks initiated with long descriptors
system.cpu3.itb.walker.walksLongTerminationLevel::Level2 2031 # Level at which table walker walks with long descriptors terminate
system.cpu3.itb.hits 54025408 # DTB hits
system.cpu3.itb.misses 59193 # DTB misses
system.cpu3.itb.accesses 54084601 # DTB accesses
+system.cpu3.numPwrStateTransitions 7272 # Number of power state transitions
+system.cpu3.pwrStateClkGateDist::samples 3636 # Distribution of time spent in the clock gated state
+system.cpu3.pwrStateClkGateDist::mean 40583971.308581 # Distribution of time spent in the clock gated state
+system.cpu3.pwrStateClkGateDist::stdev 1016609649.397212 # Distribution of time spent in the clock gated state
+system.cpu3.pwrStateClkGateDist::underflows 2250 61.88% 61.88% # Distribution of time spent in the clock gated state
+system.cpu3.pwrStateClkGateDist::1000-5e+10 1386 38.12% 100.00% # Distribution of time spent in the clock gated state
+system.cpu3.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu3.pwrStateClkGateDist::max_value 36040957368 # Distribution of time spent in the clock gated state
+system.cpu3.pwrStateClkGateDist::total 3636 # Distribution of time spent in the clock gated state
+system.cpu3.pwrStateResidencyTicks::ON 51168679359322 # Cumulative time (in ticks) in various power states
+system.cpu3.pwrStateResidencyTicks::CLK_GATED 147563319678 # Cumulative time (in ticks) in various power states
system.cpu3.numCycles 361836520 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu3.cc_regfile_writes 71874336 # number of cc regfile writes
system.cpu3.misc_regfile_reads 658260097 # number of misc regfile reads
system.cpu3.misc_regfile_writes 8003769 # number of misc regfile writes
+system.iobus.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 40273 # Transaction distribution
system.iobus.trans_dist::ReadResp 40273 # Transaction distribution
system.iobus.trans_dist::WriteReq 136539 # Transaction distribution
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 70810000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 115466 # number of replacements
system.iocache.tags.tagsinuse 10.425431 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1039713 # Number of tag accesses
system.iocache.tags.data_accesses 1039713 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8820 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8857 # number of ReadReq misses
system.iocache.demand_avg_mshr_miss_latency::total 76903.162969 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 76903.162969 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 76903.162969 # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 1175380 # number of replacements
system.l2c.tags.tagsinuse 65273.508044 # Cycle average of tags in use
system.l2c.tags.total_refs 47870421 # Total number of references to valid blocks.
system.l2c.tags.occ_task_id_percent::1024 0.959320 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 423637613 # Number of tag accesses
system.l2c.tags.data_accesses 423637613 # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.l2c.ReadReq_hits::cpu0.dtb.walker 159297 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 109140 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 56643 # number of ReadReq hits
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 76738 # Transaction distribution
system.membus.trans_dist::ReadResp 443894 # Transaction distribution
system.membus.trans_dist::WriteReq 33648 # Transaction distribution
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 28713899 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 52099554 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 26383185 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 3169 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 2082 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 2082 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 1490866 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 23977004 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 33648 # Transaction distribution
sim_ticks 51317219225000 # Number of ticks simulated
final_tick 51317219225000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 190793 # Simulator instruction rate (inst/s)
-host_op_rate 224183 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 10734613908 # Simulator tick rate (ticks/s)
-host_mem_usage 694152 # Number of bytes of host memory used
-host_seconds 4780.54 # Real time elapsed on the host
+host_inst_rate 203116 # Simulator instruction rate (inst/s)
+host_op_rate 238662 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 11427931870 # Simulator tick rate (ticks/s)
+host_mem_usage 741344 # Number of bytes of host memory used
+host_seconds 4490.51 # Real time elapsed on the host
sim_insts 912094204 # Number of instructions simulated
sim_ops 1071714405 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker 178240 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 158592 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 3667840 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 176725372148 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst 768 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 1408 # Number of bytes read from this memory
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 27 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 43 # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cpu0.branchPred.indirectMisses 2320833 # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted 406549 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks 931838 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 931838 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17645 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.hits 187312532 # DTB hits
system.cpu0.dtb.misses 931838 # DTB misses
system.cpu0.dtb.accesses 188244370 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks 102509 # Table walker walks requested
system.cpu0.itb.walker.walksLong 102509 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2 2958 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.hits 94735666 # DTB hits
system.cpu0.itb.misses 102509 # DTB misses
system.cpu0.itb.accesses 94838175 # DTB accesses
+system.cpu0.numPwrStateTransitions 16108 # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples 8054 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean 3370274965.000869 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev 64926982226.426781 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows 3593 44.61% 44.61% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10 4444 55.18% 99.79% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.01% 99.80% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 3 0.04% 99.84% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::overflows 10 0.12% 100.00% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::max_value 1988782302928 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total 8054 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON 24173024656883 # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 27144194568117 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 677363519 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.cc_regfile_writes 128258211 # number of cc regfile writes
system.cpu0.misc_regfile_reads 1206144502 # number of misc regfile reads
system.cpu0.misc_regfile_writes 15679564 # number of misc regfile writes
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 10794532 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.983410 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 308661870 # Total number of references to valid blocks.
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 1362392595 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 1362392595 # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 80965730 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 82351460 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 163317190 # number of ReadReq hits
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 92111.112619 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 94012.951926 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92973.047182 # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 16477862 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.835978 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 172394682 # Total number of references to valid blocks.
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 206602499 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 206602499 # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 85625549 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 86769133 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 172394682 # number of ReadReq hits
system.cpu1.branchPred.indirectHits 2721808 # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses 2422742 # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted 415682 # Number of mispredicted indirect branches.
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks 920636 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 920636 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17624 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.hits 190728754 # DTB hits
system.cpu1.dtb.misses 920636 # DTB misses
system.cpu1.dtb.accesses 191649390 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks 101988 # Table walker walks requested
system.cpu1.itb.walker.walksLong 101988 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 3087 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.hits 95828100 # DTB hits
system.cpu1.itb.misses 101988 # DTB misses
system.cpu1.itb.accesses 95930088 # DTB accesses
+system.cpu1.numPwrStateTransitions 16766 # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples 8383 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean 2803271183.603841 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev 54004965145.463799 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows 3515 41.93% 41.93% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10 4849 57.84% 99.77% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+10-1e+11 4 0.05% 99.82% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 3 0.04% 99.89% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::overflows 8 0.10% 100.00% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::max_value 1988782222956 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total 8383 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON 27817396892849 # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 23499822332151 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 668684774 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.cc_regfile_writes 129852515 # number of cc regfile writes
system.cpu1.misc_regfile_reads 1200738028 # number of misc regfile reads
system.cpu1.misc_regfile_writes 15156718 # number of misc regfile writes
+system.iobus.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 40297 # Transaction distribution
system.iobus.trans_dist::ReadResp 40297 # Transaction distribution
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 115457 # number of replacements
system.iocache.tags.tagsinuse 10.425589 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1039641 # Number of tag accesses
system.iocache.tags.data_accesses 1039641 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8812 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8849 # number of ReadReq misses
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87425 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 75048.409418 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 75052.695090 # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 1414907 # number of replacements
system.l2c.tags.tagsinuse 65322.046709 # Cycle average of tags in use
system.l2c.tags.total_refs 51048957 # Total number of references to valid blocks.
system.l2c.tags.occ_task_id_percent::1024 0.963455 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 452888307 # Number of tag accesses
system.l2c.tags.data_accesses 452888307 # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.l2c.ReadReq_hits::cpu0.dtb.walker 548032 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 184031 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 541554 # number of ReadReq hits
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 54318 # Transaction distribution
system.membus.trans_dist::ReadResp 482453 # Transaction distribution
system.membus.trans_dist::WriteReq 33697 # Transaction distribution
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 44601796 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 55407066 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 28133350 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 5182 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 1867 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 1867 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 2058891 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 25917963 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 33697 # Transaction distribution
sim_ticks 51820999867500 # Number of ticks simulated
final_tick 51820999867500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 784285 # Simulator instruction rate (inst/s)
-host_op_rate 921634 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 45455267989 # Simulator tick rate (ticks/s)
-host_mem_usage 675212 # Number of bytes of host memory used
-host_seconds 1140.04 # Real time elapsed on the host
+host_inst_rate 1076689 # Simulator instruction rate (inst/s)
+host_op_rate 1265246 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 62402323103 # Simulator tick rate (ticks/s)
+host_mem_usage 722120 # Number of bytes of host memory used
+host_seconds 830.43 # Real time elapsed on the host
sim_insts 894119248 # Number of instructions simulated
sim_ops 1050702892 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker 122816 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 126336 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 2599472 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 265157286235 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks 133030 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 133030 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 21129 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.hits 159828196 # DTB hits
system.cpu0.dtb.misses 133030 # DTB misses
system.cpu0.dtb.accesses 159961226 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks 78025 # Table walker walks requested
system.cpu0.itb.walker.walksLong 78025 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4409 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.hits 446488504 # DTB hits
system.cpu0.itb.misses 78025 # DTB misses
system.cpu0.itb.accesses 446566529 # DTB accesses
+system.cpu0.numPwrStateTransitions 16564 # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples 8282 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean 6000025981.117725 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev 124621883322.639465 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows 3529 42.61% 42.61% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10 4688 56.60% 99.22% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.01% 99.23% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 5 0.06% 99.29% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 45 0.54% 99.83% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::overflows 10 0.12% 100.00% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::max_value 5700356796932 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total 8282 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON 2128784691883 # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 49692215175617 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 51821574278 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 524698416 # Class of executed instruction
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 10234473 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.965653 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 310064662 # Total number of references to valid blocks.
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 1291899613 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 1291899613 # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 78014225 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 78760782 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 156775007 # number of ReadReq hits
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97945.918815 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 87529.813158 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92455.121930 # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 13785272 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.891071 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 880886027 # Total number of references to valid blocks.
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 908457605 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 908457605 # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 439628868 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 441257159 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 880886027 # number of ReadReq hits
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 75588.315846 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 75805.389222 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 75674.898551 # average overall mshr uncacheable latency
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks 133445 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 133445 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 20908 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.hits 160672898 # DTB hits
system.cpu1.dtb.misses 133445 # DTB misses
system.cpu1.dtb.accesses 160806343 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks 78111 # Table walker walks requested
system.cpu1.itb.walker.walksLong 78111 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4330 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.hits 448183312 # DTB hits
system.cpu1.itb.misses 78111 # DTB misses
system.cpu1.itb.accesses 448261423 # DTB accesses
+system.cpu1.numPwrStateTransitions 16084 # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples 8042 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean 6194937221.007833 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev 118254200557.171326 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows 3517 43.73% 43.73% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10 4458 55.43% 99.17% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.06% 99.23% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 45 0.56% 99.79% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.81% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::overflows 13 0.16% 100.00% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::max_value 3977581677820 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total 8042 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON 2001314736155 # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 49819685131345 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 51820425457 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 526600168 # Class of executed instruction
+system.iobus.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 40318 # Transaction distribution
system.iobus.trans_dist::ReadResp 40318 # Transaction distribution
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 115478 # number of replacements
system.iocache.tags.tagsinuse 10.457315 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1039830 # Number of tag accesses
system.iocache.tags.data_accesses 1039830 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8833 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8870 # number of ReadReq misses
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85937.500000 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 74458.536178 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 74462.510304 # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 1307385 # number of replacements
system.l2c.tags.tagsinuse 65260.397522 # Cycle average of tags in use
system.l2c.tags.total_refs 44030779 # Total number of references to valid blocks.
system.l2c.tags.occ_task_id_percent::1024 0.958069 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 395683924 # Number of tag accesses
system.l2c.tags.data_accesses 395683924 # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
system.l2c.ReadReq_hits::cpu0.dtb.walker 246270 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 166121 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 249681 # number of ReadReq hits
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 76831 # Transaction distribution
system.membus.trans_dist::ReadResp 450834 # Transaction distribution
system.membus.trans_dist::WriteReq 33710 # Transaction distribution
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 44722660 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 48668708 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 24647917 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 1743 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 2076 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 2076 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 1292402 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 21924695 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution
sim_ticks 61234797500 # Number of ticks simulated
final_tick 61234797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 196562 # Simulator instruction rate (inst/s)
-host_op_rate 197541 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 132848546 # Simulator tick rate (ticks/s)
-host_mem_usage 399976 # Number of bytes of host memory used
-host_seconds 460.94 # Real time elapsed on the host
+host_inst_rate 433531 # Simulator instruction rate (inst/s)
+host_op_rate 435690 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 293005809 # Simulator tick rate (ticks/s)
+host_mem_usage 447448 # Number of bytes of host memory used
+host_seconds 208.99 # Real time elapsed on the host
sim_insts 90602850 # Number of instructions simulated
sim_ops 91054081 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory
system.physmem.bytes_read::total 996672 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1797845750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 20750031 # Number of BP lookups
system.cpu.branchPred.condPredicted 17060378 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect
system.cpu.branchPred.indirectMisses 1410 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 61234797500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 122469595 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class_0::total 91054081 # Class of committed instruction
system.cpu.tickCycles 109245506 # Number of cycles that the object actually ticked
system.cpu.idleCycles 13224089 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 946097 # number of replacements
system.cpu.dcache.tags.tagsinuse 3616.804007 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 26262686 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 55454003 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 55454003 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 21593712 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 21593712 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4660692 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12993.116640 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12993.240321 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12993.240321 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 5 # number of replacements
system.cpu.icache.tags.tagsinuse 689.102041 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 27766889 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 55536181 # Number of tag accesses
system.cpu.icache.tags.data_accesses 55536181 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 27766889 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 27766889 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 27766889 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74191.011236 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 10244.686315 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1833993 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474731 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 15237888 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 15237888 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 943278 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 943278 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 943278 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1425292494 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 1029 # Transaction distribution
system.membus.trans_dist::ReadExReq 14544 # Transaction distribution
system.membus.trans_dist::ReadExResp 14544 # Transaction distribution
sim_ticks 58199030500 # Number of ticks simulated
final_tick 58199030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 218368 # Simulator instruction rate (inst/s)
-host_op_rate 219455 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 140289424 # Simulator tick rate (ticks/s)
-host_mem_usage 534192 # Number of bytes of host memory used
-host_seconds 414.85 # Real time elapsed on the host
+host_inst_rate 220490 # Simulator instruction rate (inst/s)
+host_op_rate 221588 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 141652578 # Simulator tick rate (ticks/s)
+host_mem_usage 534836 # Number of bytes of host memory used
+host_seconds 410.86 # Real time elapsed on the host
sim_insts 90589799 # Number of instructions simulated
sim_ops 91041030 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 44352 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 87616 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher 925056 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1793992016 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 28233538 # Number of BP lookups
system.cpu.branchPred.condPredicted 23266052 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 835390 # Number of conditional branches incorrect
system.cpu.branchPred.indirectMisses 1738 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 245 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 58199030500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 116398062 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.cc_regfile_writes 58686555 # number of cc regfile writes
system.cpu.misc_regfile_reads 28410103 # number of misc regfile reads
system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 5470634 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.784091 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 18249365 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 61906904 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 61906904 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 13887331 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 13887331 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4353747 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 8329.949445 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8329.982560 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 8329.982560 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 447 # number of replacements
system.cpu.icache.tags.tagsinuse 427.448157 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 32273898 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.892578 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 64550990 # Number of tag accesses
system.cpu.icache.tags.data_accesses 64550990 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 32273898 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 32273898 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 32273898 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency
+system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.prefetcher.num_hwpf_issued 4981065 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 5296247 # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit 274020 # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage 14074841 # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 248 # number of replacements
system.cpu.l2cache.tags.tagsinuse 11235.818499 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 5318374 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884155 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 180510207 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 180510207 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 5451171 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 5451171 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 17033 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 303361 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302576 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 5245531 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 5451346 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 19910 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 8206724991 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 16175 # Transaction distribution
system.membus.trans_dist::WritebackDirty 175 # Transaction distribution
system.membus.trans_dist::CleanEvict 63 # Transaction distribution
sim_ticks 361597758500 # Number of ticks simulated
final_tick 361597758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 779266 # Simulator instruction rate (inst/s)
-host_op_rate 779298 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1155667536 # Simulator tick rate (ticks/s)
-host_mem_usage 379236 # Number of bytes of host memory used
-host_seconds 312.89 # Real time elapsed on the host
+host_inst_rate 1652209 # Simulator instruction rate (inst/s)
+host_op_rate 1652277 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2450259534 # Simulator tick rate (ticks/s)
+host_mem_usage 427260 # Number of bytes of host memory used
+host_seconds 147.58 # Real time elapsed on the host
sim_insts 243825150 # Number of instructions simulated
sim_ops 243835265 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory
system.physmem.bytes_read::total 998592 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 155576 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2606034 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2761610 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 443 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 361597758500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 723195517 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 244431613 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 935475 # number of replacements
system.cpu.dcache.tags.tagsinuse 3562.412338 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 25 # number of replacements
system.cpu.icache.tags.tagsinuse 725.404879 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses
system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 9729.320449 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 15069916 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 15069916 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 935266 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 935266 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 25 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 935266 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 25 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 1036 # Transaction distribution
system.membus.trans_dist::ReadExReq 14567 # Transaction distribution
system.membus.trans_dist::ReadExResp 14567 # Transaction distribution
sim_ticks 65986743500 # Number of ticks simulated
final_tick 65986743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 84238 # Simulator instruction rate (inst/s)
-host_op_rate 148330 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 35183666 # Simulator tick rate (ticks/s)
-host_mem_usage 410392 # Number of bytes of host memory used
-host_seconds 1875.49 # Real time elapsed on the host
+host_inst_rate 167131 # Simulator instruction rate (inst/s)
+host_op_rate 294291 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 69805272 # Simulator tick rate (ticks/s)
+host_mem_usage 458048 # Number of bytes of host memory used
+host_seconds 945.30 # Real time elapsed on the host
sim_insts 157988547 # Number of instructions simulated
sim_ops 278192464 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 69440 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1890368 # Number of bytes read from this memory
system.physmem.bytes_read::total 1959808 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 2563655500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 40828848 # Number of BP lookups
system.cpu.branchPred.condPredicted 40828848 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1470674 # Number of conditional branches incorrect
system.cpu.branchPred.indirectMisses 5611035 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 566146 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states
system.cpu.workload.num_syscalls 444 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 65986743500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 131973488 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.cc_regfile_writes 65602098 # number of cc regfile writes
system.cpu.misc_regfile_reads 202573497 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 2073508 # number of replacements
system.cpu.dcache.tags.tagsinuse 4068.413497 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 71894591 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 151442194 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 151442194 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 40548572 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 40548572 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 31346019 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13004.013995 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 93 # number of replacements
system.cpu.icache.tags.tagsinuse 870.928206 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 29996478 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 59996959 # Number of tag accesses
system.cpu.icache.tags.data_accesses 59996959 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 29996478 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 29996478 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 29996478 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 76086.701707 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76086.701707 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 76086.701707 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 650 # number of replacements
system.cpu.l2cache.tags.tagsinuse 20606.403574 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 4037654 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.914673 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 33330894 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 33330894 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 2066969 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 2066969 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 93 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 325 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 325 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 1996829 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 2067249 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 93 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3116406000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 4.7 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 1640 # Transaction distribution
system.membus.trans_dist::WritebackDirty 280 # Transaction distribution
system.membus.trans_dist::CleanEvict 45 # Transaction distribution
sim_ticks 366199170500 # Number of ticks simulated
final_tick 366199170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 433838 # Simulator instruction rate (inst/s)
-host_op_rate 763918 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1005585249 # Simulator tick rate (ticks/s)
-host_mem_usage 405532 # Number of bytes of host memory used
-host_seconds 364.17 # Real time elapsed on the host
+host_inst_rate 926071 # Simulator instruction rate (inst/s)
+host_op_rate 1630662 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2146525407 # Simulator tick rate (ticks/s)
+host_mem_usage 453968 # Number of bytes of host memory used
+host_seconds 170.60 # Real time elapsed on the host
sim_insts 157988548 # Number of instructions simulated
sim_ops 278192465 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1871424 # Number of bytes read from this memory
system.physmem.bytes_read::total 1922816 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 140339 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5110399 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 5268565 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
system.cpu.workload.num_syscalls 444 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 366199170500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 732398341 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 278192465 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 2062733 # number of replacements
system.cpu.dcache.tags.tagsinuse 4076.299825 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 24 # number of replacements
system.cpu.icache.tags.tagsinuse 665.627299 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.382812 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 435393136 # Number of tag accesses
system.cpu.icache.tags.data_accesses 435393136 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 217695356 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 217695356 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 217695356 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 313 # number of replacements
system.cpu.l2cache.tags.tagsinuse 20037.622351 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3992697 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.906616 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 33179282 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 33179282 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 2062482 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 2062482 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 24 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 197 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 197 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 2062584 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 24 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 1020 # Transaction distribution
system.membus.trans_dist::WritebackDirty 102 # Transaction distribution
system.membus.trans_dist::CleanEvict 14 # Transaction distribution
sim_ticks 412079966500 # Number of ticks simulated
final_tick 412079966500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 240872 # Simulator instruction rate (inst/s)
-host_op_rate 240872 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 162212982 # Simulator tick rate (ticks/s)
-host_mem_usage 251076 # Number of bytes of host memory used
-host_seconds 2540.36 # Real time elapsed on the host
+host_inst_rate 523017 # Simulator instruction rate (inst/s)
+host_op_rate 523017 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 352221098 # Simulator tick rate (ticks/s)
+host_mem_usage 299640 # Number of bytes of host memory used
+host_seconds 1169.95 # Real time elapsed on the host
sim_insts 611901617 # Number of instructions simulated
sim_ops 611901617 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 156608 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24143296 # Number of bytes read from this memory
system.physmem.bytes_read::total 24299904 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 73580458750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 123917421 # Number of BP lookups
system.cpu.branchPred.condPredicted 87658943 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 6214661 # Number of conditional branches incorrect
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 485 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 412079966500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 824159933 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class_0::total 611901617 # Class of committed instruction
system.cpu.tickCycles 739333991 # Number of cycles that the object actually ticked
system.cpu.idleCycles 84825942 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 2535268 # number of replacements
system.cpu.dcache.tags.tagsinuse 4087.644038 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 202570428 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 414584966 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 414584966 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 146904269 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 146904269 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 55666159 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22270.814661 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22270.814661 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22270.814661 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 3158 # number of replacements
system.cpu.icache.tags.tagsinuse 1117.678366 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 226045682 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.892578 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 452106322 # Number of tag accesses
system.cpu.icache.tags.data_accesses 452106322 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 226045682 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 226045682 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 226045682 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 45856.899318 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45856.899318 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 45856.899318 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 347705 # number of replacements
system.cpu.l2cache.tags.tagsinuse 29504.977164 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3908748 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.989685 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 41820503 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 41820503 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 2339413 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 2339413 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 3158 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 2394 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2394 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 1766190 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 2633020 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 3158 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3809046000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 173378 # Transaction distribution
system.membus.trans_dist::WritebackDirty 293607 # Transaction distribution
system.membus.trans_dist::CleanEvict 51709 # Transaction distribution
sim_ticks 362631828500 # Number of ticks simulated
final_tick 362631828500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 177215 # Simulator instruction rate (inst/s)
-host_op_rate 191948 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 126858592 # Simulator tick rate (ticks/s)
-host_mem_usage 271160 # Number of bytes of host memory used
-host_seconds 2858.55 # Real time elapsed on the host
+host_inst_rate 379372 # Simulator instruction rate (inst/s)
+host_op_rate 410911 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 271571493 # Simulator tick rate (ticks/s)
+host_mem_usage 317732 # Number of bytes of host memory used
+host_seconds 1335.31 # Real time elapsed on the host
sim_insts 506579366 # Number of instructions simulated
sim_ops 548692589 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 179456 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9032064 # Number of bytes read from this memory
system.physmem.bytes_read::total 9211520 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 57113763250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 131880511 # Number of BP lookups
system.cpu.branchPred.condPredicted 98032974 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 5909980 # Number of conditional branches incorrect
system.cpu.branchPred.indirectMisses 8121 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 53795 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 362631828500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 725263657 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class_0::total 548692589 # Class of committed instruction
system.cpu.tickCycles 688919604 # Number of cycles that the object actually ticked
system.cpu.idleCycles 36344053 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 1141477 # number of replacements
system.cpu.dcache.tags.tagsinuse 4070.722142 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 170992714 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 346245015 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 346245015 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 114475063 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 114475063 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 53537828 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20520.422763 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20521.099485 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20521.099485 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 18130 # number of replacements
system.cpu.icache.tags.tagsinuse 1186.413401 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 198770599 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.913574 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 397601201 # Number of tag accesses
system.cpu.icache.tags.data_accesses 397601201 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 198770599 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 198770599 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 198770599 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21750.787461 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 112376 # number of replacements
system.cpu.l2cache.tags.tagsinuse 27628.930561 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1772118 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.952515 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 19061751 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 19061751 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 1069336 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 1069336 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 17893 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 2608 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2605 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 808883 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 1166546 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 18130 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1718367983 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 42981 # Transaction distribution
system.membus.trans_dist::WritebackDirty 97210 # Transaction distribution
system.membus.trans_dist::CleanEvict 12558 # Transaction distribution
sim_ticks 232864525000 # Number of ticks simulated
final_tick 232864525000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 230904 # Simulator instruction rate (inst/s)
-host_op_rate 250150 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 106424359 # Simulator tick rate (ticks/s)
-host_mem_usage 342436 # Number of bytes of host memory used
-host_seconds 2188.08 # Real time elapsed on the host
+host_inst_rate 221507 # Simulator instruction rate (inst/s)
+host_op_rate 239970 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 102093126 # Simulator tick rate (ticks/s)
+host_mem_usage 343096 # Number of bytes of host memory used
+host_seconds 2280.90 # Real time elapsed on the host
sim_insts 505234934 # Number of instructions simulated
sim_ops 547348155 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 523840 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10146304 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher 16460800 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 108384997620 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 174583649 # Number of BP lookups
system.cpu.branchPred.condPredicted 131051926 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 7234327 # Number of conditional branches incorrect
system.cpu.branchPred.indirectMisses 14023 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 53864 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 232864525000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 465729051 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.cc_regfile_writes 376539611 # number of cc regfile writes
system.cpu.misc_regfile_reads 217603177 # number of misc regfile reads
system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 2817145 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.627957 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 168870791 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 355267161 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 355267161 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 114168570 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 114168570 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 51722271 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12117.964016 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12118.158615 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12118.158615 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 76528 # number of replacements
system.cpu.icache.tags.tagsinuse 466.435319 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 235186472 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 470619957 # Number of tag accesses
system.cpu.icache.tags.data_accesses 470619957 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 235186472 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 235186472 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 235186472 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14634.139793 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency
+system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.prefetcher.num_hwpf_issued 8513492 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 8514887 # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit 402 # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage 743841 # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 395630 # number of replacements
system.cpu.l2cache.tags.tagsinuse 15127.357564 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3184940 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908081 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 94885258 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 94885258 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 2350571 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 2350571 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 519224 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 261080 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 244791 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 16289 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 2372715 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 2642925 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 543102 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 4226522955 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 420223 # Transaction distribution
system.membus.trans_dist::WritebackDirty 292354 # Transaction distribution
system.membus.trans_dist::CleanEvict 98859 # Transaction distribution
sim_ticks 279360903000 # Number of ticks simulated
final_tick 279360903000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2212896 # Simulator instruction rate (inst/s)
-host_op_rate 2396859 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1220336248 # Simulator tick rate (ticks/s)
-host_mem_usage 304900 # Number of bytes of host memory used
-host_seconds 228.92 # Real time elapsed on the host
+host_inst_rate 2143205 # Simulator instruction rate (inst/s)
+host_op_rate 2321375 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1181904303 # Simulator tick rate (ticks/s)
+host_mem_usage 305572 # Number of bytes of host memory used
+host_seconds 236.37 # Real time elapsed on the host
sim_insts 506578818 # Number of instructions simulated
sim_ops 548692039 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 2066434344 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 422848347 # Number of bytes read from this memory
system.physmem.bytes_read::total 2489282691 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7397006245 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2287059270 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9684065515 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 279360903000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 558721807 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 548692589 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 630707528 # Transaction distribution
system.membus.trans_dist::ReadResp 632196069 # Transaction distribution
system.membus.trans_dist::WriteReq 54239049 # Transaction distribution
sim_ticks 708539449500 # Number of ticks simulated
final_tick 708539449500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1440714 # Simulator instruction rate (inst/s)
-host_op_rate 1560229 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2021455048 # Simulator tick rate (ticks/s)
-host_mem_usage 314896 # Number of bytes of host memory used
-host_seconds 350.51 # Real time elapsed on the host
+host_inst_rate 1462928 # Simulator instruction rate (inst/s)
+host_op_rate 1584286 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2052623495 # Simulator tick rate (ticks/s)
+host_mem_usage 315564 # Number of bytes of host memory used
+host_seconds 345.19 # Real time elapsed on the host
sim_insts 504984064 # Number of instructions simulated
sim_ops 546875315 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 147392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8963904 # Number of bytes read from this memory
system.physmem.bytes_read::total 9111296 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 208022 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 12651242 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 21560431 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 708539449500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 1417078899 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 548692589 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 1136276 # number of replacements
system.cpu.dcache.tags.tagsinuse 4065.261181 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 170177272 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 343775660 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 343775660 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 113315079 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 113315079 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 53882541 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18027.042954 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18027.080637 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18027.080637 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 9788 # number of replacements
system.cpu.icache.tags.tagsinuse 983.198764 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 516597066 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 1033228695 # Number of tag accesses
system.cpu.icache.tags.data_accesses 1033228695 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 516597066 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 516597066 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 516597066 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 110394 # number of replacements
system.cpu.l2cache.tags.tagsinuse 27252.086651 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1747015 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 18853226 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 18853226 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 1065708 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 1065708 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 9751 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 2146 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2145 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 795385 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 1162038 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 9788 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1710558000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 41576 # Transaction distribution
system.membus.trans_dist::WritebackDirty 96330 # Transaction distribution
system.membus.trans_dist::CleanEvict 11920 # Transaction distribution
sim_ticks 481957625500 # Number of ticks simulated
final_tick 481957625500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 86883 # Simulator instruction rate (inst/s)
-host_op_rate 160778 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 50643012 # Simulator tick rate (ticks/s)
-host_mem_usage 314272 # Number of bytes of host memory used
-host_seconds 9516.76 # Real time elapsed on the host
+host_inst_rate 134289 # Simulator instruction rate (inst/s)
+host_op_rate 248503 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 78275315 # Simulator tick rate (ticks/s)
+host_mem_usage 362988 # Number of bytes of host memory used
+host_seconds 6157.21 # Real time elapsed on the host
sim_insts 826847303 # Number of instructions simulated
sim_ops 1530082520 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 154624 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24604096 # Number of bytes read from this memory
system.physmem.bytes_read::total 24758720 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 84631916750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 297786504 # Number of BP lookups
system.cpu.branchPred.condPredicted 297786504 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 23596621 # Number of conditional branches incorrect
system.cpu.branchPred.indirectMisses 109794733 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 11576014 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states
system.cpu.workload.num_syscalls 551 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 481957625500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 963915252 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.cc_regfile_writes 419954937 # number of cc regfile writes
system.cpu.misc_regfile_reads 1064369445 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 2545945 # number of replacements
system.cpu.dcache.tags.tagsinuse 4088.303608 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 421067815 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 851394195 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 851394195 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 272697526 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 272697526 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 148366944 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22452.333150 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22452.333150 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22452.333150 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 4014 # number of replacements
system.cpu.icache.tags.tagsinuse 1083.903563 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 216343916 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.841797 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 432715084 # Number of tag accesses
system.cpu.icache.tags.data_accesses 432715084 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 216344175 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 216344175 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 216344175 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 32980.378890 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32980.378890 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 32980.378890 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 355161 # number of replacements
system.cpu.l2cache.tags.tagsinuse 29604.694298 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3909300 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987732 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 41979246 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 41979246 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 2337968 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 2337968 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 3923 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 2834 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2829 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 5 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 1773348 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 2632888 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 4014 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3825891006 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 180179 # Transaction distribution
system.membus.trans_dist::WritebackDirty 294920 # Transaction distribution
system.membus.trans_dist::CleanEvict 57436 # Transaction distribution
sim_ticks 885772926000 # Number of ticks simulated
final_tick 885772926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 772132 # Simulator instruction rate (inst/s)
-host_op_rate 1428832 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 827158459 # Simulator tick rate (ticks/s)
-host_mem_usage 268696 # Number of bytes of host memory used
-host_seconds 1070.86 # Real time elapsed on the host
+host_inst_rate 1531547 # Simulator instruction rate (inst/s)
+host_op_rate 2834130 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1640692833 # Simulator tick rate (ticks/s)
+host_mem_usage 315956 # Number of bytes of host memory used
+host_seconds 539.88 # Real time elapsed on the host
sim_insts 826847304 # Number of instructions simulated
sim_ops 1530082521 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 8546485088 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 2285527276 # Number of bytes read from this memory
system.physmem.bytes_read::total 10832012364 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 9648618554 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3700005559 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13348624112 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states
system.cpu.workload.num_syscalls 551 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 885772926000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 1771545853 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1530082521 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 1452393978 # Transaction distribution
system.membus.trans_dist::ReadResp 1452393978 # Transaction distribution
system.membus.trans_dist::WriteReq 149158211 # Transaction distribution
sim_ticks 1650501252500 # Number of ticks simulated
final_tick 1650501252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 482495 # Simulator instruction rate (inst/s)
-host_op_rate 892859 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 963127288 # Simulator tick rate (ticks/s)
-host_mem_usage 277668 # Number of bytes of host memory used
-host_seconds 1713.69 # Real time elapsed on the host
+host_inst_rate 943240 # Simulator instruction rate (inst/s)
+host_op_rate 1745467 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1882837072 # Simulator tick rate (ticks/s)
+host_mem_usage 326104 # Number of bytes of host memory used
+host_seconds 876.60 # Real time elapsed on the host
sim_insts 826847304 # Number of instructions simulated
sim_ops 1530082521 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 115776 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24258944 # Number of bytes read from this memory
system.physmem.bytes_read::total 24374720 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 70146 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 14697925 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 26137495 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states
system.cpu.workload.num_syscalls 551 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 1650501252500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 3301002505 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1530082521 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 2517016 # number of replacements
system.cpu.dcache.tags.tagsinuse 4086.386474 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 530720441 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1069004218 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1069004218 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 382353600 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 382353600 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 148366841 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 1253 # number of replacements
system.cpu.icache.tags.tagsinuse 881.361687 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1068307822 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 2136624086 # Number of tag accesses
system.cpu.icache.tags.data_accesses 2136624086 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 1068307822 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1068307822 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1068307822 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 348438 # number of replacements
system.cpu.l2cache.tags.tagsinuse 29288.734166 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3851952 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 41509728 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 41509728 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 2325221 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 2325221 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1253 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 1732556 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 2618429 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3781668000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 174499 # Transaction distribution
system.membus.trans_dist::WritebackDirty 293207 # Transaction distribution
system.membus.trans_dist::CleanEvict 53507 # Transaction distribution
sim_ticks 223532962500 # Number of ticks simulated
final_tick 223532962500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 234970 # Simulator instruction rate (inst/s)
-host_op_rate 234970 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 131748654 # Simulator tick rate (ticks/s)
-host_mem_usage 255168 # Number of bytes of host memory used
-host_seconds 1696.66 # Real time elapsed on the host
+host_inst_rate 488740 # Simulator instruction rate (inst/s)
+host_op_rate 488740 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 274038351 # Simulator tick rate (ticks/s)
+host_mem_usage 302272 # Number of bytes of host memory used
+host_seconds 815.70 # Real time elapsed on the host
sim_insts 398664665 # Number of instructions simulated
sim_ops 398664665 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 249088 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory
system.physmem.bytes_read::total 503680 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1017823750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 45898041 # Number of BP lookups
system.cpu.branchPred.condPredicted 26691639 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 566044 # Number of conditional branches incorrect
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 223532962500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 447065925 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class_0::total 398664665 # Class of committed instruction
system.cpu.tickCycles 443407678 # Number of cycles that the object actually ticked
system.cpu.idleCycles 3658247 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 771 # number of replacements
system.cpu.dcache.tags.tagsinuse 3291.617120 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 167826980 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 335672353 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 335672353 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 94312181 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 94312181 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 73514799 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 74596.158463 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74596.158463 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 74596.158463 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 3190 # number of replacements
system.cpu.icache.tags.tagsinuse 1919.630000 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 96785699 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 193586902 # Number of tag accesses
system.cpu.icache.tags.data_accesses 193586902 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 96785699 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 96785699 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 96785699 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 60281.830495 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60281.830495 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 60281.830495 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 4421.902302 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 4798 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160828 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 114820 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 114820 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 654 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 654 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 3190 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 6135 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 654 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 3190 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 6247999 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 4733 # Transaction distribution
system.membus.trans_dist::ReadExReq 3137 # Transaction distribution
system.membus.trans_dist::ReadExResp 3137 # Transaction distribution
sim_ticks 64188759000 # Number of ticks simulated
final_tick 64188759000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 189145 # Simulator instruction rate (inst/s)
-host_op_rate 189145 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 32326376 # Simulator tick rate (ticks/s)
-host_mem_usage 256256 # Number of bytes of host memory used
-host_seconds 1985.65 # Real time elapsed on the host
+host_inst_rate 392159 # Simulator instruction rate (inst/s)
+host_op_rate 392159 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 67023124 # Simulator tick rate (ticks/s)
+host_mem_usage 303292 # Number of bytes of host memory used
+host_seconds 957.71 # Real time elapsed on the host
sim_insts 375574794 # Number of instructions simulated
sim_ops 375574794 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 220800 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 255360 # Number of bytes read from this memory
system.physmem.bytes_read::total 476160 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 684265000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 47858697 # Number of BP lookups
system.cpu.branchPred.condPredicted 27887013 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 573168 # Number of conditional branches incorrect
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 64188759000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 128377521 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fp_regfile_writes 102074619 # number of floating regfile writes
system.cpu.misc_regfile_reads 350572 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 776 # number of replacements
system.cpu.dcache.tags.tagsinuse 3292.009184 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 152572889 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.830078 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 305192990 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 305192990 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 79071847 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 79071847 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 73501036 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 77606.321839 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77606.321839 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 77606.321839 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 2132 # number of replacements
system.cpu.icache.tags.tagsinuse 1831.246133 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 46954666 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.941406 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 93924682 # Number of tag accesses
system.cpu.icache.tags.data_accesses 93924682 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 46954666 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 46954666 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 46954666 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 67833.374384 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67833.374384 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 67833.374384 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 4001.708243 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3078 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.147919 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 97187 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 97187 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 655 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 655 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 2132 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 5048 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 655 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 2132 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 6264000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 4312 # Transaction distribution
system.membus.trans_dist::ReadExReq 3128 # Transaction distribution
system.membus.trans_dist::ReadExResp 3128 # Transaction distribution
sim_ticks 567385356500 # Number of ticks simulated
final_tick 567385356500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 857568 # Simulator instruction rate (inst/s)
-host_op_rate 857568 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1220503073 # Simulator tick rate (ticks/s)
-host_mem_usage 253440 # Number of bytes of host memory used
-host_seconds 464.88 # Real time elapsed on the host
+host_inst_rate 1687815 # Simulator instruction rate (inst/s)
+host_op_rate 1687815 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2402123351 # Simulator tick rate (ticks/s)
+host_mem_usage 300208 # Number of bytes of host memory used
+host_seconds 236.20 # Real time elapsed on the host
sim_insts 398664609 # Number of instructions simulated
sim_ops 398664609 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory
system.physmem.bytes_read::total 459136 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 361518 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 447696 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 809214 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 567385356500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 1134770713 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 398664665 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 764 # number of replacements
system.cpu.dcache.tags.tagsinuse 3288.807028 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.827148 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 336554592 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 336554592 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 58846.218690 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58846.218690 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 58846.218690 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 1769 # number of replacements
system.cpu.icache.tags.tagsinuse 1795.084430 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.929688 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 797333005 # Number of tag accesses
system.cpu.icache.tags.data_accesses 797333005 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 54762.319630 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54762.319630 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 54762.319630 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 3772.330397 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2561 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.139343 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 90632 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 90632 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 649 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 649 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1769 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 649 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 1769 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 6228000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 4032 # Transaction distribution
system.membus.trans_dist::ReadExReq 3142 # Transaction distribution
system.membus.trans_dist::ReadExResp 3142 # Transaction distribution
sim_ticks 211714953000 # Number of ticks simulated
final_tick 211714953000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 119593 # Simulator instruction rate (inst/s)
-host_op_rate 143584 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 92732901 # Simulator tick rate (ticks/s)
-host_mem_usage 275300 # Number of bytes of host memory used
-host_seconds 2283.06 # Real time elapsed on the host
+host_inst_rate 271910 # Simulator instruction rate (inst/s)
+host_op_rate 326458 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 210840466 # Simulator tick rate (ticks/s)
+host_mem_usage 322892 # Number of bytes of host memory used
+host_seconds 1004.15 # Real time elapsed on the host
sim_insts 273037857 # Number of instructions simulated
sim_ops 327812214 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 219072 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 266432 # Number of bytes read from this memory
system.physmem.bytes_read::total 485504 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1682763000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 32413931 # Number of BP lookups
system.cpu.branchPred.condPredicted 16919661 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 738142 # Number of conditional branches incorrect
system.cpu.branchPred.indirectMisses 39407 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 128263 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 211714953000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 423429906 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class_0::total 327812214 # Class of committed instruction
system.cpu.tickCycles 420106568 # Number of cycles that the object actually ticked
system.cpu.idleCycles 3323338 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 1355 # number of replacements
system.cpu.dcache.tags.tagsinuse 3085.570959 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 168654881 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 337328856 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 337328856 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 86522107 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 86522107 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 82047451 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 73133.399867 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73191.378546 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 73191.378546 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 38168 # number of replacements
system.cpu.icache.tags.tagsinuse 1923.744161 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 69641436 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 139403186 # Number of tag accesses
system.cpu.icache.tags.data_accesses 139403186 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 69641436 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 69641436 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 69641436 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 17888.642314 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17888.642314 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 17888.642314 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 4199.701287 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 60529 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172363 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 561366 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 561366 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 1010 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 1010 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 23251 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 41746 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 38168 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 6789457 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 4732 # Transaction distribution
system.membus.trans_dist::ReadExReq 2854 # Transaction distribution
system.membus.trans_dist::ReadExResp 2854 # Transaction distribution
sim_ticks 111753553500 # Number of ticks simulated
final_tick 111753553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 210028 # Simulator instruction rate (inst/s)
-host_op_rate 252162 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 85964130 # Simulator tick rate (ticks/s)
-host_mem_usage 334160 # Number of bytes of host memory used
-host_seconds 1300.00 # Real time elapsed on the host
+host_inst_rate 201687 # Simulator instruction rate (inst/s)
+host_op_rate 242148 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 82550264 # Simulator tick rate (ticks/s)
+host_mem_usage 334820 # Number of bytes of host memory used
+host_seconds 1353.76 # Real time elapsed on the host
sim_insts 273037220 # Number of instructions simulated
sim_ops 327811602 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 620544 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 4626112 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher 168832 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 12405217621 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 35971731 # Number of BP lookups
system.cpu.branchPred.condPredicted 19265386 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 984189 # Number of conditional branches incorrect
system.cpu.branchPred.indirectMisses 43901 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 128855 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 111753553500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 223507108 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.cc_regfile_writes 80060950 # number of cc regfile writes
system.cpu.misc_regfile_reads 1056766060 # number of misc regfile reads
system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 1542955 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.836799 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 162076726 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 333528119 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 333528119 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 81065236 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 81065236 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 80920030 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11098.570877 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11098.942385 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11098.942385 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 726201 # number of replacements
system.cpu.icache.tags.tagsinuse 511.803602 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 81470529 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 165133375 # Number of tag accesses
system.cpu.icache.tags.data_accesses 165133375 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 81470529 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 81470529 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 81470529 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 8406.318013 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8406.318013 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 8406.318013 # average overall mshr miss latency
+system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.prefetcher.num_hwpf_issued 402434 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 402547 # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit 102 # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage 28085 # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 5603.177963 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3041133 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.381653 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 69530063 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 69530063 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 968360 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 968360 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1046226 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 130262 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 52910 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 77352 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 2049447 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 968360 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 1300796 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 2315538337 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 83887 # Transaction distribution
system.membus.trans_dist::UpgradeReq 13 # Transaction distribution
system.membus.trans_dist::ReadExReq 730 # Transaction distribution
sim_ticks 201717314000 # Number of ticks simulated
final_tick 201717314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1495302 # Simulator instruction rate (inst/s)
-host_op_rate 1795276 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1104713261 # Simulator tick rate (ticks/s)
-host_mem_usage 309028 # Number of bytes of host memory used
-host_seconds 182.60 # Real time elapsed on the host
+host_inst_rate 1421524 # Simulator instruction rate (inst/s)
+host_op_rate 1706697 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1050207028 # Simulator tick rate (ticks/s)
+host_mem_usage 310740 # Number of bytes of host memory used
+host_seconds 192.07 # Real time elapsed on the host
sim_insts 273037595 # Number of instructions simulated
sim_ops 327811950 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 1394641096 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 480709216 # Number of bytes read from this memory
system.physmem.bytes_read::total 1875350312 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 6913839315 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4366293411 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11280132726 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 201717314000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 403434629 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 327812145 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 434895828 # Transaction distribution
system.membus.trans_dist::ReadResp 434906723 # Transaction distribution
system.membus.trans_dist::WriteReq 82052672 # Transaction distribution
sim_ticks 517291025500 # Number of ticks simulated
final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 977708 # Simulator instruction rate (inst/s)
-host_op_rate 1173775 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1854370201 # Simulator tick rate (ticks/s)
-host_mem_usage 319164 # Number of bytes of host memory used
-host_seconds 278.96 # Real time elapsed on the host
+host_inst_rate 968617 # Simulator instruction rate (inst/s)
+host_op_rate 1162861 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1837127354 # Simulator tick rate (ticks/s)
+host_mem_usage 320856 # Number of bytes of host memory used
+host_seconds 281.58 # Real time elapsed on the host
sim_insts 272739286 # Number of instructions simulated
sim_ops 327433744 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory
system.physmem.bytes_read::total 437248 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 322666 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 522599 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 845265 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 517291025500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 1034582051 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 327812214 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 1332 # number of replacements
system.cpu.dcache.tags.tagsinuse 3078.335714 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 13796 # number of replacements
system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 697336309 # Number of tag accesses
system.cpu.icache.tags.data_accesses 697336309 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 348644750 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 348644750 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 348644750 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 3487.622109 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 228106 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 228106 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 998 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 998 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 6212 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 13796 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 3976 # Transaction distribution
system.membus.trans_dist::ReadExReq 2856 # Transaction distribution
system.membus.trans_dist::ReadExResp 2856 # Transaction distribution
sim_ticks 504258263000 # Number of ticks simulated
final_tick 504258263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 254365 # Simulator instruction rate (inst/s)
-host_op_rate 254365 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 138099861 # Simulator tick rate (ticks/s)
-host_mem_usage 257972 # Number of bytes of host memory used
-host_seconds 3651.40 # Real time elapsed on the host
+host_inst_rate 532728 # Simulator instruction rate (inst/s)
+host_op_rate 532728 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 289228716 # Simulator tick rate (ticks/s)
+host_mem_usage 306284 # Number of bytes of host memory used
+host_seconds 1743.46 # Real time elapsed on the host
sim_insts 928789150 # Number of instructions simulated
sim_ops 928789150 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 185088 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 18520000 # Number of bytes read from this memory
system.physmem.bytes_read::total 18705088 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 138643034750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 123840342 # Number of BP lookups
system.cpu.branchPred.condPredicted 79869322 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 685088 # Number of conditional branches incorrect
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 37 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 504258263000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 1008516526 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class_0::total 928789150 # Class of committed instruction
system.cpu.tickCycles 957154131 # Number of cycles that the object actually ticked
system.cpu.idleCycles 51362395 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 776530 # number of replacements
system.cpu.dcache.tags.tagsinuse 4092.342308 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 321596153 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 645671096 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 645671096 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 223432106 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 223432106 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 98164047 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 38186.098080 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38186.098080 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 38186.098080 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 10567 # number of replacements
system.cpu.icache.tags.tagsinuse 1686.158478 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 285751480 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.850586 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 571539889 # Number of tag accesses
system.cpu.icache.tags.data_accesses 571539889 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 285751480 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 285751480 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 285751480 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 27623.192526 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27623.192526 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 27623.192526 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 259940 # number of replacements
system.cpu.l2cache.tags.tagsinuse 32579.649991 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1218214 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 13001951 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 13001951 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 88489 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 88489 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 10567 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 2081 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2081 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 723924 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 155172 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 10567 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1170939499 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 225622 # Transaction distribution
system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution
system.membus.trans_dist::CleanEvict 191176 # Transaction distribution
sim_ticks 174766258500 # Number of ticks simulated
final_tick 174766258500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 186758 # Simulator instruction rate (inst/s)
-host_op_rate 186758 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 38746139 # Simulator tick rate (ticks/s)
-host_mem_usage 259692 # Number of bytes of host memory used
-host_seconds 4510.55 # Real time elapsed on the host
+host_inst_rate 383088 # Simulator instruction rate (inst/s)
+host_op_rate 383088 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 79477968 # Simulator tick rate (ticks/s)
+host_mem_usage 307308 # Number of bytes of host memory used
+host_seconds 2198.93 # Real time elapsed on the host
sim_insts 842382029 # Number of instructions simulated
sim_ops 842382029 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 174016 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 18524608 # Number of bytes read from this memory
system.physmem.bytes_read::total 18698624 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 87762226750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 129267026 # Number of BP lookups
system.cpu.branchPred.condPredicted 83048450 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 145225 # Number of conditional branches incorrect
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 37 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 174766258500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 349532518 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fp_regfile_writes 24680531 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 776668 # number of replacements
system.cpu.dcache.tags.tagsinuse 4091.068449 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 273851879 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 553379090 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 553379090 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 176443243 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 176443243 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 97408623 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 38280.101282 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38280.101282 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 38280.101282 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 4617 # number of replacements
system.cpu.icache.tags.tagsinuse 1647.904441 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 116209358 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.832520 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 232441538 # Number of tag accesses
system.cpu.icache.tags.data_accesses 232441538 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 116209358 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 116209358 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 116209358 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 41748.299858 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41748.299858 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 41748.299858 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 259794 # number of replacements
system.cpu.l2cache.tags.tagsinuse 32576.626048 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1207042 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999084 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 12908126 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 12908126 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 88604 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 88604 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 4617 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 2003 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2003 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 718468 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 155286 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 4617 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1171146499 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 225541 # Transaction distribution
system.membus.trans_dist::WritebackDirty 66682 # Transaction distribution
system.membus.trans_dist::CleanEvict 191110 # Transaction distribution
sim_ticks 464394627000 # Number of ticks simulated
final_tick 464394627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1449486 # Simulator instruction rate (inst/s)
-host_op_rate 1449486 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 724900195 # Simulator tick rate (ticks/s)
-host_mem_usage 247720 # Number of bytes of host memory used
-host_seconds 640.63 # Real time elapsed on the host
+host_inst_rate 3142131 # Simulator instruction rate (inst/s)
+host_op_rate 3142131 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1571406745 # Simulator tick rate (ticks/s)
+host_mem_usage 294224 # Number of bytes of host memory used
+host_seconds 295.53 # Real time elapsed on the host
sim_insts 928587629 # Number of instructions simulated
sim_ops 928587629 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 464394627000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 3715156600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1657129778 # Number of bytes read from this memory
system.physmem.bytes_read::total 5372286378 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7999999104 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5156832357 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13156831461 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 464394627000 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 37 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 464394627000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 928789255 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 928789150 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 464394627000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 1166299747 # Transaction distribution
system.membus.trans_dist::ReadResp 1166299747 # Transaction distribution
system.membus.trans_dist::WriteReq 98301200 # Transaction distribution
sim_ticks 1288319411500 # Number of ticks simulated
final_tick 1288319411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 888638 # Simulator instruction rate (inst/s)
-host_op_rate 888638 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1232892743 # Simulator tick rate (ticks/s)
-host_mem_usage 256432 # Number of bytes of host memory used
-host_seconds 1044.96 # Real time elapsed on the host
+host_inst_rate 1791468 # Simulator instruction rate (inst/s)
+host_op_rate 1791468 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2485477121 # Simulator tick rate (ticks/s)
+host_mem_usage 303212 # Number of bytes of host memory used
+host_seconds 518.34 # Real time elapsed on the host
sim_insts 928587629 # Number of instructions simulated
sim_ops 928587629 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 137024 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 18511872 # Number of bytes read from this memory
system.physmem.bytes_read::total 18648896 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 106359 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 14369008 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 17787986 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 37 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 1288319411500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 2576638823 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 928789150 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 776432 # number of replacements
system.cpu.dcache.tags.tagsinuse 4094.180330 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 672404122 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 236799083 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 236799083 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 98232186 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 30158.438903 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30158.438903 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 30158.438903 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 4618 # number of replacements
system.cpu.icache.tags.tagsinuse 1474.418872 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 928782983 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.756836 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 1857584470 # Number of tag accesses
system.cpu.icache.tags.data_accesses 1857584470 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 928782983 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 928782983 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 928782983 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 29014.023995 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29014.023995 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 29014.023995 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 258847 # number of replacements
system.cpu.l2cache.tags.tagsinuse 32654.651136 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1207020 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998962 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 12902563 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 12902563 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 88866 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 88866 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 4618 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 1718 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1718 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 155549 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 4618 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1170792000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 224741 # Transaction distribution
system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution
system.membus.trans_dist::CleanEvict 190447 # Transaction distribution
sim_ticks 489945697500 # Number of ticks simulated
final_tick 489945697500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 152136 # Simulator instruction rate (inst/s)
-host_op_rate 187299 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 116346895 # Simulator tick rate (ticks/s)
-host_mem_usage 275904 # Number of bytes of host memory used
-host_seconds 4211.08 # Real time elapsed on the host
+host_inst_rate 287135 # Simulator instruction rate (inst/s)
+host_op_rate 353501 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 219588415 # Simulator tick rate (ticks/s)
+host_mem_usage 322476 # Number of bytes of host memory used
+host_seconds 2231.20 # Real time elapsed on the host
sim_insts 640655085 # Number of instructions simulated
sim_ops 788730744 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 163712 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 18473856 # Number of bytes read from this memory
system.physmem.bytes_read::total 18637568 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 137017032000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 144591747 # Number of BP lookups
system.cpu.branchPred.condPredicted 96197702 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 97552 # Number of conditional branches incorrect
system.cpu.branchPred.indirectMisses 5518 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 8032 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 673 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 489945697500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 979891395 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class_0::total 788730744 # Class of committed instruction
system.cpu.tickCycles 924243701 # Number of cycles that the object actually ticked
system.cpu.idleCycles 55647694 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 778302 # number of replacements
system.cpu.dcache.tags.tagsinuse 4092.104499 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 378448234 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 759382252 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 759382252 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 249619506 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 249619506 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 128813766 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 37749.404609 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37744.983372 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 37744.983372 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 24859 # number of replacements
system.cpu.icache.tags.tagsinuse 1712.892625 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 252585994 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.855957 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 505251826 # Number of tag accesses
system.cpu.icache.tags.data_accesses 505251826 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 252585994 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 252585994 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 252585994 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 18416.469395 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18416.469395 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 18416.469395 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 258808 # number of replacements
system.cpu.l2cache.tags.tagsinuse 32560.749490 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1247790 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 13231738 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 13231738 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 88712 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 88712 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 23528 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 2027 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2012 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 739688 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 154810 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 24859 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1173610473 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 225121 # Transaction distribution
system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution
system.membus.trans_dist::CleanEvict 190682 # Transaction distribution
sim_ticks 326731324000 # Number of ticks simulated
final_tick 326731324000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 188423 # Simulator instruction rate (inst/s)
-host_op_rate 231974 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 96095829 # Simulator tick rate (ticks/s)
-host_mem_usage 319396 # Number of bytes of host memory used
-host_seconds 3400.06 # Real time elapsed on the host
+host_inst_rate 187465 # Simulator instruction rate (inst/s)
+host_op_rate 230795 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 95607340 # Simulator tick rate (ticks/s)
+host_mem_usage 320048 # Number of bytes of host memory used
+host_seconds 3417.43 # Real time elapsed on the host
sim_insts 640649299 # Number of instructions simulated
sim_ops 788724958 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 227072 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 47957824 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher 12822400 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 116279470187 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 174663372 # Number of BP lookups
system.cpu.branchPred.condPredicted 119116658 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 4015834 # Number of conditional branches incorrect
system.cpu.branchPred.indirectMisses 14567 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 1279491 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 673 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 326731324000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 653462649 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.cc_regfile_writes 369203387 # number of cc regfile writes
system.cpu.misc_regfile_reads 606830949 # number of misc regfile reads
system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 2756452 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.912722 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 371048240 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 751744798 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 751744798 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 243125245 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 243125245 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 127906950 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25018.715661 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25014.942917 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 25014.942917 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 1979880 # number of replacements
system.cpu.icache.tags.tagsinuse 510.626245 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 245759391 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 497466609 # Number of tag accesses
system.cpu.icache.tags.data_accesses 497466609 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 245759426 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 245759426 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 245759426 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7623.101721 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency
+system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.prefetcher.num_hwpf_issued 1350865 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 1355053 # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit 3664 # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage 4790051 # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 301370 # number of replacements
system.cpu.l2cache.tags.tagsinuse 16350.432681 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 7222107 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.612183 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 142338236 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 142338236 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 736314 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 736314 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 3356496 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 759527 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 116739 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 642788 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 4016692 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 802648 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 4000018 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 4135548979 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 951856 # Transaction distribution
system.membus.trans_dist::WritebackDirty 66334 # Transaction distribution
system.membus.trans_dist::CleanEvict 227102 # Transaction distribution
sim_ticks 395726778500 # Number of ticks simulated
final_tick 395726778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1843468 # Simulator instruction rate (inst/s)
-host_op_rate 2269552 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1138694237 # Simulator tick rate (ticks/s)
-host_mem_usage 309656 # Number of bytes of host memory used
-host_seconds 347.53 # Real time elapsed on the host
+host_inst_rate 1817115 # Simulator instruction rate (inst/s)
+host_op_rate 2237108 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1122416416 # Simulator tick rate (ticks/s)
+host_mem_usage 311336 # Number of bytes of host memory used
+host_seconds 352.57 # Real time elapsed on the host
sim_insts 640654411 # Number of instructions simulated
sim_ops 788730070 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 2573511596 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1144718516 # Number of bytes read from this memory
system.physmem.bytes_read::total 3718230112 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 6503253598 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4215120178 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10718373776 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 673 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 395726778500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 791453558 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 788730744 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 893703778 # Transaction distribution
system.membus.trans_dist::ReadResp 893709517 # Transaction distribution
system.membus.trans_dist::WriteReq 128951477 # Transaction distribution
sim_ticks 1045756396500 # Number of ticks simulated
final_tick 1045756396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1156934 # Simulator instruction rate (inst/s)
-host_op_rate 1421363 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1892295085 # Simulator tick rate (ticks/s)
-host_mem_usage 319640 # Number of bytes of host memory used
-host_seconds 552.64 # Real time elapsed on the host
+host_inst_rate 1150404 # Simulator instruction rate (inst/s)
+host_op_rate 1413341 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1881615398 # Simulator tick rate (ticks/s)
+host_mem_usage 320304 # Number of bytes of host memory used
+host_seconds 555.78 # Real time elapsed on the host
sim_insts 639366787 # Number of instructions simulated
sim_ops 785501035 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 112576 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 18470976 # Number of bytes read from this memory
system.physmem.bytes_read::total 18583552 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 107650 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 17662790 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 21815620 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 673 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 1045756396500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 2091512793 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 788730744 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 778046 # number of replacements
system.cpu.dcache.tags.tagsinuse 4093.549761 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 759367050 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 249613198 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 249613198 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 128882154 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 30085.763737 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30082.674885 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 30082.674885 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 8769 # number of replacements
system.cpu.icache.tags.tagsinuse 1391.385132 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 1286766008 # Number of tag accesses
system.cpu.icache.tags.data_accesses 1286766008 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 643367692 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 643367692 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 643367692 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 257772 # number of replacements
system.cpu.l2cache.tags.tagsinuse 32622.591915 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1218050 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999237 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 12984278 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 12984278 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 88995 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 88995 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 8752 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 1580 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1573 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 155093 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 8769 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 224275 # Transaction distribution
system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution
system.membus.trans_dist::CleanEvict 190094 # Transaction distribution
sim_ticks 59447065000 # Number of ticks simulated
final_tick 59447065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 249746 # Simulator instruction rate (inst/s)
-host_op_rate 249746 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 167876675 # Simulator tick rate (ticks/s)
-host_mem_usage 256840 # Number of bytes of host memory used
-host_seconds 354.11 # Real time elapsed on the host
+host_inst_rate 518825 # Simulator instruction rate (inst/s)
+host_op_rate 518825 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 348748418 # Simulator tick rate (ticks/s)
+host_mem_usage 305412 # Number of bytes of host memory used
+host_seconds 170.46 # Real time elapsed on the host
sim_insts 88438073 # Number of instructions simulated
sim_ops 88438073 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 432832 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10149568 # Number of bytes read from this memory
system.physmem.bytes_read::total 10582400 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 17372590500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 14660042 # Number of BP lookups
system.cpu.branchPred.condPredicted 9484785 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 381684 # Number of conditional branches incorrect
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 59447065000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 118894130 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class_0::total 88438073 # Class of committed instruction
system.cpu.tickCycles 91425505 # Number of cycles that the object actually ticked
system.cpu.idleCycles 27468625 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 200766 # number of replacements
system.cpu.dcache.tags.tagsinuse 4070.673886 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 34612040 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 70168000 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 70168000 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 20278781 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 20278781 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 14333259 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66662.777870 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66662.777870 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 66662.777870 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 152872 # number of replacements
system.cpu.icache.tags.tagsinuse 1932.382407 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 25430610 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 51325982 # Number of tag accesses
system.cpu.icache.tags.data_accesses 51325982 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 25430610 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 25430610 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 25430610 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 15032.300334 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15032.300334 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 15032.300334 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 133382 # number of replacements
system.cpu.l2cache.tags.tagsinuse 30429.048447 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 403995 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.979919 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 6016424 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 6016424 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 168424 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 168424 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 152872 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 4037 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4037 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 216218 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 282893 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 152872 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 307297491 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 34467 # Transaction distribution
system.membus.trans_dist::WritebackDirty 114469 # Transaction distribution
system.membus.trans_dist::CleanEvict 14990 # Transaction distribution
sim_ticks 22275010500 # Number of ticks simulated
final_tick 22275010500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 168633 # Simulator instruction rate (inst/s)
-host_op_rate 168633 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 47194651 # Simulator tick rate (ticks/s)
-host_mem_usage 258376 # Number of bytes of host memory used
-host_seconds 471.98 # Real time elapsed on the host
+host_inst_rate 330986 # Simulator instruction rate (inst/s)
+host_op_rate 330986 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 92631737 # Simulator tick rate (ticks/s)
+host_mem_usage 306452 # Number of bytes of host memory used
+host_seconds 240.47 # Real time elapsed on the host
sim_insts 79591756 # Number of instructions simulated
sim_ops 79591756 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 409984 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10153216 # Number of bytes read from this memory
system.physmem.bytes_read::total 10563200 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 9336732250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 16474744 # Number of BP lookups
system.cpu.branchPred.condPredicted 10670267 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 324432 # Number of conditional branches incorrect
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 22275010500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 44550025 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fp_regfile_writes 240367 # number of floating regfile writes
system.cpu.misc_regfile_reads 38271 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 201418 # number of replacements
system.cpu.dcache.tags.tagsinuse 4070.642288 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 33984828 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 70818146 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 70818146 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 20423642 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 20423642 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 13561123 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 84920.081912 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84920.081912 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 84920.081912 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 90292 # number of replacements
system.cpu.icache.tags.tagsinuse 1916.963164 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 13622372 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 27546828 # Number of tag accesses
system.cpu.icache.tags.data_accesses 27546828 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 13622372 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 13622372 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 13622372 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 17004.672897 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17004.672897 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 17004.672897 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 133082 # number of replacements
system.cpu.l2cache.tags.tagsinuse 30595.837110 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 280630 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.979401 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 5025086 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 5025086 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 168806 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 168806 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 90292 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 4045 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4045 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 154463 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 283225 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 90292 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 308281978 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 34270 # Transaction distribution
system.membus.trans_dist::WritebackDirty 114419 # Transaction distribution
system.membus.trans_dist::CleanEvict 14728 # Transaction distribution
sim_ticks 56802974500 # Number of ticks simulated
final_tick 56802974500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 132517 # Simulator instruction rate (inst/s)
-host_op_rate 169470 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 106146312 # Simulator tick rate (ticks/s)
-host_mem_usage 275700 # Number of bytes of host memory used
-host_seconds 535.14 # Real time elapsed on the host
+host_inst_rate 307576 # Simulator instruction rate (inst/s)
+host_op_rate 393344 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 246367888 # Simulator tick rate (ticks/s)
+host_mem_usage 323312 # Number of bytes of host memory used
+host_seconds 230.56 # Real time elapsed on the host
sim_insts 70915150 # Number of instructions simulated
sim_ops 90690106 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 285504 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7924672 # Number of bytes read from this memory
system.physmem.bytes_read::total 8210176 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 14394586000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 14774616 # Number of BP lookups
system.cpu.branchPred.condPredicted 9890616 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 339334 # Number of conditional branches incorrect
system.cpu.branchPred.indirectMisses 16551 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 24800 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 56802974500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 113605949 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class_0::total 90690106 # Class of committed instruction
system.cpu.tickCycles 95311103 # Number of cycles that the object actually ticked
system.cpu.idleCycles 18294846 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 156448 # number of replacements
system.cpu.dcache.tags.tagsinuse 4067.225830 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 42620314 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 86009120 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 86009120 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 22862903 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 22862903 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 19642172 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66407.785760 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67158.632524 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 67158.632524 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 43497 # number of replacements
system.cpu.icache.tags.tagsinuse 1852.676989 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 24844377 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 49825373 # Number of tag accesses
system.cpu.icache.tags.data_accesses 49825373 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 24844377 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 24844377 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 24844377 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 18874.923144 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18874.923144 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 18874.923144 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 96391 # number of replacements
system.cpu.l2cache.tags.tagsinuse 29870.997301 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 163417 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.950653 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 3420152 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 3420152 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 128389 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 128389 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 39908 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 3359 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3330 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 99049 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 214604 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 43497 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 240850431 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 26002 # Transaction distribution
system.membus.trans_dist::WritebackDirty 86215 # Transaction distribution
system.membus.trans_dist::CleanEvict 6912 # Transaction distribution
sim_ticks 33524756000 # Number of ticks simulated
final_tick 33524756000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 201547 # Simulator instruction rate (inst/s)
-host_op_rate 257754 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 95290096 # Simulator tick rate (ticks/s)
-host_mem_usage 324320 # Number of bytes of host memory used
-host_seconds 351.82 # Real time elapsed on the host
+host_inst_rate 198459 # Simulator instruction rate (inst/s)
+host_op_rate 253806 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 93830272 # Simulator tick rate (ticks/s)
+host_mem_usage 324968 # Number of bytes of host memory used
+host_seconds 357.29 # Real time elapsed on the host
sim_insts 70907652 # Number of instructions simulated
sim_ops 90682607 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 697984 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 2927552 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher 6172096 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 19085999585 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 17055826 # Number of BP lookups
system.cpu.branchPred.condPredicted 11447804 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 598855 # Number of conditional branches incorrect
system.cpu.branchPred.indirectMisses 37541 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 22230 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 33524756000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 67049513 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.cc_regfile_writes 38766867 # number of cc regfile writes
system.cpu.misc_regfile_reads 44112661 # number of misc regfile reads
system.cpu.misc_regfile_writes 31840 # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 486293 # number of replacements
system.cpu.dcache.tags.tagsinuse 510.756058 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 40330532 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 84456645 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 84456645 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 21406566 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 21406566 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 18832689 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13363.935265 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16209.256523 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16209.256523 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 325000 # number of replacements
system.cpu.icache.tags.tagsinuse 510.229072 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 22083387 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 45161716 # Number of tag accesses
system.cpu.icache.tags.data_accesses 45161716 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 22083387 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 22083387 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 22083387 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 10013.342037 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10013.342037 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 10013.342037 # average overall mshr miss latency
+system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.prefetcher.num_hwpf_issued 822902 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 826054 # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit 2760 # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage 78906 # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 128177 # number of replacements
system.cpu.l2cache.tags.tagsinuse 15989.063291 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1184574 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996338 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 25089114 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 25089114 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 260314 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 260314 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 470737 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 67456 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 56671 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 10785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 663721 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 357454 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 550979 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 730433064 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 144751 # Transaction distribution
system.membus.trans_dist::WritebackDirty 97140 # Transaction distribution
system.membus.trans_dist::CleanEvict 28117 # Transaction distribution
sim_ticks 1208777694500 # Number of ticks simulated
final_tick 1208777694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 239767 # Simulator instruction rate (inst/s)
-host_op_rate 239767 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 158688267 # Simulator tick rate (ticks/s)
-host_mem_usage 248760 # Number of bytes of host memory used
-host_seconds 7617.31 # Real time elapsed on the host
+host_inst_rate 530685 # Simulator instruction rate (inst/s)
+host_op_rate 530685 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 351230785 # Simulator tick rate (ticks/s)
+host_mem_usage 297332 # Number of bytes of host memory used
+host_seconds 3441.55 # Real time elapsed on the host
sim_insts 1826378509 # Number of instructions simulated
sim_ops 1826378509 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 61312 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 124970112 # Number of bytes read from this memory
system.physmem.bytes_read::total 125031424 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 587184084000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 246097965 # Number of BP lookups
system.cpu.branchPred.condPredicted 186356162 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 15588061 # Number of conditional branches incorrect
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 1208777694500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 2417555389 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class_0::total 1826378509 # Class of committed instruction
system.cpu.tickCycles 2075251932 # Number of cycles that the object actually ticked
system.cpu.idleCycles 342303457 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 9121974 # number of replacements
system.cpu.dcache.tags.tagsinuse 4080.726355 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 601538856 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1231275880 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1231275880 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 443056865 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 443056865 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 158481991 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28519.372194 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28519.372194 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 28519.372194 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 3 # number of replacements
system.cpu.icache.tags.tagsinuse 750.173547 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 597988654 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.466309 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 1195980182 # Number of tag accesses
system.cpu.icache.tags.data_accesses 1195980182 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 597988654 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 597988654 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 597988654 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 78684.759916 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78684.759916 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 78684.759916 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 1920891 # number of replacements
system.cpu.l2cache.tags.tagsinuse 30765.315888 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 14409692 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909576 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 149830076 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 149830076 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 3686603 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 3686603 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 1268 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1268 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 7239688 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 4708742 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 13689105000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 1173106 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1022139 # Transaction distribution
system.membus.trans_dist::CleanEvict 897726 # Transaction distribution
sim_ticks 669587683000 # Number of ticks simulated
final_tick 669587683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 147374 # Simulator instruction rate (inst/s)
-host_op_rate 147374 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 56841738 # Simulator tick rate (ticks/s)
-host_mem_usage 250296 # Number of bytes of host memory used
-host_seconds 11779.86 # Real time elapsed on the host
+host_inst_rate 268815 # Simulator instruction rate (inst/s)
+host_op_rate 268815 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 103681118 # Simulator tick rate (ticks/s)
+host_mem_usage 297332 # Number of bytes of host memory used
+host_seconds 6458.15 # Real time elapsed on the host
sim_insts 1736043781 # Number of instructions simulated
sim_ops 1736043781 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 60736 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 125489536 # Number of bytes read from this memory
system.physmem.bytes_read::total 125550272 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 434911888500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 409349783 # Number of BP lookups
system.cpu.branchPred.condPredicted 318159413 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 15962959 # Number of conditional branches incorrect
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 669587683000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 1339175367 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fp_regfile_writes 612 # number of floating regfile writes
system.cpu.misc_regfile_reads 25 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 9207202 # number of replacements
system.cpu.dcache.tags.tagsinuse 4087.451175 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 712346624 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1470154674 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1470154674 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 556848448 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 556848448 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 155498172 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 29017.117684 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29017.117684 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 29017.117684 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 1 # number of replacements
system.cpu.icache.tags.tagsinuse 753.790798 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 420611422 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.462891 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 841226771 # Number of tag accesses
system.cpu.icache.tags.data_accesses 841226771 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 420611422 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 420611422 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 420611422 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 84061.642782 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84061.642782 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 84061.642782 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 1929018 # number of replacements
system.cpu.l2cache.tags.tagsinuse 31408.626842 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 14580161 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909027 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 151193610 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 151193610 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 3727750 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 3727750 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 1275 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1275 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 7333042 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 4752054 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 13816947000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 1189304 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1024304 # Transaction distribution
system.membus.trans_dist::CleanEvict 903679 # Transaction distribution
sim_ticks 913189263000 # Number of ticks simulated
final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1469307 # Simulator instruction rate (inst/s)
-host_op_rate 1469307 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 737317476 # Simulator tick rate (ticks/s)
-host_mem_usage 238516 # Number of bytes of host memory used
-host_seconds 1238.53 # Real time elapsed on the host
+host_inst_rate 3169811 # Simulator instruction rate (inst/s)
+host_op_rate 3169811 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1590652371 # Simulator tick rate (ticks/s)
+host_mem_usage 285272 # Number of bytes of host memory used
+host_seconds 574.10 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 913189263000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 7305514036 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1974795935 # Number of bytes read from this memory
system.physmem.bytes_read::total 9280309971 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7999999926 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3068994956 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11068994882 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 913189263000 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 913189263000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 1826378527 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1826378509 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 913189263000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 2270974172 # Transaction distribution
system.membus.trans_dist::ReadResp 2270974172 # Transaction distribution
system.membus.trans_dist::WriteReq 160728502 # Transaction distribution
sim_ticks 2636719559500 # Number of ticks simulated
final_tick 2636719559500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 874013 # Simulator instruction rate (inst/s)
-host_op_rate 874013 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1266376533 # Simulator tick rate (ticks/s)
-host_mem_usage 247480 # Number of bytes of host memory used
-host_seconds 2082.10 # Real time elapsed on the host
+host_inst_rate 1821657 # Simulator instruction rate (inst/s)
+host_op_rate 1821657 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2639438336 # Simulator tick rate (ticks/s)
+host_mem_usage 295280 # Number of bytes of host memory used
+host_seconds 998.97 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 124892160 # Number of bytes read from this memory
system.physmem.bytes_read::total 124943488 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 19467 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 47366494 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 72191620 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 2636719559500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 5273439119 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1826378509 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 9107638 # number of replacements
system.cpu.dcache.tags.tagsinuse 4079.293901 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1219760064 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1219760064 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22494.942017 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22494.942017 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22494.942017 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 1 # number of replacements
system.cpu.icache.tags.tagsinuse 612.605858 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.391113 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 3652757822 # Number of tag accesses
system.cpu.icache.tags.data_accesses 3652757822 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 61044.264339 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61044.264339 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 61044.264339 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 1919525 # number of replacements
system.cpu.l2cache.tags.tagsinuse 30540.825713 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 14380256 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909180 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 149600037 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 149600037 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 3679426 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 3679426 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 1122 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1122 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 4701388 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 13667601000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 1169857 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1021962 # Transaction distribution
system.membus.trans_dist::CleanEvict 896683 # Transaction distribution
sim_ticks 1116865668500 # Number of ticks simulated
final_tick 1116865668500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 243832 # Simulator instruction rate (inst/s)
-host_op_rate 262692 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 176313668 # Simulator tick rate (ticks/s)
-host_mem_usage 266900 # Number of bytes of host memory used
-host_seconds 6334.54 # Real time elapsed on the host
+host_inst_rate 380135 # Simulator instruction rate (inst/s)
+host_op_rate 409538 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 274873670 # Simulator tick rate (ticks/s)
+host_mem_usage 314372 # Number of bytes of host memory used
+host_seconds 4063.20 # Real time elapsed on the host
sim_insts 1544563088 # Number of instructions simulated
sim_ops 1664032481 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 130931712 # Number of bytes read from this memory
system.physmem.bytes_read::total 130981824 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 593987729250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 239639355 # Number of BP lookups
system.cpu.branchPred.condPredicted 186342486 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 14526193 # Number of conditional branches incorrect
system.cpu.branchPred.indirectMisses 307 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 164 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 1116865668500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 2233731337 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class_0::total 1664032481 # Class of committed instruction
system.cpu.tickCycles 1834123667 # Number of cycles that the object actually ticked
system.cpu.idleCycles 399607670 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 9221041 # number of replacements
system.cpu.dcache.tags.tagsinuse 4085.616095 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 624218928 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1276841941 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1276841941 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 453887732 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 453887732 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 170331073 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 29090.718934 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29090.723802 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 29090.723802 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 29 # number of replacements
system.cpu.icache.tags.tagsinuse 660.385482 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 465281510 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.385742 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 930565477 # Number of tag accesses
system.cpu.icache.tags.data_accesses 930565477 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 465281510 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 465281510 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 465281510 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75193.528694 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 2013919 # number of replacements
system.cpu.l2cache.tags.tagsinuse 31258.258362 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 14509191 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 151498004 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 151498004 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 3684567 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 3684567 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 29 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 1286 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1280 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 7335103 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 4734690 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 29 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 13837707995 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 1245432 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1050123 # Transaction distribution
system.membus.trans_dist::CleanEvict 962724 # Transaction distribution
sim_ticks 767803843500 # Number of ticks simulated
final_tick 767803843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 232866 # Simulator instruction rate (inst/s)
-host_op_rate 250878 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 115757951 # Simulator tick rate (ticks/s)
-host_mem_usage 355612 # Number of bytes of host memory used
-host_seconds 6632.84 # Real time elapsed on the host
+host_inst_rate 232978 # Simulator instruction rate (inst/s)
+host_op_rate 250999 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 115813638 # Simulator tick rate (ticks/s)
+host_mem_usage 356264 # Number of bytes of host memory used
+host_seconds 6629.65 # Real time elapsed on the host
sim_insts 1544563024 # Number of instructions simulated
sim_ops 1664032416 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 235320384 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher 63711040 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 576690946995 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 286292198 # Number of BP lookups
system.cpu.branchPred.condPredicted 223415085 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 14631198 # Number of conditional branches incorrect
system.cpu.branchPred.indirectMisses 1139 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 136 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 767803843500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 1535607688 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.cc_regfile_writes 551854660 # number of cc regfile writes
system.cpu.misc_regfile_reads 675853616 # number of misc regfile reads
system.cpu.misc_regfile_writes 124 # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 17003710 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.964650 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 638076364 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1335728390 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1335728390 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 469357603 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 469357603 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 168718615 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26316.087921 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26316.090373 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26316.090373 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 589 # number of replacements
system.cpu.icache.tags.tagsinuse 444.836642 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 656966815 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.949219 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 1313937945 # Number of tag accesses
system.cpu.icache.tags.data_accesses 1313937945 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 656966815 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 656966815 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 656966815 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency
+system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.prefetcher.num_hwpf_issued 11611376 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 11640224 # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit 19566 # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage 4656640 # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 4706089 # number of replacements
system.cpu.l2cache.tags.tagsinuse 16099.754607 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 22829126 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.921448 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 552242422 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 552242422 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 4833112 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 4833112 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 12149903 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 2918086 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2899299 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18787 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 14267664 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 6469008 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 12171187 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 25506339992 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 3696594 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1635896 # Transaction distribution
system.membus.trans_dist::CleanEvict 3001813 # Transaction distribution
sim_ticks 832017490500 # Number of ticks simulated
final_tick 832017490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2181717 # Simulator instruction rate (inst/s)
-host_op_rate 2350469 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1175236125 # Simulator tick rate (ticks/s)
-host_mem_usage 301652 # Number of bytes of host memory used
-host_seconds 707.96 # Real time elapsed on the host
+host_inst_rate 2178318 # Simulator instruction rate (inst/s)
+host_op_rate 2346807 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1173405208 # Simulator tick rate (ticks/s)
+host_mem_usage 302320 # Number of bytes of host memory used
+host_seconds 709.06 # Real time elapsed on the host
sim_insts 1544563042 # Number of instructions simulated
sim_ops 1664032434 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 6178262360 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1581387671 # Number of bytes read from this memory
system.physmem.bytes_read::total 7759650031 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7425640002 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2650840984 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10076480986 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 832017490500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 1664034982 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1664032481 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 1999474725 # Transaction distribution
system.membus.trans_dist::ReadResp 1999474786 # Transaction distribution
system.membus.trans_dist::WriteReq 172586047 # Transaction distribution
sim_ticks 2377029670500 # Number of ticks simulated
final_tick 2377029670500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1359798 # Simulator instruction rate (inst/s)
-host_op_rate 1465373 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2100575394 # Simulator tick rate (ticks/s)
-host_mem_usage 311664 # Number of bytes of host memory used
-host_seconds 1131.61 # Real time elapsed on the host
+host_inst_rate 1373046 # Simulator instruction rate (inst/s)
+host_op_rate 1479650 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2121040557 # Simulator tick rate (ticks/s)
+host_mem_usage 312336 # Number of bytes of host memory used
+host_seconds 1120.69 # Real time elapsed on the host
sim_insts 1538759602 # Number of instructions simulated
sim_ops 1658228915 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 124870272 # Number of bytes read from this memory
system.physmem.bytes_read::total 124909696 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 16585 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 52532063 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 80041838 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 2377029670500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 4754059341 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1664032481 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 9111140 # number of replacements
system.cpu.dcache.tags.tagsinuse 4083.741120 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22490.216928 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22490.221153 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22490.221153 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 7 # number of replacements
system.cpu.icache.tags.tagsinuse 515.144337 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.308105 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 3089131820 # Number of tag accesses
system.cpu.icache.tags.data_accesses 3089131820 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 1544564953 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1544564953 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1544564953 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 1919027 # number of replacements
system.cpu.l2cache.tags.tagsinuse 31012.105366 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 14386231 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 149644904 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 149644904 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 3681379 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 3681379 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 7 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 1063 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1063 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 4702506 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 1169580 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1021127 # Transaction distribution
system.membus.trans_dist::CleanEvict 897056 # Transaction distribution
sim_ticks 2846007227500 # Number of ticks simulated
final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 786137 # Simulator instruction rate (inst/s)
-host_op_rate 1224873 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 743780816 # Simulator tick rate (ticks/s)
-host_mem_usage 258352 # Number of bytes of host memory used
-host_seconds 3826.41 # Real time elapsed on the host
+host_inst_rate 1672243 # Simulator instruction rate (inst/s)
+host_op_rate 2605507 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1582143797 # Simulator tick rate (ticks/s)
+host_mem_usage 305608 # Number of bytes of host memory used
+host_seconds 1798.83 # Real time elapsed on the host
sim_insts 3008081022 # Number of instructions simulated
sim_ops 4686862596 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 32105863056 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5023868345 # Number of bytes read from this memory
system.physmem.bytes_read::total 37129731401 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 11281019509 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2307979078 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13588998587 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states
system.cpu.workload.num_syscalls 46 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 2846007227500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 5692014456 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 4686862596 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 5252417628 # Transaction distribution
system.membus.trans_dist::ReadResp 5252417628 # Transaction distribution
system.membus.trans_dist::WriteReq 438528338 # Transaction distribution
sim_ticks 5895947852500 # Number of ticks simulated
final_tick 5895947852500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 545612 # Simulator instruction rate (inst/s)
-host_op_rate 850113 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1069419451 # Simulator tick rate (ticks/s)
-host_mem_usage 268340 # Number of bytes of host memory used
-host_seconds 5513.22 # Real time elapsed on the host
+host_inst_rate 1001702 # Simulator instruction rate (inst/s)
+host_op_rate 1560742 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1963371956 # Simulator tick rate (ticks/s)
+host_mem_usage 316648 # Number of bytes of host memory used
+host_seconds 3002.97 # Real time elapsed on the host
sim_insts 3008081022 # Number of instructions simulated
sim_ops 4686862596 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 124876480 # Number of bytes read from this memory
system.physmem.bytes_read::total 124919680 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7327 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 21180052 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 32284237 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
system.cpu.workload.num_syscalls 46 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 5895947852500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 11791895705 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 4686862596 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 9108581 # number of replacements
system.cpu.dcache.tags.tagsinuse 4084.587762 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 10 # number of replacements
system.cpu.icache.tags.tagsinuse 555.751337 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 4013232207 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.324707 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 8026466439 # Number of tag accesses
system.cpu.icache.tags.data_accesses 8026466439 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 4013232207 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 4013232207 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 4013232207 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 1919169 # number of replacements
system.cpu.l2cache.tags.tagsinuse 31137.283983 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 14382005 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908905 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 149614323 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 149614323 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 3682716 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 3682716 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 10 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 1002 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1002 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 4705005 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 10 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 1169437 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1022289 # Transaction distribution
system.membus.trans_dist::CleanEvict 896090 # Transaction distribution
sim_ticks 51905634500 # Number of ticks simulated
final_tick 51905634500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 261291 # Simulator instruction rate (inst/s)
-host_op_rate 261291 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 147573427 # Simulator tick rate (ticks/s)
-host_mem_usage 252408 # Number of bytes of host memory used
-host_seconds 351.73 # Real time elapsed on the host
+host_inst_rate 509703 # Simulator instruction rate (inst/s)
+host_op_rate 509703 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 287873591 # Simulator tick rate (ticks/s)
+host_mem_usage 300976 # Number of bytes of host memory used
+host_seconds 180.31 # Real time elapsed on the host
sim_insts 91903089 # Number of instructions simulated
sim_ops 91903089 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 202816 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 137664 # Number of bytes read from this memory
system.physmem.bytes_read::total 340480 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1011440250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 11440185 # Number of BP lookups
system.cpu.branchPred.condPredicted 8207191 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 765027 # Number of conditional branches incorrect
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 51905634500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 103811269 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class_0::total 91903089 # Class of committed instruction
system.cpu.tickCycles 102098443 # Number of cycles that the object actually ticked
system.cpu.idleCycles 1712826 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 157 # number of replacements
system.cpu.dcache.tags.tagsinuse 1447.414267 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 26572424 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 53153936 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 53153936 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 20074229 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 20074229 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 6498195 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75493.273543 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75493.273543 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75493.273543 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 13853 # number of replacements
system.cpu.icache.tags.tagsinuse 1642.330146 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 22935687 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 45918830 # Number of tag accesses
system.cpu.icache.tags.data_accesses 45918830 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 22935687 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 22935687 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 22935687 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 24717.681269 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24717.681269 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 24717.681269 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 2479.710860 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 26619 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.111908 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 261876 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 261876 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 13853 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 16303 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 13853 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3345000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 3601 # Transaction distribution
system.membus.trans_dist::ReadExReq 1719 # Transaction distribution
system.membus.trans_dist::ReadExResp 1719 # Transaction distribution
sim_ticks 21909208500 # Number of ticks simulated
final_tick 21909208500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 161119 # Simulator instruction rate (inst/s)
-host_op_rate 161119 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 41933875 # Simulator tick rate (ticks/s)
-host_mem_usage 253948 # Number of bytes of host memory used
-host_seconds 522.47 # Real time elapsed on the host
+host_inst_rate 299674 # Simulator instruction rate (inst/s)
+host_op_rate 299674 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 77995222 # Simulator tick rate (ticks/s)
+host_mem_usage 302008 # Number of bytes of host memory used
+host_seconds 280.90 # Real time elapsed on the host
sim_insts 84179709 # Number of instructions simulated
sim_ops 84179709 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory
system.physmem.bytes_read::total 334528 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 632027000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 16102191 # Number of BP lookups
system.cpu.branchPred.condPredicted 11688099 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 930994 # Number of conditional branches incorrect
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 21909208500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 43818418 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fp_regfile_writes 6178143 # number of floating regfile writes
system.cpu.misc_regfile_reads 719113 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 158 # number of replacements
system.cpu.dcache.tags.tagsinuse 1457.375474 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 28588753 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.509521 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 57198843 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 57198843 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 22095651 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 22095651 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 6492632 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 78282.306150 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78282.306150 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 78282.306150 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 9515 # number of replacements
system.cpu.icache.tags.tagsinuse 1600.928709 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 15918297 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.946289 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 31876857 # Number of tag accesses
system.cpu.icache.tags.data_accesses 31876857 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 15918297 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 15918297 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 15918297 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 29396.018858 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29396.018858 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 29396.018858 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 2407.364249 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 18027 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109528 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 192294 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 192294 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 108 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 108 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 9515 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 11969 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 108 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 9515 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3367500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 3524 # Transaction distribution
system.membus.trans_dist::ReadExReq 1703 # Transaction distribution
system.membus.trans_dist::ReadExResp 1703 # Transaction distribution
sim_ticks 130382890500 # Number of ticks simulated
final_tick 130382890500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 181123 # Simulator instruction rate (inst/s)
-host_op_rate 190933 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 137045131 # Simulator tick rate (ticks/s)
-host_mem_usage 270196 # Number of bytes of host memory used
-host_seconds 951.39 # Real time elapsed on the host
+host_inst_rate 369340 # Simulator instruction rate (inst/s)
+host_op_rate 389344 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 279457902 # Simulator tick rate (ticks/s)
+host_mem_usage 317800 # Number of bytes of host memory used
+host_seconds 466.56 # Real time elapsed on the host
sim_insts 172317810 # Number of instructions simulated
sim_ops 181650743 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 138112 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory
system.physmem.bytes_read::total 247424 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1060850750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 49622074 # Number of BP lookups
system.cpu.branchPred.condPredicted 39447439 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 5514206 # Number of conditional branches incorrect
system.cpu.branchPred.indirectMisses 5775 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 40452 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 400 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 130382890500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 260765781 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class_0::total 181650743 # Class of committed instruction
system.cpu.tickCycles 254551967 # Number of cycles that the object actually ticked
system.cpu.idleCycles 6213814 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 42 # number of replacements
system.cpu.dcache.tags.tagsinuse 1378.689350 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 40754473 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 81515639 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 81515639 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 28346557 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 28346557 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 12362640 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 76115.193370 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76111.816676 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 76111.816676 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 2881 # number of replacements
system.cpu.icache.tags.tagsinuse 1423.942746 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 70779397 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.876953 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 141572827 # Number of tag accesses
system.cpu.icache.tags.data_accesses 141572827 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 70779397 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 70779397 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 70779397 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41418.448055 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 1999.548128 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 5178 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084930 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 76554 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 76554 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 2559 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 5389 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 2881 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 2723486 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 2775 # Transaction distribution
system.membus.trans_dist::ReadExReq 1091 # Transaction distribution
system.membus.trans_dist::ReadExResp 1091 # Transaction distribution
sim_ticks 84937723500 # Number of ticks simulated
final_tick 84937723500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 205804 # Simulator instruction rate (inst/s)
-host_op_rate 216952 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 101452217 # Simulator tick rate (ticks/s)
-host_mem_usage 314712 # Number of bytes of host memory used
-host_seconds 837.22 # Real time elapsed on the host
+host_inst_rate 205612 # Simulator instruction rate (inst/s)
+host_op_rate 216749 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 101357587 # Simulator tick rate (ticks/s)
+host_mem_usage 315376 # Number of bytes of host memory used
+host_seconds 838.00 # Real time elapsed on the host
sim_insts 172303022 # Number of instructions simulated
sim_ops 181635954 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 587328 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 132096 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher 70976 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 2138239588 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 85626366 # Number of BP lookups
system.cpu.branchPred.condPredicted 68177013 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 5935452 # Number of conditional branches incorrect
system.cpu.branchPred.indirectMisses 27943 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 40316 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 400 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 84937723500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 169875448 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.cc_regfile_writes 229512691 # number of cc regfile writes
system.cpu.misc_regfile_reads 57440840 # number of misc regfile reads
system.cpu.misc_regfile_writes 820036 # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 72581 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.413915 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 41031177 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 82360603 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 82360603 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 28644947 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 28644947 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 12341311 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 10129.083297 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10126.585295 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 10126.585295 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 53623 # number of replacements
system.cpu.icache.tags.tagsinuse 510.594536 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 78269055 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 156707315 # Number of tag accesses
system.cpu.icache.tags.data_accesses 156707315 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 78269055 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 78269055 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 78269055 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 19208.778853 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19208.778853 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 19208.778853 # average overall mshr miss latency
+system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.prefetcher.num_hwpf_issued 9269 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 9269 # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage 1371 # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 2141.370901 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 157591 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.179688 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 3955418 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 3955418 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 64698 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 64698 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 51033 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 11905 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3377 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 8528 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 118606 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 64698 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 61506 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 109644490 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 12116 # Transaction distribution
system.membus.trans_dist::ReadExReq 234 # Transaction distribution
system.membus.trans_dist::ReadExResp 234 # Transaction distribution
sim_ticks 103324153500 # Number of ticks simulated
final_tick 103324153500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 48808 # Simulator instruction rate (inst/s)
-host_op_rate 81806 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 38183996 # Simulator tick rate (ticks/s)
-host_mem_usage 302208 # Number of bytes of host memory used
-host_seconds 2705.95 # Real time elapsed on the host
+host_inst_rate 98344 # Simulator instruction rate (inst/s)
+host_op_rate 164833 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 76937982 # Simulator tick rate (ticks/s)
+host_mem_usage 350904 # Number of bytes of host memory used
+host_seconds 1342.95 # Real time elapsed on the host
sim_insts 132071192 # Number of instructions simulated
sim_ops 221363384 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 231488 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 130496 # Number of bytes read from this memory
system.physmem.bytes_read::total 361984 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1069805000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 40908032 # Number of BP lookups
system.cpu.branchPred.condPredicted 40908032 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 6741329 # Number of conditional branches incorrect
system.cpu.branchPred.indirectMisses 25447446 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 5035252 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states
system.cpu.workload.num_syscalls 400 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 103324153500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 206648308 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.cc_regfile_writes 65774990 # number of cc regfile writes
system.cpu.misc_regfile_reads 176892429 # number of misc regfile reads
system.cpu.misc_regfile_writes 1689 # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 72 # number of replacements
system.cpu.dcache.tags.tagsinuse 1525.498489 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 82766316 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.498291 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 165539971 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 165539971 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 62251936 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 62251936 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 20513707 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67741.214668 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 6515 # number of replacements
system.cpu.icache.tags.tagsinuse 1663.291735 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 41248897 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.968750 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 82532972 # Number of tag accesses
system.cpu.icache.tags.data_accesses 82532972 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 41248897 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 41248897 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 41248897 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 37852.238640 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37852.238640 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 37852.238640 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 2796.844278 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 11471 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.126801 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 146881 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 146881 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 18 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 18 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 6469 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 9600 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 18 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 6515 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3422499 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 4149 # Transaction distribution
system.membus.trans_dist::UpgradeReq 500 # Transaction distribution
system.membus.trans_dist::ReadExReq 1507 # Transaction distribution
sim_ticks 1869357999000 # Number of ticks simulated
final_tick 1869357999000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1770526 # Simulator instruction rate (inst/s)
-host_op_rate 1770526 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 50919239991 # Simulator tick rate (ticks/s)
-host_mem_usage 331076 # Number of bytes of host memory used
-host_seconds 36.71 # Real time elapsed on the host
+host_inst_rate 2674040 # Simulator instruction rate (inst/s)
+host_op_rate 2674039 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 76903724257 # Simulator tick rate (ticks/s)
+host_mem_usage 377772 # Number of bytes of host memory used
+host_seconds 24.31 # Real time elapsed on the host
sim_insts 64999904 # Number of instructions simulated
sim_ops 64999904 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.inst 758272 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 66535616 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 106112 # Number of bytes read from this memory
system.physmem.bw_total::cpu1.data 409946 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 40657620 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
+system.cpu0.numPwrStateTransitions 13588 # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples 6794 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean 271506704.857374 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev 434955692.191892 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10 6794 100.00% 100.00% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::min_value 21000 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total 6794 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON 24741446199 # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 1844616552801 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 3738722793 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.op_class::IprAccess 675558 1.37% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 49485886 # Class of executed instruction
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 1781367 # number of replacements
system.cpu0.dcache.tags.tagsinuse 506.187330 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 10705767 # Total number of references to valid blocks.
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 51822038 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 51822038 # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 6068885 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 6068885 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 4360085 # number of WriteReq hits
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks 633126 # number of writebacks
system.cpu0.dcache.writebacks::total 633126 # number of writebacks
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 618292 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.240644 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 48866947 # Total number of references to valid blocks.
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 50104825 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 50104825 # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 48866947 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 48866947 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 48866947 # number of demand (read+write) hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
+system.cpu1.numPwrStateTransitions 5407 # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples 2704 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean 688459933.247041 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev 437290592.854298 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10 2704 100.00% 100.00% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::min_value 400000 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::max_value 976035500 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total 2704 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON 7762339500 # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 1861595659500 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 3738296609 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 15525875 # Class of executed instruction
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements 201757 # number of replacements
system.cpu1.dcache.tags.tagsinuse 497.601962 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 4718401 # Total number of references to valid blocks.
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.601562 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 20020608 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 20020608 # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data 2632688 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 2632688 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 1954643 # number of WriteReq hits
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks 144536 # number of writebacks
system.cpu1.dcache.writebacks::total 144536 # number of writebacks
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements 380647 # number of replacements
system.cpu1.icache.tags.tagsinuse 453.133719 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 15144687 # Total number of references to valid blocks.
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 15907063 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 15907063 # Number of data accesses
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst 15144687 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 15144687 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 15144687 # number of demand (read+write) hits
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
+system.iobus.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 7628 # Transaction distribution
system.iobus.trans_dist::ReadResp 7628 # Transaction distribution
system.iobus.trans_dist::WriteReq 56140 # Transaction distribution
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2747818 # Cumulative packet size per connected master and slave (bytes)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 41699 # number of replacements
system.iocache.tags.tagsinuse 0.434096 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 375579 # Number of tag accesses
system.iocache.tags.data_accesses 375579 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses
system.iocache.ReadReq_misses::total 179 # number of ReadReq misses
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.writebacks::writebacks 41520 # number of writebacks
system.iocache.writebacks::total 41520 # number of writebacks
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 999922 # number of replacements
system.l2c.tags.tagsinuse 65337.856710 # Cycle average of tags in use
system.l2c.tags.total_refs 4259780 # Total number of references to valid blocks.
system.l2c.tags.occ_task_id_percent::1024 0.992584 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 46377199 # Number of tag accesses
system.l2c.tags.data_accesses 46377199 # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 777662 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 777662 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 721480 # number of WritebackClean hits
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 7449 # Transaction distribution
system.membus.trans_dist::ReadResp 948784 # Transaction distribution
system.membus.trans_dist::WriteReq 14588 # Transaction distribution
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 2204371 # Request fanout histogram
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 6035847 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 3018700 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 374456 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 1611 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 1521 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 90 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 7449 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2732152 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 7058663 # Request fanout histogram
+system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
+system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
+system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
+system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
+system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
+system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
+system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
+system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
---------- End Simulation Statistics ----------
sim_ticks 1829331993500 # Number of ticks simulated
final_tick 1829331993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1838030 # Simulator instruction rate (inst/s)
-host_op_rate 1838029 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 56003449171 # Simulator tick rate (ticks/s)
-host_mem_usage 325188 # Number of bytes of host memory used
-host_seconds 32.66 # Real time elapsed on the host
+host_inst_rate 2717372 # Simulator instruction rate (inst/s)
+host_op_rate 2717371 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 82796436895 # Simulator tick rate (ticks/s)
+host_mem_usage 372644 # Number of bytes of host memory used
+host_seconds 22.09 # Real time elapsed on the host
sim_insts 60038469 # Number of instructions simulated
sim_ops 60038469 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 66835072 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
system.physmem.bw_total::cpu.data 36535234 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 525 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 41054479 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.numPwrStateTransitions 12714 # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples 6357 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean 283043475.573698 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev 441371914.604153 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10 6357 100.00% 100.00% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::min_value 386000 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::total 6357 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::ON 30024619278 # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 1799307374222 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 3658670345 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 60050307 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 2042707 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 14038420 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 66369780 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 66369780 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 7807771 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 7807771 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 5848210 # number of WriteReq hits
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 833475 # number of writebacks
system.cpu.dcache.writebacks::total 833475 # number of writebacks
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 919603 # number of replacements
system.cpu.icache.tags.tagsinuse 511.215257 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 59130077 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 60970537 # Number of tag accesses
system.cpu.icache.tags.data_accesses 60970537 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 59130077 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 59130077 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 59130077 # number of demand (read+write) hits
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 919603 # number of writebacks
system.cpu.icache.writebacks::total 919603 # number of writebacks
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 992419 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65424.374401 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 4560132 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 48753652 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 48753652 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 833475 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 833475 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 919351 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 1449 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1449 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq 7184 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2666288 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
+system.iobus.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 7358 # Transaction distribution
system.iobus.trans_dist::ReadResp 7358 # Transaction distribution
system.iobus.trans_dist::WriteReq 51390 # Transaction distribution
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2707742 # Cumulative packet size per connected master and slave (bytes)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 41686 # number of replacements
system.iocache.tags.tagsinuse 1.225569 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 375534 # Number of tag accesses
system.iocache.tags.data_accesses 375534 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.writebacks::writebacks 41512 # number of writebacks
system.iocache.writebacks::total 41512 # number of writebacks
+system.membus.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 7184 # Transaction distribution
system.membus.trans_dist::ReadResp 948291 # Transaction distribution
system.membus.trans_dist::WriteReq 9838 # Transaction distribution
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 2149812 # Request fanout histogram
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
+system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
+system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
+system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
+system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
+system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
+system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
+system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
+system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
---------- End Simulation Statistics ----------
sim_ticks 1963612574000 # Number of ticks simulated
final_tick 1963612574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 993881 # Simulator instruction rate (inst/s)
-host_op_rate 993880 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 32036346352 # Simulator tick rate (ticks/s)
-host_mem_usage 331076 # Number of bytes of host memory used
-host_seconds 61.29 # Real time elapsed on the host
+host_inst_rate 1460699 # Simulator instruction rate (inst/s)
+host_op_rate 1460699 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 47083590827 # Simulator tick rate (ticks/s)
+host_mem_usage 378804 # Number of bytes of host memory used
+host_seconds 41.70 # Real time elapsed on the host
sim_insts 60918165 # Number of instructions simulated
sim_ops 60918165 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.inst 830784 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 24731648 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 28416 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 35445557750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
+system.cpu0.numPwrStateTransitions 13591 # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples 6796 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean 272307750.367863 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev 432682187.397928 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10 6796 100.00% 100.00% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::min_value 55000 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total 6796 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON 113009102500 # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 1850603471500 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 3925790590 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.op_class::IprAccess 735920 1.54% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 47764191 # Class of executed instruction
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 1179864 # number of replacements
system.cpu0.dcache.tags.tagsinuse 505.229406 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 11369687 # Total number of references to valid blocks.
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 51471495 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 51471495 # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 6411173 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 6411173 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 4657733 # number of WriteReq hits
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222006.821378 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87951.663231 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87951.663231 # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 698162 # number of replacements
system.cpu0.icache.tags.tagsinuse 508.148952 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 47065399 # Total number of references to valid blocks.
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 48462983 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 48462983 # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 47065399 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 47065399 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 47065399 # number of demand (read+write) hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
+system.cpu1.numPwrStateTransitions 5480 # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples 2740 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean 707616074.452555 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev 409900069.702285 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10 2740 100.00% 100.00% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::min_value 76500 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::max_value 974673500 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total 2740 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON 24744530000 # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 1938868044000 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 3927225148 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.op_class::IprAccess 364421 2.77% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 13165936 # Class of executed instruction
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements 166516 # number of replacements
system.cpu1.dcache.tags.tagsinuse 486.373615 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 4012325 # Total number of references to valid blocks.
system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 16958396 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 16958396 # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data 2257201 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 2257201 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 1642023 # number of WriteReq hits
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 226674.157303 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 6094.864048 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 6094.864048 # average overall mshr uncacheable latency
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements 316153 # number of replacements
system.cpu1.icache.tags.tagsinuse 445.936315 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 12849230 # Total number of references to valid blocks.
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 13482644 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 13482644 # Number of data accesses
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst 12849230 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 12849230 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 12849230 # number of demand (read+write) hits
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
+system.iobus.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 7373 # Transaction distribution
system.iobus.trans_dist::ReadResp 7373 # Transaction distribution
system.iobus.trans_dist::WriteReq 55610 # Transaction distribution
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 41948000 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 41694 # number of replacements
system.iocache.tags.tagsinuse 0.569299 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 375534 # Number of tag accesses
system.iocache.tags.data_accesses 375534 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
system.iocache.demand_avg_mshr_miss_latency::total 66900.242990 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66900.242990 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 66900.242990 # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 341504 # number of replacements
system.l2c.tags.tagsinuse 65213.029486 # Cycle average of tags in use
system.l2c.tags.total_refs 3680110 # Total number of references to valid blocks.
system.l2c.tags.occ_task_id_percent::1024 0.991867 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 35882279 # Number of tag accesses
system.l2c.tags.data_accesses 35882279 # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 792706 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 792706 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 747201 # number of WritebackClean hits
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 7199 # Transaction distribution
system.membus.trans_dist::ReadResp 292676 # Transaction distribution
system.membus.trans_dist::WriteReq 14058 # Transaction distribution
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
system.membus.respLayer2.occupancy 893117 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 4780466 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 2390280 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 355276 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 975 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 915 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 60 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2101675 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 14058 # Transaction distribution
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 281513896 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
+system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
+system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
+system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
+system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
+system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
+system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
+system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
---------- End Simulation Statistics ----------
sim_ticks 1941275996000 # Number of ticks simulated
final_tick 1941275996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 855166 # Simulator instruction rate (inst/s)
-host_op_rate 855166 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 29548473540 # Simulator tick rate (ticks/s)
-host_mem_usage 325188 # Number of bytes of host memory used
-host_seconds 65.70 # Real time elapsed on the host
+host_inst_rate 1512910 # Simulator instruction rate (inst/s)
+host_op_rate 1512909 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 52275426747 # Simulator tick rate (ticks/s)
+host_mem_usage 372644 # Number of bytes of host memory used
+host_seconds 37.14 # Real time elapsed on the host
sim_insts 56182685 # Number of instructions simulated
sim_ops 56182685 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 844800 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24856512 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 45029052250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.numPwrStateTransitions 12750 # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples 6375 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean 281084846.274667 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev 439246514.470007 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10 6374 99.98% 100.00% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::total 6375 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::ON 149360100999 # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 1791915895001 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 3882551992 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 953470 1.70% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 56194518 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 1390402 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.973391 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 14048961 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 63150419 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 63150419 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 7814383 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 7814383 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 5852265 # number of WriteReq hits
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220343.217893 # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92080.956401 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92080.956401 # average overall mshr uncacheable latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 928931 # number of replacements
system.cpu.icache.tags.tagsinuse 506.355616 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 55264917 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 57124121 # Number of tag accesses
system.cpu.icache.tags.data_accesses 57124121 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 55264917 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 55264917 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 55264917 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 13722.555459 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13722.555459 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13722.555459 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 336393 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65234.360001 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3930403 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 37812972 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 37812972 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 834944 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 834944 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 928709 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 1136 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1136 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2023294 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 9653 # Transaction distribution
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
+system.iobus.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
system.iobus.trans_dist::WriteReq 51205 # Transaction distribution
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 41685 # number of replacements
system.iocache.tags.tagsinuse 1.339384 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 375525 # Number of tag accesses
system.iocache.tags.data_accesses 375525 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
system.iocache.demand_avg_mshr_miss_latency::total 76175.143607 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76175.143607 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 76175.143607 # average overall mshr miss latency
+system.membus.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 6930 # Transaction distribution
system.membus.trans_dist::ReadResp 292274 # Transaction distribution
system.membus.trans_dist::WriteReq 9653 # Transaction distribution
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
system.membus.respLayer2.occupancy 887117 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
+system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
+system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
+system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
+system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
+system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
+system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
+system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
+system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states
---------- End Simulation Statistics ----------
sim_ticks 2783854535000 # Number of ticks simulated
final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1770003 # Simulator instruction rate (inst/s)
-host_op_rate 2154695 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 34512663529 # Simulator tick rate (ticks/s)
-host_mem_usage 623244 # Number of bytes of host memory used
-host_seconds 80.66 # Real time elapsed on the host
+host_inst_rate 1481321 # Simulator instruction rate (inst/s)
+host_op_rate 1803271 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 28883760858 # Simulator tick rate (ticks/s)
+host_mem_usage 624788 # Number of bytes of host memory used
+host_seconds 96.38 # Real time elapsed on the host
sim_insts 142771651 # Number of instructions simulated
sim_ops 173801592 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 1207012 # Number of bytes read from this memory
system.physmem.bw_total::cpu.data 3715122 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 7325048 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 10028 # Table walker walks requested
system.cpu.dtb.walker.walksShort 10028 # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walkWaitTime::samples 10028 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.hits 54650055 # DTB hits
system.cpu.dtb.misses 10028 # DTB misses
system.cpu.dtb.accesses 54660083 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 4762 # Table walker walks requested
system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency
system.cpu.itb.hits 147038166 # DTB hits
system.cpu.itb.misses 4762 # DTB misses
system.cpu.itb.accesses 147042928 # DTB accesses
+system.cpu.numPwrStateTransitions 6160 # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples 3080 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean 874939482.384091 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev 17329944773.080986 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::underflows 3002 97.47% 97.47% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10 72 2.34% 99.81% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::max_value 499984036900 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::total 3080 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::ON 89040929257 # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 2694813605743 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 5567712151 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 177218432 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 819392 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 53783872 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 219235088 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 219235088 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 30128801 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 30128801 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 22339792 # number of WriteReq hits
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 682017 # number of writebacks
system.cpu.dcache.writebacks::total 682017 # number of writebacks
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 1698998 # number of replacements
system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 145341757 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 148740789 # Number of tag accesses
system.cpu.icache.tags.data_accesses 148740789 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 145341757 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 145341757 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 145341757 # number of demand (read+write) hits
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 1698998 # number of writebacks
system.cpu.icache.writebacks::total 1698998 # number of writebacks
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 109913 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65155.314985 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 4524855 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 40578944 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 40578944 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 11218 # number of ReadReq hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq 67800 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2288329 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 5318737 # Request fanout histogram
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 30164 # Transaction distribution
system.iobus.trans_dist::ReadResp 30164 # Transaction distribution
system.iobus.trans_dist::WriteReq 59002 # Transaction distribution
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 36430 # number of replacements
system.iocache.tags.tagsinuse 0.909893 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328176 # Number of tag accesses
system.iocache.tags.data_accesses 328176 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses
system.iocache.ReadReq_misses::total 240 # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.writebacks::writebacks 36190 # number of writebacks
system.iocache.writebacks::total 36190 # number of writebacks
+system.membus.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 40087 # Transaction distribution
system.membus.trans_dist::ReadResp 74202 # Transaction distribution
system.membus.trans_dist::WriteReq 27546 # Transaction distribution
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 434821 # Request fanout histogram
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
---------- End Simulation Statistics ----------
sim_ticks 2802882797500 # Number of ticks simulated
final_tick 2802882797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1600792 # Simulator instruction rate (inst/s)
-host_op_rate 1950541 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 30558377305 # Simulator tick rate (ticks/s)
-host_mem_usage 639316 # Number of bytes of host memory used
-host_seconds 91.72 # Real time elapsed on the host
+host_inst_rate 1371763 # Simulator instruction rate (inst/s)
+host_op_rate 1671473 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 26186322462 # Simulator tick rate (ticks/s)
+host_mem_usage 640448 # Number of bytes of host memory used
+host_seconds 107.04 # Real time elapsed on the host
sim_insts 146828219 # Number of instructions simulated
sim_ops 178907974 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 1109284 # Number of bytes read from this memory
system.physmem.bw_total::cpu1.data 386000 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 7225250 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks 7964 # Table walker walks requested
system.cpu0.dtb.walker.walksShort 7964 # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walkWaitTime::samples 7964 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.hits 36730698 # DTB hits
system.cpu0.dtb.misses 7964 # DTB misses
system.cpu0.dtb.accesses 36738662 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks 3358 # Table walker walks requested
system.cpu0.itb.walker.walksShort 3358 # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.hits 97439155 # DTB hits
system.cpu0.itb.misses 3358 # DTB misses
system.cpu0.itb.accesses 97442513 # DTB accesses
+system.cpu0.numPwrStateTransitions 3932 # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples 1966 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean 1395773493.506104 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev 23114974453.612934 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows 1154 58.70% 58.70% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10 806 41.00% 99.69% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.75% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.80% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.20% 100.00% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::max_value 499983242180 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total 1966 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON 58792109267 # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 2744090688233 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 5605767562 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 116881836 # Class of executed instruction
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 693478 # number of replacements
system.cpu0.dcache.tags.tagsinuse 494.853458 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 35932315 # Total number of references to valid blocks.
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 74113673 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 74113673 # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 19108531 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 19108531 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 15690320 # number of WriteReq hits
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks 693478 # number of writebacks
system.cpu0.dcache.writebacks::total 693478 # number of writebacks
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 1109639 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 96331337 # Total number of references to valid blocks.
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 195993154 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 195993154 # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 96331337 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 96331337 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 96331337 # number of demand (read+write) hits
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks 1109639 # number of writebacks
system.cpu0.icache.writebacks::total 1109639 # number of writebacks
+system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements 249747 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 16131.550435 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 2729892 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.983276 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 59696130 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 59696130 # Number of data accesses
+system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10179 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4500 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 14679 # number of ReadReq hits
system.cpu0.toL2Bus.snoop_filter.tot_snoops 218415 # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 215401 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3014 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq 61410 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 1651731 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 28341 # Transaction distribution
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total 4318336 # Request fanout histogram
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks 3359 # Table walker walks requested
system.cpu1.dtb.walker.walksShort 3359 # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walkWaitTime::samples 3359 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.hits 19761166 # DTB hits
system.cpu1.dtb.misses 3359 # DTB misses
system.cpu1.dtb.accesses 19764525 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks 1734 # Table walker walks requested
system.cpu1.itb.walker.walksShort 1734 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walkWaitTime::samples 1734 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.hits 53671758 # DTB hits
system.cpu1.itb.misses 1734 # DTB misses
system.cpu1.itb.accesses 53673492 # DTB accesses
+system.cpu1.numPwrStateTransitions 5477 # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples 2739 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean 1011344723.290617 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev 25846310002.973743 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows 1957 71.45% 71.45% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10 777 28.37% 99.82% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.89% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::max_value 979984930372 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total 2739 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON 32809600407 # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 2770073197093 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 5605296470 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 65459659 # Class of executed instruction
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements 191946 # number of replacements
system.cpu1.dcache.tags.tagsinuse 472.736015 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 19503545 # Total number of references to valid blocks.
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 39752069 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 39752069 # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data 11858716 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 11858716 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 7397520 # number of WriteReq hits
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks 191946 # number of writebacks
system.cpu1.dcache.writebacks::total 191946 # number of writebacks
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements 523401 # number of replacements
system.cpu1.icache.tags.tagsinuse 499.711077 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 53148935 # Total number of references to valid blocks.
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 107869609 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 107869609 # Number of data accesses
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst 53148935 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 53148935 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 53148935 # number of demand (read+write) hits
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks 523401 # number of writebacks
system.cpu1.icache.writebacks::total 523401 # number of writebacks
+system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements 47503 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 15229.973296 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 1184897 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.915833 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 24502168 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 24502168 # Number of data accesses
+system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3621 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1918 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 5539 # number of ReadReq hits
system.cpu1.toL2Bus.snoop_filter.tot_snoops 166202 # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164239 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1963 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq 12750 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 709337 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total 1820541 # Request fanout histogram
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 30995 # Transaction distribution
system.iobus.trans_dist::ReadResp 30995 # Transaction distribution
system.iobus.trans_dist::WriteReq 59419 # Transaction distribution
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 36442 # number of replacements
system.iocache.tags.tagsinuse 14.586085 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328284 # Number of tag accesses
system.iocache.tags.data_accesses 328284 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.writebacks::writebacks 36190 # number of writebacks
system.iocache.writebacks::total 36190 # number of writebacks
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 107745 # number of replacements
system.l2c.tags.tagsinuse 62386.756535 # Cycle average of tags in use
system.l2c.tags.total_refs 243993 # Total number of references to valid blocks.
system.l2c.tags.occ_task_id_percent::1024 0.925491 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 5181909 # Number of tag accesses
system.l2c.tags.data_accesses 5181909 # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 225821 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 225821 # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data 557 # number of UpgradeReq hits
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 43996 # Transaction distribution
system.membus.trans_dist::ReadResp 75748 # Transaction distribution
system.membus.trans_dist::WriteReq 30846 # Transaction distribution
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 537521 # Request fanout histogram
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 863181 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 444499 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 128781 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 9832 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 9332 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 500 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 44000 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 301660 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 30846 # Transaction distribution
sim_ticks 2783854535000 # Number of ticks simulated
final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1638061 # Simulator instruction rate (inst/s)
-host_op_rate 1994077 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 31939974807 # Simulator tick rate (ticks/s)
-host_mem_usage 619068 # Number of bytes of host memory used
-host_seconds 87.16 # Real time elapsed on the host
+host_inst_rate 1429089 # Simulator instruction rate (inst/s)
+host_op_rate 1739687 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 27865307050 # Simulator tick rate (ticks/s)
+host_mem_usage 619548 # Number of bytes of host memory used
+host_seconds 99.90 # Real time elapsed on the host
sim_insts 142771651 # Number of instructions simulated
sim_ops 173801592 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 1207012 # Number of bytes read from this memory
system.physmem.bw_total::cpu.data 3715122 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 7325048 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 10028 # Table walker walks requested
system.cpu.dtb.walker.walksShort 10028 # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walkWaitTime::samples 10028 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.hits 54650055 # DTB hits
system.cpu.dtb.misses 10028 # DTB misses
system.cpu.dtb.accesses 54660083 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 4762 # Table walker walks requested
system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency
system.cpu.itb.hits 147038166 # DTB hits
system.cpu.itb.misses 4762 # DTB misses
system.cpu.itb.accesses 147042928 # DTB accesses
+system.cpu.numPwrStateTransitions 6160 # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples 3080 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean 874939482.384091 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev 17329944773.080986 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::underflows 3002 97.47% 97.47% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10 72 2.34% 99.81% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::max_value 499984036900 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::total 3080 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::ON 89040929257 # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 2694813605743 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 5567712151 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 177218432 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 819392 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 53783872 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 219235088 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 219235088 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 30128801 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 30128801 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 22339792 # number of WriteReq hits
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 682017 # number of writebacks
system.cpu.dcache.writebacks::total 682017 # number of writebacks
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 1698998 # number of replacements
system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 145341757 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 148740789 # Number of tag accesses
system.cpu.icache.tags.data_accesses 148740789 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 145341757 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 145341757 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 145341757 # number of demand (read+write) hits
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 1698998 # number of writebacks
system.cpu.icache.writebacks::total 1698998 # number of writebacks
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 109913 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65155.314985 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 4524855 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 40578944 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 40578944 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 11218 # number of ReadReq hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq 67800 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2288329 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 5318737 # Request fanout histogram
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 30164 # Transaction distribution
system.iobus.trans_dist::ReadResp 30164 # Transaction distribution
system.iobus.trans_dist::WriteReq 59002 # Transaction distribution
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 36430 # number of replacements
system.iocache.tags.tagsinuse 0.909893 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328176 # Number of tag accesses
system.iocache.tags.data_accesses 328176 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses
system.iocache.ReadReq_misses::total 240 # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.writebacks::writebacks 36190 # number of writebacks
system.iocache.writebacks::total 36190 # number of writebacks
+system.membus.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 40087 # Transaction distribution
system.membus.trans_dist::ReadResp 74202 # Transaction distribution
system.membus.trans_dist::WriteReq 27546 # Transaction distribution
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 434821 # Request fanout histogram
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states
---------- End Simulation Statistics ----------
sim_ticks 2869788970000 # Number of ticks simulated
final_tick 2869788970000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1069345 # Simulator instruction rate (inst/s)
-host_op_rate 1293434 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 23327334867 # Simulator tick rate (ticks/s)
-host_mem_usage 660408 # Number of bytes of host memory used
-host_seconds 123.02 # Real time elapsed on the host
+host_inst_rate 932940 # Simulator instruction rate (inst/s)
+host_op_rate 1128445 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 20351712140 # Simulator tick rate (ticks/s)
+host_mem_usage 661084 # Number of bytes of host memory used
+host_seconds 141.01 # Real time elapsed on the host
sim_insts 131553574 # Number of instructions simulated
sim_ops 159121622 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 1162532 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 32266568364 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks 7943 # Table walker walks requested
system.cpu0.dtb.walker.walksShort 7943 # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1501 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.hits 43906449 # DTB hits
system.cpu0.dtb.misses 7943 # DTB misses
system.cpu0.dtb.accesses 43914392 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks 3349 # Table walker walks requested
system.cpu0.itb.walker.walksShort 3349 # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1 299 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.hits 119016789 # DTB hits
system.cpu0.itb.misses 3349 # DTB misses
system.cpu0.itb.accesses 119020138 # DTB accesses
+system.cpu0.numPwrStateTransitions 3732 # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples 1866 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean 1464105256.698285 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev 23703834177.511120 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows 1075 57.61% 57.61% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10 786 42.12% 99.73% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.79% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.21% 100.00% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::max_value 499964077872 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total 1866 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON 137768561001 # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 2732020408999 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 5739577940 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 143145074 # Class of executed instruction
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 692159 # number of replacements
system.cpu0.dcache.tags.tagsinuse 489.914647 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 43035506 # Total number of references to valid blocks.
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 88449499 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 88449499 # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 23895288 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 23895288 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 18018356 # number of WriteReq hits
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208508.461248 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110014.123309 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110014.123309 # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 1103881 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.449165 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 117912387 # Total number of references to valid blocks.
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 239137980 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 239137980 # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 117912387 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 117912387 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 117912387 # number of demand (read+write) hits
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89937.541565 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89937.541565 # average overall mshr uncacheable latency
+system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued 1853175 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 1853224 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 43 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 238416 # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements 266444 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 16079.510665 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 2925486 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.918030 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 60110945 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 60110945 # Number of data accesses
+system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10236 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4573 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 14809 # number of ReadReq hits
system.cpu0.toL2Bus.snoop_filter.tot_snoops 316049 # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 311748 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4301 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq 61613 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 1692022 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 28463 # Transaction distribution
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy 14392485 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks 3352 # Table walker walks requested
system.cpu1.dtb.walker.walksShort 3352 # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 656 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.hits 7360620 # DTB hits
system.cpu1.dtb.misses 3352 # DTB misses
system.cpu1.dtb.accesses 7363972 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks 1746 # Table walker walks requested
system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.hits 16556610 # DTB hits
system.cpu1.itb.misses 1746 # DTB misses
system.cpu1.itb.accesses 16558356 # DTB accesses
+system.cpu1.numPwrStateTransitions 5511 # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples 2756 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean 1031898407.856313 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev 25737040202.524998 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows 1964 71.26% 71.26% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10 786 28.52% 99.78% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.85% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::8e+11-8.5e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::max_value 929980631528 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total 2756 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON 25876957948 # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 2843912012052 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 5738649789 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 20092250 # Class of executed instruction
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements 186389 # number of replacements
system.cpu1.dcache.tags.tagsinuse 469.298921 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 7093769 # Total number of references to valid blocks.
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.714844 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 14939866 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 14939866 # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data 3629400 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 3629400 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 3230955 # number of WriteReq hits
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143268.820679 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79966.997295 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79966.997295 # average overall mshr uncacheable latency
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements 505464 # number of replacements
system.cpu1.icache.tags.tagsinuse 498.478732 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 16050629 # Total number of references to valid blocks.
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 33619186 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 33619186 # Number of data accesses
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst 16050629 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 16050629 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 16050629 # number of demand (read+write) hits
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89132.768362 # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89132.768362 # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89132.768362 # average overall mshr uncacheable latency
+system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued 197600 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 197600 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 58944 # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements 44688 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 14938.485252 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 1161636 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.832886 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 23775762 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 23775762 # Number of data accesses
+system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3761 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2010 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 5771 # number of ReadReq hits
system.cpu1.toL2Bus.snoop_filter.tot_snoops 179165 # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 176020 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 3145 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq 12644 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 724299 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 2450 # Transaction distribution
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy 6050495 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 31015 # Transaction distribution
system.iobus.trans_dist::ReadResp 31015 # Transaction distribution
system.iobus.trans_dist::WriteReq 59422 # Transaction distribution
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 36445 # number of replacements
system.iocache.tags.tagsinuse 14.386648 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328311 # Number of tag accesses
system.iocache.tags.data_accesses 328311 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses
system.iocache.ReadReq_misses::total 255 # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.demand_avg_mshr_miss_latency::total 69016.530442 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 69016.530442 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 69016.530442 # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 126308 # number of replacements
system.l2c.tags.tagsinuse 63017.044477 # Cycle average of tags in use
system.l2c.tags.total_refs 424315 # Total number of references to valid blocks.
system.l2c.tags.occ_task_id_percent::1024 0.508820 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 5890164 # Number of tag accesses
system.l2c.tags.data_accesses 5890164 # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 260994 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 260994 # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data 31980 # number of UpgradeReq hits
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 44083 # Transaction distribution
system.membus.trans_dist::ReadResp 213856 # Transaction distribution
system.membus.trans_dist::WriteReq 30913 # Transaction distribution
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 1346131 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 980232 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 530887 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 150046 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 20267 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 19482 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 44086 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 477451 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution
sim_ticks 2909586837500 # Number of ticks simulated
final_tick 2909586837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1061137 # Simulator instruction rate (inst/s)
-host_op_rate 1279400 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 27454664075 # Simulator tick rate (ticks/s)
-host_mem_usage 618904 # Number of bytes of host memory used
-host_seconds 105.98 # Real time elapsed on the host
+host_inst_rate 987334 # Simulator instruction rate (inst/s)
+host_op_rate 1190416 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 25545157236 # Simulator tick rate (ticks/s)
+host_mem_usage 619552 # Number of bytes of host memory used
+host_seconds 113.90 # Real time elapsed on the host
sim_insts 112457035 # Number of instructions simulated
sim_ops 135588119 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 1186532 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 36861863500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 9546 # Table walker walks requested
system.cpu.dtb.walker.walksShort 9546 # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1255 # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.hits 44127473 # DTB hits
system.cpu.dtb.misses 9546 # DTB misses
system.cpu.dtb.accesses 44137019 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 4763 # Table walker walks requested
system.cpu.itb.walker.walksShort 4763 # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walksShortTerminationLevel::Level1 310 # Level at which table walker walks with short descriptors terminate
system.cpu.itb.hits 115554258 # DTB hits
system.cpu.itb.misses 4763 # DTB misses
system.cpu.itb.accesses 115559021 # DTB accesses
+system.cpu.numPwrStateTransitions 6066 # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples 3033 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean 886754793.248599 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev 17463725759.115368 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::underflows 2967 97.82% 97.82% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10 60 1.98% 99.80% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::max_value 499963874372 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::total 3033 # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::ON 220059549577 # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 2689527287923 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 5819173675 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 138708215 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 819223 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.702328 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 43236237 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 177112679 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 177112679 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 23112984 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 23112984 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 18824227 # number of WriteReq hits
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201623.402274 # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106903.970916 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106903.970916 # average overall mshr uncacheable latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 1695721 # number of replacements
system.cpu.icache.tags.tagsinuse 510.436852 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 113858019 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 117250497 # Number of tag accesses
system.cpu.icache.tags.data_accesses 117250497 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 113858019 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 113858019 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 113858019 # number of demand (read+write) hits
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126639.436932 # average overall mshr uncacheable latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 87565 # number of replacements
system.cpu.l2cache.tags.tagsinuse 64865.223598 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 4544536 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995331 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 40512344 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 40512344 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7807 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4039 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 11846 # number of ReadReq hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 581 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 581 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq 67213 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2287480 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy 17837000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 30177 # Transaction distribution
system.iobus.trans_dist::ReadResp 30177 # Transaction distribution
system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 36418 # number of replacements
system.iocache.tags.tagsinuse 1.084082 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328068 # Number of tag accesses
system.iocache.tags.data_accesses 328068 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide 228 # number of ReadReq misses
system.iocache.ReadReq_misses::total 228 # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.demand_avg_mshr_miss_latency::total 75532.261687 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 75532.261687 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 75532.261687 # average overall mshr miss latency
+system.membus.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 40160 # Transaction distribution
system.membus.trans_dist::ReadResp 70548 # Transaction distribution
system.membus.trans_dist::WriteReq 27589 # Transaction distribution
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 1186623 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2909586837500 # Cumulative time (in ticks) in various power states
---------- End Simulation Statistics ----------
sim_ticks 2783853866500 # Number of ticks simulated
final_tick 2783853866500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1657563 # Simulator instruction rate (inst/s)
-host_op_rate 2017817 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 32320507686 # Simulator tick rate (ticks/s)
-host_mem_usage 622988 # Number of bytes of host memory used
-host_seconds 86.13 # Real time elapsed on the host
+host_inst_rate 1399722 # Simulator instruction rate (inst/s)
+host_op_rate 1703936 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 27292901384 # Simulator tick rate (ticks/s)
+host_mem_usage 623636 # Number of bytes of host memory used
+host_seconds 102.00 # Real time elapsed on the host
sim_insts 142770436 # Number of instructions simulated
sim_ops 173800089 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 724196 # Number of bytes read from this memory
system.physmem.bw_total::cpu1.data 2034732 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 7324797 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks 5701 # Table walker walks requested
system.cpu0.dtb.walker.walksShort 5701 # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walkWaitTime::samples 5701 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.hits 27278258 # DTB hits
system.cpu0.dtb.misses 5701 # DTB misses
system.cpu0.dtb.accesses 27283959 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks 2590 # Table walker walks requested
system.cpu0.itb.walker.walksShort 2590 # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walkWaitTime::samples 2590 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.hits 74798476 # DTB hits
system.cpu0.itb.misses 2590 # DTB misses
system.cpu0.itb.accesses 74801066 # DTB accesses
+system.cpu0.numPwrStateTransitions 3056 # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples 1528 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean 1733162653.613220 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev 24573206654.114037 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows 1469 96.14% 96.14% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10 53 3.47% 99.61% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.07% 99.67% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.07% 99.74% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.07% 99.80% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 3 0.20% 100.00% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::max_value 499984036900 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total 1528 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON 135581331779 # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 2648272534721 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 5536444785 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 89752341 # Class of executed instruction
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 819388 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 53783378 # Total number of references to valid blocks.
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 219233092 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 219233092 # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 15305418 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 14823075 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 30128493 # number of ReadReq hits
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks 682241 # number of writebacks
system.cpu0.dcache.writebacks::total 682241 # number of writebacks
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 1698997 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 145340473 # Total number of references to valid blocks.
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 148739503 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 148739503 # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 73956240 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 71384233 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 145340473 # number of ReadReq hits
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks 1698997 # number of writebacks
system.cpu0.icache.writebacks::total 1698997 # number of writebacks
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks 6190 # Table walker walks requested
system.cpu1.dtb.walker.walksShort 6190 # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walkWaitTime::samples 6190 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.hits 27369436 # DTB hits
system.cpu1.dtb.misses 6190 # DTB misses
system.cpu1.dtb.accesses 27375626 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks 3051 # Table walker walks requested
system.cpu1.itb.walker.walksShort 3051 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walkWaitTime::samples 3051 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.hits 72237526 # DTB hits
system.cpu1.itb.misses 3051 # DTB misses
system.cpu1.itb.accesses 72240577 # DTB accesses
+system.cpu1.numPwrStateTransitions 3092 # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples 1546 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean 1765528734.857697 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev 61147535730.449074 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows 1529 98.90% 98.90% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10 14 0.91% 99.81% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.06% 99.87% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.06% 99.94% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::overflows 1 0.06% 100.00% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::max_value 2395080450001 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total 1546 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON 54346442410 # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 2729507424090 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 88014282 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 87464517 # Class of executed instruction
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 30164 # Transaction distribution
system.iobus.trans_dist::ReadResp 30164 # Transaction distribution
system.iobus.trans_dist::WriteReq 59002 # Transaction distribution
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 36430 # number of replacements
system.iocache.tags.tagsinuse 0.909889 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328176 # Number of tag accesses
system.iocache.tags.data_accesses 328176 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses
system.iocache.ReadReq_misses::total 240 # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.writebacks::writebacks 36190 # number of writebacks
system.iocache.writebacks::total 36190 # number of writebacks
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 109908 # number of replacements
system.l2c.tags.tagsinuse 65155.315514 # Cycle average of tags in use
system.l2c.tags.total_refs 4528029 # Total number of references to valid blocks.
system.l2c.tags.occ_task_id_percent::1024 0.996048 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 40604397 # Number of tag accesses
system.l2c.tags.data_accesses 40604397 # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
system.l2c.ReadReq_hits::cpu0.dtb.walker 4717 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 2285 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 4983 # number of ReadReq hits
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 40087 # Transaction distribution
system.membus.trans_dist::ReadResp 74196 # Transaction distribution
system.membus.trans_dist::WriteReq 27546 # Transaction distribution
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 434811 # Request fanout histogram
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 5060315 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 2540903 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 39264 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 71253 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2291775 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution
sim_ticks 2903879904500 # Number of ticks simulated
final_tick 2903879904500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1077958 # Simulator instruction rate (inst/s)
-host_op_rate 1299696 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 27831365956 # Simulator tick rate (ticks/s)
-host_mem_usage 624164 # Number of bytes of host memory used
-host_seconds 104.34 # Real time elapsed on the host
+host_inst_rate 952808 # Simulator instruction rate (inst/s)
+host_op_rate 1148802 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 24600165137 # Simulator tick rate (ticks/s)
+host_mem_usage 624836 # Number of bytes of host memory used
+host_seconds 118.04 # Real time elapsed on the host
sim_insts 112472358 # Number of instructions simulated
sim_ops 135608167 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 557092 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 33450042500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks 6844 # Table walker walks requested
system.cpu0.dtb.walker.walksShort 6844 # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 2237 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.hits 21854325 # DTB hits
system.cpu0.dtb.misses 6844 # DTB misses
system.cpu0.dtb.accesses 21861169 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks 3527 # Table walker walks requested
system.cpu0.itb.walker.walksShort 3527 # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1 843 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.hits 57466570 # DTB hits
system.cpu0.itb.misses 3527 # DTB misses
system.cpu0.itb.accesses 57470097 # DTB accesses
+system.cpu0.numPwrStateTransitions 3088 # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples 1544 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean 1559165456.796632 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev 23913437415.201466 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows 1498 97.02% 97.02% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10 41 2.66% 99.68% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.06% 99.74% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.06% 99.81% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 3 0.19% 100.00% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::max_value 499963862372 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total 1544 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON 496528439206 # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 2407351465294 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 2904046767 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 68839780 # Class of executed instruction
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 819212 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.827217 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 43241768 # Total number of references to valid blocks.
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 177132717 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 177132717 # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 11490299 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 11626240 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 23116539 # number of ReadReq hits
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95931.651267 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 118119.739548 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 106956.365896 # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 1697986 # number of replacements
system.cpu0.icache.tags.tagsinuse 510.728403 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 113871932 # Total number of references to valid blocks.
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 117268940 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 117268940 # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 56612158 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 57259774 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 113871932 # number of ReadReq hits
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 76179.006872 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 76179.006872 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 76179.006872 # average overall mshr uncacheable latency
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks 6555 # Table walker walks requested
system.cpu1.dtb.walker.walksShort 6555 # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 1891 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.hits 22278160 # DTB hits
system.cpu1.dtb.misses 6555 # DTB misses
system.cpu1.dtb.accesses 22284715 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks 3197 # Table walker walks requested
system.cpu1.itb.walker.walksShort 3197 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 694 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.hits 58103866 # DTB hits
system.cpu1.itb.misses 3197 # DTB misses
system.cpu1.itb.accesses 58107063 # DTB accesses
+system.cpu1.numPwrStateTransitions 2958 # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples 1479 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean 1717670727.160244 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev 49232811122.635986 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows 1466 99.12% 99.12% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10 10 0.68% 99.80% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.07% 99.86% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.07% 99.93% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::overflows 1 0.07% 100.00% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::max_value 1799694071001 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total 1479 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON 363444899030 # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 2540435005470 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 2903713042 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 69889494 # Class of executed instruction
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 30183 # Transaction distribution
system.iobus.trans_dist::ReadResp 30183 # Transaction distribution
system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 36424 # number of replacements
system.iocache.tags.tagsinuse 1.079319 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328122 # Number of tag accesses
system.iocache.tags.data_accesses 328122 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses
system.iocache.ReadReq_misses::total 234 # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.demand_avg_mshr_miss_latency::total 68070.398952 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 68070.398952 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 68070.398952 # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 88930 # number of replacements
system.l2c.tags.tagsinuse 64921.564367 # Cycle average of tags in use
system.l2c.tags.total_refs 4554585 # Total number of references to valid blocks.
system.l2c.tags.occ_task_id_percent::1024 0.995682 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 40592424 # Number of tag accesses
system.l2c.tags.data_accesses 40592424 # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
system.l2c.ReadReq_hits::cpu0.dtb.walker 6056 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 3327 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 5249 # number of ReadReq hits
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 40160 # Transaction distribution
system.membus.trans_dist::ReadResp 70472 # Transaction distribution
system.membus.trans_dist::WriteReq 27589 # Transaction distribution
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 1219623 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 5058603 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 2540370 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 38310 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 250 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 250 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2903879904500 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 74739 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2297326 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution
sim_ticks 200409271000 # Number of ticks simulated
final_tick 4321213476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 17114164 # Simulator instruction rate (inst/s)
-host_op_rate 17114158 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6548224120 # Simulator tick rate (ticks/s)
-host_mem_usage 490760 # Number of bytes of host memory used
-host_seconds 30.61 # Real time elapsed on the host
+host_inst_rate 21345619 # Simulator instruction rate (inst/s)
+host_op_rate 21345611 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 8167264006 # Simulator tick rate (ticks/s)
+host_mem_usage 541036 # Number of bytes of host memory used
+host_seconds 24.54 # Real time elapsed on the host
sim_insts 523780905 # Number of instructions simulated
sim_ops 523780905 # Number of ops (including micro ops) simulated
drivesys.voltage_domain.voltage 1 # Voltage in Volts
drivesys.clk_domain.clock 1000 # Clock period in ticks
+drivesys.physmem.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
drivesys.physmem.bytes_read::cpu.inst 76205572 # Number of bytes read from this memory
drivesys.physmem.bytes_read::cpu.data 26284292 # Number of bytes read from this memory
drivesys.physmem.bytes_read::tsunami.ethernet 57260550 # Number of bytes read from this memory
drivesys.physmem.bw_total::cpu.data 204101955 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.bw_total::tsunami.ethernet 285723379 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.bw_total::total 870075068 # Total bandwidth to/from this memory (bytes/s)
+drivesys.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+drivesys.bridge.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
drivesys.cpu.clk_domain.clock 250 # Clock period in ticks
drivesys.cpu.dtb.fetch_hits 0 # ITB hits
drivesys.cpu.dtb.fetch_misses 0 # ITB misses
drivesys.cpu.itb.data_misses 0 # DTB misses
drivesys.cpu.itb.data_acv 0 # DTB access violations
drivesys.cpu.itb.data_accesses 0 # DTB accesses
+drivesys.cpu.numPwrStateTransitions 39752 # Number of power state transitions
+drivesys.cpu.pwrStateClkGateDist::samples 19877 # Distribution of time spent in the clock gated state
+drivesys.cpu.pwrStateClkGateDist::mean 9843365.409770 # Distribution of time spent in the clock gated state
+drivesys.cpu.pwrStateClkGateDist::stdev 830979.613808 # Distribution of time spent in the clock gated state
+drivesys.cpu.pwrStateClkGateDist::1000-5e+10 19877 100.00% 100.00% # Distribution of time spent in the clock gated state
+drivesys.cpu.pwrStateClkGateDist::min_value 25500 # Distribution of time spent in the clock gated state
+drivesys.cpu.pwrStateClkGateDist::max_value 9947500 # Distribution of time spent in the clock gated state
+drivesys.cpu.pwrStateClkGateDist::total 19877 # Distribution of time spent in the clock gated state
+drivesys.cpu.pwrStateResidencyTicks::ON 4757933250 # Cumulative time (in ticks) in various power states
+drivesys.cpu.pwrStateResidencyTicks::CLK_GATED 195656574250 # Cumulative time (in ticks) in various power states
drivesys.cpu.numCycles 801651324 # number of cpu cycles simulated
drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions.
+drivesys.iobridge.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+drivesys.iobus.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
drivesys.iobus.trans_dist::ReadReq 2484469 # Transaction distribution
drivesys.iobus.trans_dist::ReadResp 2484469 # Transaction distribution
drivesys.iobus.trans_dist::WriteReq 39723 # Transaction distribution
drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 57261614 # Cumulative packet size per connected master and slave (bytes)
drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::total 57261614 # Cumulative packet size per connected master and slave (bytes)
drivesys.iobus.pkt_size::total 58210218 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
drivesys.membus.trans_dist::ReadReq 25081955 # Transaction distribution
drivesys.membus.trans_dist::ReadResp 25182911 # Transaction distribution
drivesys.membus.trans_dist::WriteReq 1963575 # Transaction distribution
drivesys.membus.snoop_fanout::min_value 0 # Request fanout histogram
drivesys.membus.snoop_fanout::max_value 1 # Request fanout histogram
drivesys.membus.snoop_fanout::total 27247410 # Request fanout histogram
+drivesys.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
drivesys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks
+drivesys.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted
drivesys.tsunami.ethernet.rxBytes 960 # Bytes Received
drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted
drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
drivesys.tsunami.ethernet.postedInterrupts 2385831 # number of posts to CPU
drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+drivesys.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.io.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
testsys.voltage_domain.voltage 1 # Voltage in Volts
testsys.clk_domain.clock 1000 # Clock period in ticks
+testsys.physmem.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
testsys.physmem.bytes_read::cpu.inst 81044080 # Number of bytes read from this memory
testsys.physmem.bytes_read::cpu.data 27825116 # Number of bytes read from this memory
testsys.physmem.bytes_read::tsunami.ethernet 57260496 # Number of bytes read from this memory
testsys.physmem.bw_total::cpu.data 221698925 # Total bandwidth to/from this memory (bytes/s)
testsys.physmem.bw_total::tsunami.ethernet 285722301 # Total bandwidth to/from this memory (bytes/s)
testsys.physmem.bw_total::total 911814095 # Total bandwidth to/from this memory (bytes/s)
+testsys.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+testsys.bridge.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
testsys.cpu.clk_domain.clock 500 # Clock period in ticks
testsys.cpu.dtb.fetch_hits 0 # ITB hits
testsys.cpu.dtb.fetch_misses 0 # ITB misses
testsys.cpu.itb.data_misses 0 # DTB misses
testsys.cpu.itb.data_acv 0 # DTB access violations
testsys.cpu.itb.data_accesses 0 # DTB accesses
+testsys.cpu.numPwrStateTransitions 39159 # Number of power state transitions
+testsys.cpu.pwrStateClkGateDist::samples 19580 # Distribution of time spent in the clock gated state
+testsys.cpu.pwrStateClkGateDist::mean 9718476.378958 # Distribution of time spent in the clock gated state
+testsys.cpu.pwrStateClkGateDist::stdev 783559.874332 # Distribution of time spent in the clock gated state
+testsys.cpu.pwrStateClkGateDist::1000-5e+10 19580 100.00% 100.00% # Distribution of time spent in the clock gated state
+testsys.cpu.pwrStateClkGateDist::min_value 105000 # Distribution of time spent in the clock gated state
+testsys.cpu.pwrStateClkGateDist::max_value 9815000 # Distribution of time spent in the clock gated state
+testsys.cpu.pwrStateClkGateDist::total 19580 # Distribution of time spent in the clock gated state
+testsys.cpu.pwrStateResidencyTicks::ON 11102310500 # Cumulative time (in ticks) in various power states
+testsys.cpu.pwrStateResidencyTicks::CLK_GATED 190287767500 # Cumulative time (in ticks) in various power states
testsys.cpu.numCycles 400825859 # number of cpu cycles simulated
testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
testsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
testsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
testsys.disk2.dma_write_txs 0 # Number of DMA write transactions.
+testsys.iobridge.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+testsys.iobus.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
testsys.iobus.trans_dist::ReadReq 2483943 # Transaction distribution
testsys.iobus.trans_dist::ReadResp 2483943 # Transaction distribution
testsys.iobus.trans_dist::WriteReq 39573 # Transaction distribution
testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 57261398 # Cumulative packet size per connected master and slave (bytes)
testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::total 57261398 # Cumulative packet size per connected master and slave (bytes)
testsys.iobus.pkt_size::total 58203550 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
testsys.membus.trans_dist::ReadReq 26478762 # Transaction distribution
testsys.membus.trans_dist::ReadResp 26587372 # Transaction distribution
testsys.membus.trans_dist::WriteReq 2189273 # Transaction distribution
testsys.membus.snoop_fanout::min_value 0 # Request fanout histogram
testsys.membus.snoop_fanout::max_value 1 # Request fanout histogram
testsys.membus.snoop_fanout::total 28885173 # Request fanout histogram
+testsys.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+testsys.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+testsys.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
testsys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks
+testsys.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+testsys.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted
testsys.tsunami.ethernet.rxBytes 798 # Bytes Received
testsys.tsunami.ethernet.txPackets 8 # Number of Packets Transmitted
testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
testsys.tsunami.ethernet.postedInterrupts 2385819 # number of posts to CPU
testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+testsys.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+testsys.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+testsys.tsunami.io.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
+testsys.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
---------- End Simulation Statistics ----------
sim_ticks 407341500 # Number of ticks simulated
final_tick 4321620817500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 9054438128 # Simulator instruction rate (inst/s)
-host_op_rate 9052667837 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 7037972394 # Simulator tick rate (ticks/s)
-host_mem_usage 490760 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 10808376500 # Simulator instruction rate (inst/s)
+host_op_rate 10806472833 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 8401634086 # Simulator tick rate (ticks/s)
+host_mem_usage 541036 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
sim_insts 523853183 # Number of instructions simulated
sim_ops 523853183 # Number of ops (including micro ops) simulated
drivesys.voltage_domain.voltage 1 # Voltage in Volts
drivesys.clk_domain.clock 1000 # Clock period in ticks
+drivesys.physmem.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
drivesys.physmem.bytes_read::cpu.inst 144608 # Number of bytes read from this memory
drivesys.physmem.bytes_read::cpu.data 49952 # Number of bytes read from this memory
drivesys.physmem.bytes_read::tsunami.ethernet 116400 # Number of bytes read from this memory
drivesys.physmem.bw_total::cpu.data 190601743 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.bw_total::tsunami.ethernet 285755318 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.bw_total::total 831361401 # Total bandwidth to/from this memory (bytes/s)
+drivesys.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+drivesys.bridge.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
drivesys.cpu.clk_domain.clock 250 # Clock period in ticks
drivesys.cpu.dtb.fetch_hits 0 # ITB hits
drivesys.cpu.dtb.fetch_misses 0 # ITB misses
drivesys.cpu.itb.data_misses 0 # DTB misses
drivesys.cpu.itb.data_acv 0 # DTB access violations
drivesys.cpu.itb.data_accesses 0 # DTB accesses
+drivesys.cpu.numPwrStateTransitions 82 # Number of power state transitions
+drivesys.cpu.pwrStateClkGateDist::samples 42 # Distribution of time spent in the clock gated state
+drivesys.cpu.pwrStateClkGateDist::mean 9483660.714286 # Distribution of time spent in the clock gated state
+drivesys.cpu.pwrStateClkGateDist::stdev 1743513.957554 # Distribution of time spent in the clock gated state
+drivesys.cpu.pwrStateClkGateDist::1000-5e+10 42 100.00% 100.00% # Distribution of time spent in the clock gated state
+drivesys.cpu.pwrStateClkGateDist::min_value 920000 # Distribution of time spent in the clock gated state
+drivesys.cpu.pwrStateClkGateDist::max_value 9947500 # Distribution of time spent in the clock gated state
+drivesys.cpu.pwrStateClkGateDist::total 42 # Distribution of time spent in the clock gated state
+drivesys.cpu.pwrStateResidencyTicks::ON 9027750 # Cumulative time (in ticks) in various power states
+drivesys.cpu.pwrStateResidencyTicks::CLK_GATED 398313750 # Cumulative time (in ticks) in various power states
drivesys.cpu.numCycles 1626281 # number of cpu cycles simulated
drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions.
+drivesys.iobridge.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+drivesys.iobus.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
drivesys.iobus.trans_dist::ReadReq 5050 # Transaction distribution
drivesys.iobus.trans_dist::ReadResp 5050 # Transaction distribution
drivesys.iobus.trans_dist::WriteReq 81 # Transaction distribution
drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 116400 # Cumulative packet size per connected master and slave (bytes)
drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::total 116400 # Cumulative packet size per connected master and slave (bytes)
drivesys.iobus.pkt_size::total 118328 # Cumulative packet size per connected master and slave (bytes)
+drivesys.membus.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
drivesys.membus.trans_dist::ReadReq 47907 # Transaction distribution
drivesys.membus.trans_dist::ReadResp 48111 # Transaction distribution
drivesys.membus.trans_dist::WriteReq 3689 # Transaction distribution
drivesys.membus.snoop_fanout::min_value 0 # Request fanout histogram
drivesys.membus.snoop_fanout::max_value 1 # Request fanout histogram
drivesys.membus.snoop_fanout::total 52004 # Request fanout histogram
+drivesys.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
drivesys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks
+drivesys.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
drivesys.tsunami.ethernet.descDMAReads 4850 # Number of descriptors the device read w/ DMA
drivesys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
drivesys.tsunami.ethernet.descDmaReadBytes 116400 # number of descriptor bytes read w/ DMA
drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
drivesys.tsunami.ethernet.postedInterrupts 4850 # number of posts to CPU
drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+drivesys.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.io.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+drivesys.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
testsys.voltage_domain.voltage 1 # Voltage in Volts
testsys.clk_domain.clock 1000 # Clock period in ticks
+testsys.physmem.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
testsys.physmem.bytes_read::cpu.inst 144504 # Number of bytes read from this memory
testsys.physmem.bytes_read::cpu.data 49936 # Number of bytes read from this memory
testsys.physmem.bytes_read::tsunami.ethernet 116376 # Number of bytes read from this memory
testsys.physmem.bw_total::cpu.data 190601743 # Total bandwidth to/from this memory (bytes/s)
testsys.physmem.bw_total::tsunami.ethernet 285696400 # Total bandwidth to/from this memory (bytes/s)
testsys.physmem.bw_total::total 831047168 # Total bandwidth to/from this memory (bytes/s)
+testsys.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+testsys.bridge.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
testsys.cpu.clk_domain.clock 500 # Clock period in ticks
testsys.cpu.dtb.fetch_hits 0 # ITB hits
testsys.cpu.dtb.fetch_misses 0 # ITB misses
testsys.cpu.itb.data_misses 0 # DTB misses
testsys.cpu.itb.data_acv 0 # DTB access violations
testsys.cpu.itb.data_accesses 0 # DTB accesses
+testsys.cpu.numPwrStateTransitions 80 # Number of power state transitions
+testsys.cpu.pwrStateClkGateDist::samples 41 # Distribution of time spent in the clock gated state
+testsys.cpu.pwrStateClkGateDist::mean 9495085.365854 # Distribution of time spent in the clock gated state
+testsys.cpu.pwrStateClkGateDist::stdev 1417220.659876 # Distribution of time spent in the clock gated state
+testsys.cpu.pwrStateClkGateDist::1000-5e+10 41 100.00% 100.00% # Distribution of time spent in the clock gated state
+testsys.cpu.pwrStateClkGateDist::min_value 2964500 # Distribution of time spent in the clock gated state
+testsys.cpu.pwrStateClkGateDist::max_value 9815000 # Distribution of time spent in the clock gated state
+testsys.cpu.pwrStateClkGateDist::total 41 # Distribution of time spent in the clock gated state
+testsys.cpu.pwrStateResidencyTicks::ON 18043000 # Cumulative time (in ticks) in various power states
+testsys.cpu.pwrStateResidencyTicks::CLK_GATED 389298500 # Cumulative time (in ticks) in various power states
testsys.cpu.numCycles 821056 # number of cpu cycles simulated
testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
testsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
testsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
testsys.disk2.dma_write_txs 0 # Number of DMA write transactions.
+testsys.iobridge.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+testsys.iobus.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
testsys.iobus.trans_dist::ReadReq 5049 # Transaction distribution
testsys.iobus.trans_dist::ReadResp 5049 # Transaction distribution
testsys.iobus.trans_dist::WriteReq 81 # Transaction distribution
testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 116376 # Cumulative packet size per connected master and slave (bytes)
testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::total 116376 # Cumulative packet size per connected master and slave (bytes)
testsys.iobus.pkt_size::total 118304 # Cumulative packet size per connected master and slave (bytes)
+testsys.membus.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
testsys.membus.trans_dist::ReadReq 47876 # Transaction distribution
testsys.membus.trans_dist::ReadResp 48080 # Transaction distribution
testsys.membus.trans_dist::WriteReq 3691 # Transaction distribution
testsys.membus.snoop_fanout::min_value 0 # Request fanout histogram
testsys.membus.snoop_fanout::max_value 1 # Request fanout histogram
testsys.membus.snoop_fanout::total 51975 # Request fanout histogram
+testsys.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+testsys.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+testsys.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
testsys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks
+testsys.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+testsys.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
testsys.tsunami.ethernet.descDMAReads 4849 # Number of descriptors the device read w/ DMA
testsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
testsys.tsunami.ethernet.descDmaReadBytes 116376 # number of descriptor bytes read w/ DMA
testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
testsys.tsunami.ethernet.postedInterrupts 4849 # number of posts to CPU
testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+testsys.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+testsys.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+testsys.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+testsys.tsunami.io.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
+testsys.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
---------- End Simulation Statistics ----------
sim_ticks 37494000 # Number of ticks simulated
final_tick 37494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 176621 # Simulator instruction rate (inst/s)
-host_op_rate 176529 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1031613588 # Simulator tick rate (ticks/s)
-host_mem_usage 248004 # Number of bytes of host memory used
-host_seconds 0.04 # Real time elapsed on the host
+host_inst_rate 200557 # Simulator instruction rate (inst/s)
+host_op_rate 200498 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1171902214 # Simulator tick rate (ticks/s)
+host_mem_usage 294520 # Number of bytes of host memory used
+host_seconds 0.03 # Real time elapsed on the host
sim_insts 6413 # Number of instructions simulated
sim_ops 6413 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10816 # Number of bytes read from this memory
system.physmem.bytes_read::total 34048 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 28986000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 2009 # Number of BP lookups
system.cpu.branchPred.condPredicted 1241 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 379 # Number of conditional branches incorrect
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 37494000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 74988 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class_0::total 6413 # Class of committed instruction
system.cpu.tickCycles 12653 # Number of cycles that the object actually ticked
system.cpu.idleCycles 62335 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 104.135823 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1980 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 4583 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4583 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 1240 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1240 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 77565.088757 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77565.088757 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 77565.088757 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 175.312988 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 2323 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.177734 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 5738 # Number of tag accesses
system.cpu.icache.tags.data_accesses 5738 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 2323 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 2323 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 2323 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 75280.219780 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75280.219780 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 75280.219780 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 233.336913 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014008 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4796 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4796 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 460 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 253500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 459 # Transaction distribution
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
sim_ticks 22019000 # Number of ticks simulated
final_tick 22019000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 115969 # Simulator instruction rate (inst/s)
-host_op_rate 115940 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 399737091 # Simulator tick rate (ticks/s)
-host_mem_usage 249288 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 117755 # Simulator instruction rate (inst/s)
+host_op_rate 117735 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 405950936 # Simulator tick rate (ticks/s)
+host_mem_usage 294524 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
sim_insts 6385 # Number of instructions simulated
sim_ops 6385 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory
system.physmem.bytes_read::total 31040 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 14308250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 2849 # Number of BP lookups
system.cpu.branchPred.condPredicted 1676 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 481 # Number of conditional branches incorrect
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 22019000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 44039 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 109.409218 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 2405 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 6061 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 6061 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 1899 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1899 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 81858.381503 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81858.381503 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 81858.381503 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 158.432951 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1836 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.152832 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 4899 # Number of tag accesses
system.cpu.icache.tags.data_accesses 4899 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 1836 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1836 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1836 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 78180.511182 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78180.511182 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 78180.511182 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 220.994877 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012604 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4373 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4373 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 414 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 413 # Transaction distribution
system.membus.trans_dist::ReadExReq 72 # Transaction distribution
system.membus.trans_dist::ReadExResp 72 # Transaction distribution
sim_ticks 3214500 # Number of ticks simulated
final_tick 3214500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1011674 # Simulator instruction rate (inst/s)
-host_op_rate 1009913 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 506215370 # Simulator tick rate (ticks/s)
-host_mem_usage 237756 # Number of bytes of host memory used
+host_inst_rate 879431 # Simulator instruction rate (inst/s)
+host_op_rate 878309 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 440397606 # Simulator tick rate (ticks/s)
+host_mem_usage 282472 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 3214500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 25652 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory
system.physmem.bytes_read::total 34456 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7980090216 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4821900762 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12801990978 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 3214500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 3214500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 6430 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6413 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 3214500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 7598 # Transaction distribution
system.membus.trans_dist::ReadResp 7598 # Transaction distribution
system.membus.trans_dist::WriteReq 865 # Transaction distribution
sim_ticks 121535 # Number of ticks simulated
final_tick 121535 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 71837 # Simulator instruction rate (inst/s)
-host_op_rate 71828 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1363198 # Simulator tick rate (ticks/s)
-host_mem_usage 407704 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
+host_inst_rate 67126 # Simulator instruction rate (inst/s)
+host_op_rate 67120 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1273887 # Simulator tick rate (ticks/s)
+host_mem_usage 453732 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 93504 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 93504 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 17728 # Number of bytes written to this memory
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 111353 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 121535 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 121535 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6413 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
+system.ruby.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
system.ruby.delayHist::samples 9652 # delay histogram for all message
system.ruby.miss_latency_hist_seqr::stdev 30.103565
system.ruby.miss_latency_hist_seqr | 331 22.20% 22.20% | 1141 76.53% 98.73% | 4 0.27% 98.99% | 1 0.07% 99.06% | 8 0.54% 99.60% | 6 0.40% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 1491
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.L1Dcache.demand_hits 1250 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 800 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses
system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
system.ruby.l2_cntrl0.L2cache.demand_hits 30 # Number of cache demand hits
system.ruby.l2_cntrl0.L2cache.demand_misses 1461 # Number of cache demand misses
system.ruby.l2_cntrl0.L2cache.demand_accesses 1491 # Number of cache demand accesses
+system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.percent_links_utilized 4.310281
system.ruby.network.routers0.msg_count.Control::0 1491
system.ruby.network.routers0.msg_count.Request_Control::2 1041
system.ruby.network.routers0.msg_bytes.Writeback_Data::0 10440
system.ruby.network.routers0.msg_bytes.Writeback_Data::1 10152
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 2336
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
system.ruby.network.routers1.percent_links_utilized 8.369194
system.ruby.network.routers1.msg_count.Control::0 2952
system.ruby.network.routers1.msg_count.Request_Control::2 1041
system.ruby.network.routers1.msg_bytes.Writeback_Data::0 10440
system.ruby.network.routers1.msg_bytes.Writeback_Data::1 10152
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 2336
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
system.ruby.network.routers2.percent_links_utilized 4.058913
system.ruby.network.routers2.msg_count.Control::0 1461
system.ruby.network.routers2.msg_count.Response_Data::1 1738
system.ruby.network.routers2.msg_bytes.Control::0 11688
system.ruby.network.routers2.msg_bytes.Response_Data::1 125136
system.ruby.network.routers2.msg_bytes.Response_Control::1 21032
+system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
system.ruby.network.routers3.percent_links_utilized 5.579463
system.ruby.network.routers3.msg_count.Control::0 2952
system.ruby.network.routers3.msg_count.Request_Control::2 1041
system.ruby.network.routers3.msg_bytes.Writeback_Data::0 10440
system.ruby.network.routers3.msg_bytes.Writeback_Data::1 10152
system.ruby.network.routers3.msg_bytes.Writeback_Control::0 2336
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Control 8856
system.ruby.network.msg_count.Request_Control 3123
system.ruby.network.msg_count.Response_Data 9687
system.ruby.network.msg_byte.Response_Control 114384
system.ruby.network.msg_byte.Writeback_Data 61776
system.ruby.network.msg_byte.Writeback_Control 7008
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.throttle0.link_utilization 6.128687
system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 1041
system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 1491
sim_ticks 108878 # Number of ticks simulated
final_tick 108878 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 68389 # Simulator instruction rate (inst/s)
-host_op_rate 68380 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1162621 # Simulator tick rate (ticks/s)
-host_mem_usage 413676 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
+host_inst_rate 66441 # Simulator instruction rate (inst/s)
+host_op_rate 66435 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1129573 # Simulator tick rate (ticks/s)
+host_mem_usage 461124 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 75712 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 75712 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 12416 # Number of bytes written to this memory
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 96382 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 108878 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 108878 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6413 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
+system.ruby.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
system.ruby.outstanding_req_hist_seqr::samples 8464
system.ruby.miss_latency_hist_seqr::stdev 33.791401
system.ruby.miss_latency_hist_seqr | 412 28.97% 28.97% | 995 69.97% 98.95% | 2 0.14% 99.09% | 0 0.00% 99.09% | 9 0.63% 99.72% | 4 0.28% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 1422
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.L1Dcache.demand_hits 1274 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 776 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_hits 5767 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
system.ruby.l2_cntrl0.L2cache.demand_hits 239 # Number of cache demand hits
system.ruby.l2_cntrl0.L2cache.demand_misses 1183 # Number of cache demand misses
system.ruby.l2_cntrl0.L2cache.demand_accesses 1422 # Number of cache demand accesses
+system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.percent_links_utilized 6.929545
system.ruby.network.routers0.msg_count.Request_Control::0 1422
system.ruby.network.routers0.msg_count.Response_Data::2 1183
system.ruby.network.routers0.msg_bytes.Writeback_Data::2 94248
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 21680
system.ruby.network.routers0.msg_bytes.Unblock_Control::2 11744
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
system.ruby.network.routers1.percent_links_utilized 10.407520
system.ruby.network.routers1.msg_count.Request_Control::0 1422
system.ruby.network.routers1.msg_count.Request_Control::1 1183
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 21680
system.ruby.network.routers1.msg_bytes.Writeback_Control::1 3104
system.ruby.network.routers1.msg_bytes.Unblock_Control::2 21208
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
system.ruby.network.routers2.percent_links_utilized 3.477975
system.ruby.network.routers2.msg_count.Request_Control::1 1183
system.ruby.network.routers2.msg_count.Response_Data::2 1183
system.ruby.network.routers2.msg_bytes.Writeback_Data::2 13968
system.ruby.network.routers2.msg_bytes.Writeback_Control::1 3104
system.ruby.network.routers2.msg_bytes.Unblock_Control::2 9464
+system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
system.ruby.network.routers3.percent_links_utilized 6.938347
system.ruby.network.routers3.msg_count.Request_Control::0 1422
system.ruby.network.routers3.msg_count.Request_Control::1 1183
system.ruby.network.routers3.msg_bytes.Writeback_Control::0 21680
system.ruby.network.routers3.msg_bytes.Writeback_Control::1 3104
system.ruby.network.routers3.msg_bytes.Unblock_Control::2 21208
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Request_Control 7815
system.ruby.network.msg_count.Response_Data 7098
system.ruby.network.msg_count.ResponseL2hit_Data 717
system.ruby.network.msg_byte.Writeback_Data 324648
system.ruby.network.msg_byte.Writeback_Control 74352
system.ruby.network.msg_byte.Unblock_Control 63624
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.throttle0.link_utilization 6.499476
system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 1183
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 239
sim_ticks 108253 # Number of ticks simulated
final_tick 108253 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 4411 # Simulator instruction rate (inst/s)
-host_op_rate 4411 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 74577 # Simulator tick rate (ticks/s)
-host_mem_usage 409256 # Number of bytes of host memory used
-host_seconds 1.45 # Real time elapsed on the host
+host_inst_rate 94410 # Simulator instruction rate (inst/s)
+host_op_rate 94397 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1595747 # Simulator tick rate (ticks/s)
+host_mem_usage 455808 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 75456 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 75456 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14656 # Number of bytes written to this memory
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 95729 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 108253 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 108253 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6413 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
+system.ruby.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
system.ruby.outstanding_req_hist_seqr::samples 8464
system.ruby.miss_latency_hist_seqr | 162 13.74% 13.74% | 996 84.48% 98.22% | 8 0.68% 98.90% | 4 0.34% 99.24% | 5 0.42% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 1179
system.ruby.Directory.incomplete_times_seqr 1178
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.L1Dcache.demand_hits 1313 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 737 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_hits 5767 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
system.ruby.l2_cntrl0.L2cache.demand_hits 187 # Number of cache demand hits
system.ruby.l2_cntrl0.L2cache.demand_misses 1196 # Number of cache demand misses
system.ruby.l2_cntrl0.L2cache.demand_accesses 1383 # Number of cache demand accesses
+system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.percent_links_utilized 6.022466
system.ruby.network.routers0.msg_count.Request_Control::1 1383
system.ruby.network.routers0.msg_count.Response_Data::4 1179
system.ruby.network.routers0.msg_bytes.Response_Control::4 8
system.ruby.network.routers0.msg_bytes.Writeback_Data::4 97560
system.ruby.network.routers0.msg_bytes.Persistent_Control::3 416
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
system.ruby.network.routers1.percent_links_utilized 4.541676
system.ruby.network.routers1.msg_count.Request_Control::1 1383
system.ruby.network.routers1.msg_count.Request_Control::2 1196
system.ruby.network.routers1.msg_bytes.Writeback_Data::4 114048
system.ruby.network.routers1.msg_bytes.Writeback_Control::4 7744
system.ruby.network.routers1.msg_bytes.Persistent_Control::3 208
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
system.ruby.network.routers2.percent_links_utilized 3.432237
system.ruby.network.routers2.msg_count.Request_Control::2 1196
system.ruby.network.routers2.msg_count.Response_Data::4 1179
system.ruby.network.routers2.msg_bytes.Writeback_Data::4 16488
system.ruby.network.routers2.msg_bytes.Writeback_Control::4 7744
system.ruby.network.routers2.msg_bytes.Persistent_Control::3 208
+system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
system.ruby.network.routers3.percent_links_utilized 4.665460
system.ruby.network.routers3.msg_count.Request_Control::1 1383
system.ruby.network.routers3.msg_count.Request_Control::2 1196
system.ruby.network.routers3.msg_bytes.Writeback_Data::4 114048
system.ruby.network.routers3.msg_bytes.Writeback_Control::4 7744
system.ruby.network.routers3.msg_bytes.Persistent_Control::3 416
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Request_Control 7737
system.ruby.network.msg_count.Response_Data 3537
system.ruby.network.msg_count.ResponseL2hit_Data 612
system.ruby.network.msg_byte.Writeback_Data 342144
system.ruby.network.msg_byte.Writeback_Control 23232
system.ruby.network.msg_byte.Persistent_Control 1248
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.throttle0.link_utilization 5.761503
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1179
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 204
sim_ticks 86770 # Number of ticks simulated
final_tick 86770 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 99240 # Simulator instruction rate (inst/s)
-host_op_rate 99218 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1344283 # Simulator tick rate (ticks/s)
-host_mem_usage 407932 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 95809 # Simulator instruction rate (inst/s)
+host_op_rate 95795 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1297998 # Simulator tick rate (ticks/s)
+host_mem_usage 453692 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 74240 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 74240 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14080 # Number of bytes written to this memory
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 82150 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 86770 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 86770 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6413 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
+system.ruby.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
system.ruby.outstanding_req_hist_seqr::samples 8464
system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits
system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses
system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.L1Dcache.demand_hits 1333 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 717 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses
system.ruby.l1_cntrl0.L2cache.demand_hits 203 # Number of cache demand hits
system.ruby.l1_cntrl0.L2cache.demand_misses 1160 # Number of cache demand misses
system.ruby.l1_cntrl0.L2cache.demand_accesses 1363 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.fully_busy_cycles 7 # cycles for which number of transistions == max transitions
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.percent_links_utilized 5.172295
system.ruby.network.routers0.msg_count.Request_Control::2 1160
system.ruby.network.routers0.msg_count.Response_Data::4 1160
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 9152
system.ruby.network.routers0.msg_bytes.Writeback_Control::5 7392
system.ruby.network.routers0.msg_bytes.Unblock_Control::5 9280
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
system.ruby.network.routers1.percent_links_utilized 5.172006
system.ruby.network.routers1.msg_count.Request_Control::2 1160
system.ruby.network.routers1.msg_count.Response_Data::4 1160
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 9152
system.ruby.network.routers1.msg_bytes.Writeback_Control::5 7392
system.ruby.network.routers1.msg_bytes.Unblock_Control::5 9272
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
system.ruby.network.routers2.percent_links_utilized 5.172295
system.ruby.network.routers2.msg_count.Request_Control::2 1160
system.ruby.network.routers2.msg_count.Response_Data::4 1160
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 9152
system.ruby.network.routers2.msg_bytes.Writeback_Control::5 7392
system.ruby.network.routers2.msg_bytes.Unblock_Control::5 9280
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Request_Control 3480
system.ruby.network.msg_count.Response_Data 3480
system.ruby.network.msg_count.Writeback_Data 660
system.ruby.network.msg_byte.Writeback_Data 47520
system.ruby.network.msg_byte.Writeback_Control 77088
system.ruby.network.msg_byte.Unblock_Control 27832
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.throttle0.link_utilization 6.675118
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1160
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1144
sim_ticks 107065 # Number of ticks simulated
final_tick 107065 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 109103 # Simulator instruction rate (inst/s)
-host_op_rate 109072 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1823360 # Simulator tick rate (ticks/s)
-host_mem_usage 411068 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 58028 # Simulator instruction rate (inst/s)
+host_op_rate 58023 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 970128 # Simulator tick rate (ticks/s)
+host_mem_usage 456600 # Number of bytes of host memory used
+host_seconds 0.11 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 110784 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 110784 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 110528 # Number of bytes written to this memory
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 92641 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 107065 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 107065 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6413 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
+system.ruby.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
system.ruby.delayHist::samples 3458 # delay histogram for all message
system.ruby.miss_latency_hist_seqr | 1488 85.96% 85.96% | 190 10.98% 96.94% | 41 2.37% 99.31% | 1 0.06% 99.36% | 6 0.35% 99.71% | 4 0.23% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 1731
system.ruby.Directory.incomplete_times_seqr 1730
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.cacheMemory.demand_hits 6732 # Number of cache demand hits
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1731 # Number of cache demand misses
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8463 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.percent_links_utilized 8.074534
system.ruby.network.routers0.msg_count.Control::2 1731
system.ruby.network.routers0.msg_count.Data::2 1727
system.ruby.network.routers0.msg_bytes.Data::2 124344
system.ruby.network.routers0.msg_bytes.Response_Data::4 124632
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13816
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
system.ruby.network.routers1.percent_links_utilized 8.074534
system.ruby.network.routers1.msg_count.Control::2 1731
system.ruby.network.routers1.msg_count.Data::2 1727
system.ruby.network.routers1.msg_bytes.Data::2 124344
system.ruby.network.routers1.msg_bytes.Response_Data::4 124632
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13816
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
system.ruby.network.routers2.percent_links_utilized 8.074534
system.ruby.network.routers2.msg_count.Control::2 1731
system.ruby.network.routers2.msg_count.Data::2 1727
system.ruby.network.routers2.msg_bytes.Data::2 124344
system.ruby.network.routers2.msg_bytes.Response_Data::4 124632
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 13816
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Control 5193
system.ruby.network.msg_count.Data 5181
system.ruby.network.msg_count.Response_Data 5193
system.ruby.network.msg_byte.Data 373032
system.ruby.network.msg_byte.Response_Data 373896
system.ruby.network.msg_byte.Writeback_Control 41448
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.throttle0.link_utilization 8.082006
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1731
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1727
sim_ticks 35682500 # Number of ticks simulated
final_tick 35682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 581025 # Simulator instruction rate (inst/s)
-host_op_rate 580437 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3231677275 # Simulator tick rate (ticks/s)
-host_mem_usage 247496 # Number of bytes of host memory used
+host_inst_rate 516760 # Simulator instruction rate (inst/s)
+host_op_rate 516348 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2875227341 # Simulator tick rate (ticks/s)
+host_mem_usage 291440 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory
system.physmem.bytes_read::total 28544 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 498619772 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 301324179 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 799943950 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 35682500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 71365 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6413 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 103.763836 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1882 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 4268 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4268 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 1090 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1090 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 127.232065 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 6135 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 13107 # Number of tag accesses
system.cpu.icache.tags.data_accesses 13107 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 6135 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 6135 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 6135 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 184.000496 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011383 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4022 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4022 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 373 # Transaction distribution
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
sim_ticks 20320000 # Number of ticks simulated
final_tick 20320000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 154508 # Simulator instruction rate (inst/s)
-host_op_rate 154391 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1212791416 # Simulator tick rate (ticks/s)
-host_mem_usage 246696 # Number of bytes of host memory used
+host_inst_rate 171591 # Simulator instruction rate (inst/s)
+host_op_rate 171481 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1347191282 # Simulator tick rate (ticks/s)
+host_mem_usage 293200 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
sim_insts 2585 # Number of instructions simulated
sim_ops 2585 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 20320000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory
system.physmem.bytes_read::total 19840 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 14869250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 20320000 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 794 # Number of BP lookups
system.cpu.branchPred.condPredicted 395 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 170 # Number of conditional branches incorrect
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 20320000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 40640 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class_0::total 2585 # Class of committed instruction
system.cpu.tickCycles 5416 # Number of cycles that the object actually ticked
system.cpu.idleCycles 35224 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20320000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 48.513757 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 693 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1679 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1679 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20320000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 442 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 442 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 251 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 76000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 76000 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20320000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 119.123012 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 750 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.109863 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 2175 # Number of tag accesses
system.cpu.icache.tags.data_accesses 2175 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20320000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 750 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 750 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 750 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 75457.777778 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75457.777778 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 75457.777778 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20320000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 147.162900 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008636 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 2790 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 2790 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 20320000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 225 # number of ReadCleanReq misses
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20320000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 20320000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 283 # Transaction distribution
system.membus.trans_dist::ReadExReq 27 # Transaction distribution
system.membus.trans_dist::ReadExResp 27 # Transaction distribution
sim_ticks 12409500 # Number of ticks simulated
final_tick 12409500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 87055 # Simulator instruction rate (inst/s)
-host_op_rate 87008 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 452104980 # Simulator tick rate (ticks/s)
-host_mem_usage 247976 # Number of bytes of host memory used
-host_seconds 0.03 # Real time elapsed on the host
+host_inst_rate 52563 # Simulator instruction rate (inst/s)
+host_op_rate 52553 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 273157641 # Simulator tick rate (ticks/s)
+host_mem_usage 293200 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
sim_insts 2387 # Number of instructions simulated
sim_ops 2387 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory
system.physmem.bytes_read::total 17408 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 7371500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 1003 # Number of BP lookups
system.cpu.branchPred.condPredicted 492 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 213 # Number of conditional branches incorrect
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 12409500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 24820 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fp_regfile_reads 6 # number of floating regfile reads
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 45.439304 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 735 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1919 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1919 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 522 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 522 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 78211.764706 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78211.764706 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 78211.764706 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 90.399218 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 625 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.091309 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 1943 # Number of tag accesses
system.cpu.icache.tags.data_accesses 1943 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 625 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 625 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 625 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 75724.593583 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75724.593583 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 75724.593583 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 119.261302 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.007568 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 2448 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 2448 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadExReq_misses::cpu.data 24 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 24 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 187 # number of ReadCleanReq misses
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 248 # Transaction distribution
system.membus.trans_dist::ReadExReq 24 # Transaction distribution
system.membus.trans_dist::ReadExResp 24 # Transaction distribution
sim_ticks 1297500 # Number of ticks simulated
final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 461545 # Simulator instruction rate (inst/s)
-host_op_rate 460635 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 231518490 # Simulator tick rate (ticks/s)
-host_mem_usage 237472 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
+host_inst_rate 615280 # Simulator instruction rate (inst/s)
+host_op_rate 613973 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 308554926 # Simulator tick rate (ticks/s)
+host_mem_usage 281160 # Number of bytes of host memory used
+host_seconds 0.00 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1297500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 3016 # Number of bytes read from this memory
system.physmem.bytes_read::total 13356 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7969171484 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3910597303 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11879768786 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 1297500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 1297500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 2596 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 2585 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 1297500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 3000 # Transaction distribution
system.membus.trans_dist::ReadResp 3000 # Transaction distribution
system.membus.trans_dist::WriteReq 294 # Transaction distribution
sim_ticks 45733 # Number of ticks simulated
final_tick 45733 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 63739 # Simulator instruction rate (inst/s)
-host_op_rate 63721 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1130531 # Simulator tick rate (ticks/s)
-host_mem_usage 407420 # Number of bytes of host memory used
+host_inst_rate 61876 # Simulator instruction rate (inst/s)
+host_op_rate 61863 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1097622 # Simulator tick rate (ticks/s)
+host_mem_usage 452416 # Number of bytes of host memory used
host_seconds 0.04 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 35008 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 35008 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 6592 # Number of bytes written to this memory
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 37150 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 45733 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 45733 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 2585 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
+system.ruby.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
system.ruby.delayHist::samples 3612 # delay histogram for all message
system.ruby.miss_latency_hist_seqr::stdev 30.458568
system.ruby.miss_latency_hist_seqr | 134 23.43% 23.43% | 432 75.52% 98.95% | 1 0.17% 99.13% | 0 0.00% 99.13% | 1 0.17% 99.30% | 4 0.70% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 572
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.L1Dcache.demand_hits 437 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 272 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses
system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states
system.ruby.l2_cntrl0.L2cache.demand_hits 25 # Number of cache demand hits
system.ruby.l2_cntrl0.L2cache.demand_misses 547 # Number of cache demand misses
system.ruby.l2_cntrl0.L2cache.demand_accesses 572 # Number of cache demand accesses
+system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.percent_links_utilized 4.350250
system.ruby.network.routers0.msg_count.Control::0 572
system.ruby.network.routers0.msg_count.Request_Control::2 431
system.ruby.network.routers0.msg_bytes.Writeback_Data::0 3240
system.ruby.network.routers0.msg_bytes.Writeback_Data::1 4464
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 632
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states
system.ruby.network.routers1.percent_links_utilized 8.380163
system.ruby.network.routers1.msg_count.Control::0 1119
system.ruby.network.routers1.msg_count.Request_Control::2 431
system.ruby.network.routers1.msg_bytes.Writeback_Data::0 3240
system.ruby.network.routers1.msg_bytes.Writeback_Data::1 4464
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 632
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states
system.ruby.network.routers2.percent_links_utilized 4.029913
system.ruby.network.routers2.msg_count.Control::0 547
system.ruby.network.routers2.msg_count.Response_Data::1 650
system.ruby.network.routers2.msg_bytes.Control::0 4376
system.ruby.network.routers2.msg_bytes.Response_Data::1 46800
system.ruby.network.routers2.msg_bytes.Response_Control::1 7800
+system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states
system.ruby.network.routers3.percent_links_utilized 5.586775
system.ruby.network.routers3.msg_count.Control::0 1119
system.ruby.network.routers3.msg_count.Request_Control::2 431
system.ruby.network.routers3.msg_bytes.Writeback_Data::0 3240
system.ruby.network.routers3.msg_bytes.Writeback_Data::1 4464
system.ruby.network.routers3.msg_bytes.Writeback_Control::0 632
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Control 3357
system.ruby.network.msg_count.Request_Control 1293
system.ruby.network.msg_count.Response_Data 3666
system.ruby.network.msg_byte.Response_Control 41760
system.ruby.network.msg_byte.Writeback_Data 23112
system.ruby.network.msg_byte.Writeback_Control 1896
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.throttle0.link_utilization 6.235104
system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 431
system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 572
sim_ticks 41712 # Number of ticks simulated
final_tick 41712 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 64355 # Simulator instruction rate (inst/s)
-host_op_rate 64336 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1041083 # Simulator tick rate (ticks/s)
-host_mem_usage 410320 # Number of bytes of host memory used
+host_inst_rate 62826 # Simulator instruction rate (inst/s)
+host_op_rate 62813 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1016484 # Simulator tick rate (ticks/s)
+host_mem_usage 457644 # Number of bytes of host memory used
host_seconds 0.04 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 29696 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 29696 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 4992 # Number of bytes written to this memory
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 37281 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 41712 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 41712 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 2585 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
+system.ruby.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
system.ruby.outstanding_req_hist_seqr::samples 3295
system.ruby.miss_latency_hist_seqr::stdev 31.323348
system.ruby.miss_latency_hist_seqr | 80 14.71% 14.71% | 80 14.71% 29.41% | 359 65.99% 95.40% | 18 3.31% 98.71% | 2 0.37% 99.08% | 0 0.00% 99.08% | 1 0.18% 99.26% | 0 0.00% 99.26% | 1 0.18% 99.45% | 3 0.55% 100.00%
system.ruby.miss_latency_hist_seqr::total 544
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.L1Dcache.demand_hits 435 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 274 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states
system.ruby.l2_cntrl0.L2cache.demand_hits 80 # Number of cache demand hits
system.ruby.l2_cntrl0.L2cache.demand_misses 464 # Number of cache demand misses
system.ruby.l2_cntrl0.L2cache.demand_accesses 544 # Number of cache demand accesses
+system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.percent_links_utilized 6.800201
system.ruby.network.routers0.msg_count.Request_Control::0 544
system.ruby.network.routers0.msg_count.Response_Data::2 464
system.ruby.network.routers0.msg_bytes.Writeback_Data::2 34704
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 8032
system.ruby.network.routers0.msg_bytes.Unblock_Control::2 4512
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states
system.ruby.network.routers1.percent_links_utilized 10.372914
system.ruby.network.routers1.msg_count.Request_Control::0 544
system.ruby.network.routers1.msg_count.Request_Control::1 464
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 8032
system.ruby.network.routers1.msg_bytes.Writeback_Control::1 1248
system.ruby.network.routers1.msg_bytes.Unblock_Control::2 8216
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states
system.ruby.network.routers2.percent_links_utilized 3.572713
system.ruby.network.routers2.msg_count.Request_Control::1 464
system.ruby.network.routers2.msg_count.Response_Data::2 464
system.ruby.network.routers2.msg_bytes.Writeback_Data::2 5616
system.ruby.network.routers2.msg_bytes.Writeback_Control::1 1248
system.ruby.network.routers2.msg_bytes.Unblock_Control::2 3704
+system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states
system.ruby.network.routers3.percent_links_utilized 6.915276
system.ruby.network.routers3.msg_count.Request_Control::0 544
system.ruby.network.routers3.msg_count.Request_Control::1 464
system.ruby.network.routers3.msg_bytes.Writeback_Control::0 8032
system.ruby.network.routers3.msg_bytes.Writeback_Control::1 1248
system.ruby.network.routers3.msg_bytes.Unblock_Control::2 8216
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Request_Control 3024
system.ruby.network.msg_count.Response_Data 2784
system.ruby.network.msg_count.ResponseL2hit_Data 240
system.ruby.network.msg_byte.Writeback_Data 120960
system.ruby.network.msg_byte.Writeback_Control 27840
system.ruby.network.msg_byte.Unblock_Control 24648
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.throttle0.link_utilization 6.470560
system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 464
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 80
sim_ticks 40527 # Number of ticks simulated
final_tick 40527 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 1955 # Simulator instruction rate (inst/s)
-host_op_rate 1955 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 30751 # Simulator tick rate (ticks/s)
-host_mem_usage 407948 # Number of bytes of host memory used
-host_seconds 1.32 # Real time elapsed on the host
+host_inst_rate 89328 # Simulator instruction rate (inst/s)
+host_op_rate 89293 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1403832 # Simulator tick rate (ticks/s)
+host_mem_usage 454496 # Number of bytes of host memory used
+host_seconds 0.03 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 28672 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 28672 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 5376 # Number of bytes written to this memory
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 37083 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 40527 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 40527 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 2585 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
+system.ruby.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
system.ruby.outstanding_req_hist_seqr::samples 3295
system.ruby.miss_latency_hist_seqr | 73 16.29% 16.29% | 368 82.14% 98.44% | 2 0.45% 98.88% | 0 0.00% 98.88% | 3 0.67% 99.55% | 2 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 448
system.ruby.Directory.incomplete_times_seqr 447
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.L1Dcache.demand_hits 461 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 248 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states
system.ruby.l2_cntrl0.L2cache.demand_hits 64 # Number of cache demand hits
system.ruby.l2_cntrl0.L2cache.demand_misses 454 # Number of cache demand misses
system.ruby.l2_cntrl0.L2cache.demand_accesses 518 # Number of cache demand accesses
+system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.percent_links_utilized 5.992918
system.ruby.network.routers0.msg_count.Request_Control::1 518
system.ruby.network.routers0.msg_count.Response_Data::4 448
system.ruby.network.routers0.msg_bytes.Response_Control::4 8
system.ruby.network.routers0.msg_bytes.Writeback_Data::4 36144
system.ruby.network.routers0.msg_bytes.Persistent_Control::3 128
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states
system.ruby.network.routers1.percent_links_utilized 4.472327
system.ruby.network.routers1.msg_count.Request_Control::1 518
system.ruby.network.routers1.msg_count.Request_Control::2 454
system.ruby.network.routers1.msg_bytes.Writeback_Data::4 42192
system.ruby.network.routers1.msg_bytes.Writeback_Control::4 2920
system.ruby.network.routers1.msg_bytes.Persistent_Control::3 64
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states
system.ruby.network.routers2.percent_links_utilized 3.463740
system.ruby.network.routers2.msg_count.Request_Control::2 454
system.ruby.network.routers2.msg_count.Response_Data::4 448
system.ruby.network.routers2.msg_bytes.Writeback_Data::4 6048
system.ruby.network.routers2.msg_bytes.Writeback_Control::4 2920
system.ruby.network.routers2.msg_bytes.Persistent_Control::3 64
+system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states
system.ruby.network.routers3.percent_links_utilized 4.642995
system.ruby.network.routers3.msg_count.Request_Control::1 518
system.ruby.network.routers3.msg_count.Request_Control::2 454
system.ruby.network.routers3.msg_bytes.Writeback_Data::4 42192
system.ruby.network.routers3.msg_bytes.Writeback_Control::4 2920
system.ruby.network.routers3.msg_bytes.Persistent_Control::3 128
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Request_Control 2916
system.ruby.network.msg_count.Response_Data 1344
system.ruby.network.msg_count.ResponseL2hit_Data 210
system.ruby.network.msg_byte.Writeback_Data 126576
system.ruby.network.msg_byte.Writeback_Control 8760
system.ruby.network.msg_byte.Persistent_Control 384
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.throttle0.link_utilization 5.762825
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 448
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 70
sim_ticks 32936 # Number of ticks simulated
final_tick 32936 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 83066 # Simulator instruction rate (inst/s)
-host_op_rate 82987 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1059779 # Simulator tick rate (ticks/s)
-host_mem_usage 407644 # Number of bytes of host memory used
+host_inst_rate 91605 # Simulator instruction rate (inst/s)
+host_op_rate 91573 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1170024 # Simulator tick rate (ticks/s)
+host_mem_usage 453424 # Number of bytes of host memory used
host_seconds 0.03 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 28224 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 28224 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 5184 # Number of bytes written to this memory
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 29634 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 32936 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 32936 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 2585 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
+system.ruby.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
system.ruby.outstanding_req_hist_seqr::samples 3295
system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits
system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses
system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.L1Dcache.demand_hits 469 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 240 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses
system.ruby.l1_cntrl0.L2cache.demand_hits 69 # Number of cache demand hits
system.ruby.l1_cntrl0.L2cache.demand_misses 441 # Number of cache demand misses
system.ruby.l1_cntrl0.L2cache.demand_accesses 510 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.fully_busy_cycles 5 # cycles for which number of transistions == max transitions
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.percent_links_utilized 5.141031
system.ruby.network.routers0.msg_count.Request_Control::2 441
system.ruby.network.routers0.msg_count.Response_Data::4 441
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 3400
system.ruby.network.routers0.msg_bytes.Writeback_Control::5 2752
system.ruby.network.routers0.msg_bytes.Unblock_Control::5 3520
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states
system.ruby.network.routers1.percent_links_utilized 5.141031
system.ruby.network.routers1.msg_count.Request_Control::2 441
system.ruby.network.routers1.msg_count.Response_Data::4 441
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 3400
system.ruby.network.routers1.msg_bytes.Writeback_Control::5 2752
system.ruby.network.routers1.msg_bytes.Unblock_Control::5 3520
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states
system.ruby.network.routers2.percent_links_utilized 5.141031
system.ruby.network.routers2.msg_count.Request_Control::2 441
system.ruby.network.routers2.msg_count.Response_Data::4 441
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 3400
system.ruby.network.routers2.msg_bytes.Writeback_Control::5 2752
system.ruby.network.routers2.msg_bytes.Unblock_Control::5 3520
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Request_Control 1323
system.ruby.network.msg_count.Response_Data 1323
system.ruby.network.msg_count.Writeback_Data 243
system.ruby.network.msg_byte.Writeback_Data 17496
system.ruby.network.msg_byte.Writeback_Control 28656
system.ruby.network.msg_byte.Unblock_Control 10560
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.throttle0.link_utilization 6.670513
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 441
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 425
sim_ticks 41659 # Number of ticks simulated
final_tick 41659 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 92225 # Simulator instruction rate (inst/s)
-host_op_rate 92177 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1489374 # Simulator tick rate (ticks/s)
-host_mem_usage 407716 # Number of bytes of host memory used
-host_seconds 0.03 # Real time elapsed on the host
+host_inst_rate 54027 # Simulator instruction rate (inst/s)
+host_op_rate 54016 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 873053 # Simulator tick rate (ticks/s)
+host_mem_usage 453224 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 40064 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 40064 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 39808 # Number of bytes written to this memory
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 37357 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 41659 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 41659 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 2585 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
+system.ruby.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
system.ruby.delayHist::samples 1248 # delay histogram for all message
system.ruby.miss_latency_hist_seqr | 517 82.59% 82.59% | 90 14.38% 96.96% | 14 2.24% 99.20% | 0 0.00% 99.20% | 2 0.32% 99.52% | 3 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 626
system.ruby.Directory.incomplete_times_seqr 625
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.cacheMemory.demand_hits 2668 # Number of cache demand hits
system.ruby.l1_cntrl0.cacheMemory.demand_misses 626 # Number of cache demand misses
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 3294 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.percent_links_utilized 7.489378
system.ruby.network.routers0.msg_count.Control::2 626
system.ruby.network.routers0.msg_count.Data::2 622
system.ruby.network.routers0.msg_bytes.Data::2 44784
system.ruby.network.routers0.msg_bytes.Response_Data::4 45072
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 4976
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states
system.ruby.network.routers1.percent_links_utilized 7.489378
system.ruby.network.routers1.msg_count.Control::2 626
system.ruby.network.routers1.msg_count.Data::2 622
system.ruby.network.routers1.msg_bytes.Data::2 44784
system.ruby.network.routers1.msg_bytes.Response_Data::4 45072
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 4976
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states
system.ruby.network.routers2.percent_links_utilized 7.489378
system.ruby.network.routers2.msg_count.Control::2 626
system.ruby.network.routers2.msg_count.Data::2 622
system.ruby.network.routers2.msg_bytes.Data::2 44784
system.ruby.network.routers2.msg_bytes.Response_Data::4 45072
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 4976
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Control 1878
system.ruby.network.msg_count.Data 1866
system.ruby.network.msg_count.Response_Data 1878
system.ruby.network.msg_byte.Data 134352
system.ruby.network.msg_byte.Response_Data 135216
system.ruby.network.msg_byte.Writeback_Control 14928
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.throttle0.link_utilization 7.508582
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 626
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 622
sim_ticks 18239500 # Number of ticks simulated
final_tick 18239500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 339288 # Simulator instruction rate (inst/s)
-host_op_rate 338780 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2394585777 # Simulator tick rate (ticks/s)
-host_mem_usage 246188 # Number of bytes of host memory used
+host_inst_rate 346390 # Simulator instruction rate (inst/s)
+host_op_rate 345952 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2445638693 # Simulator tick rate (ticks/s)
+host_mem_usage 291156 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 10432 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5248 # Number of bytes read from this memory
system.physmem.bytes_read::total 15680 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 571945503 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 287727186 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 859672688 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 18239500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 36479 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 2585 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 47.277997 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.020020 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1500 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1500 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 79.677134 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.079590 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 5335 # Number of tag accesses
system.cpu.icache.tags.data_accesses 5335 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 61003.067485 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61003.067485 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 61003.067485 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 106.649585 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.006653 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 2205 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 2205 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 163 # number of ReadCleanReq misses
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 123000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 218 # Transaction distribution
system.membus.trans_dist::ReadExReq 27 # Transaction distribution
system.membus.trans_dist::ReadExResp 27 # Transaction distribution
sim_ticks 29977500 # Number of ticks simulated
final_tick 29977500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 146522 # Simulator instruction rate (inst/s)
-host_op_rate 171470 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 953185288 # Simulator tick rate (ticks/s)
-host_mem_usage 264656 # Number of bytes of host memory used
+host_inst_rate 147440 # Simulator instruction rate (inst/s)
+host_op_rate 172555 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 959274014 # Simulator tick rate (ticks/s)
+host_mem_usage 309288 # Number of bytes of host memory used
host_seconds 0.03 # Real time elapsed on the host
sim_insts 4605 # Number of instructions simulated
sim_ops 5391 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory
system.physmem.bytes_read::total 26944 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 22324250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 1949 # Number of BP lookups
system.cpu.branchPred.condPredicted 1165 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 351 # Number of conditional branches incorrect
system.cpu.branchPred.indirectMisses 125 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 62 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 29977500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 59955 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class_0::total 5391 # Class of committed instruction
system.cpu.tickCycles 10654 # Number of cycles that the object actually ticked
system.cpu.idleCycles 49301 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 86.495507 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1916 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 4342 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4342 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 65510.273973 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65510.273973 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 65510.273973 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 4 # number of replacements
system.cpu.icache.tags.tagsinuse 162.122030 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1926 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 4821 # Number of tag accesses
system.cpu.icache.tags.data_accesses 4821 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 1926 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1926 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1926 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 71848.297214 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71848.297214 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 71848.297214 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 195.781809 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 43 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4197 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4197 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 426 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 222992 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 378 # Transaction distribution
system.membus.trans_dist::ReadExReq 43 # Transaction distribution
system.membus.trans_dist::ReadExResp 43 # Transaction distribution
sim_ticks 17232500 # Number of ticks simulated
final_tick 17232500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 74741 # Simulator instruction rate (inst/s)
-host_op_rate 87520 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 280399381 # Simulator tick rate (ticks/s)
-host_mem_usage 309668 # Number of bytes of host memory used
+host_inst_rate 78702 # Simulator instruction rate (inst/s)
+host_op_rate 92158 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 295258113 # Simulator tick rate (ticks/s)
+host_mem_usage 310332 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
sim_insts 4592 # Number of instructions simulated
sim_ops 5378 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory
system.physmem.bytes_read::total 25408 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 14752750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 2837 # Number of BP lookups
system.cpu.branchPred.condPredicted 1744 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 464 # Number of conditional branches incorrect
system.cpu.branchPred.indirectMisses 251 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.hits 0 # DTB hits
system.cpu.checker.dtb.misses 0 # DTB misses
system.cpu.checker.dtb.accesses 0 # DTB accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
system.cpu.checker.itb.walker.walks 0 # Table walker walks requested
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.misses 0 # DTB misses
system.cpu.checker.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
+system.cpu.checker.pwrStateResidencyTicks::ON 17232500 # Cumulative time (in ticks) in various power states
system.cpu.checker.numCycles 5391 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.pwrStateResidencyTicks::ON 17232500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 34466 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.cc_regfile_writes 3276 # number of cc regfile writes
system.cpu.misc_regfile_reads 2978 # number of misc regfile reads
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 88.359063 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 2095 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 5339 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 5339 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70870.748299 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 2 # number of replacements
system.cpu.icache.tags.tagsinuse 150.405898 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 4216 # Number of tag accesses
system.cpu.icache.tags.data_accesses 4216 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 1577 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1577 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1577 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73923.469388 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 187.999052 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010834 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 3933 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 3933 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 399 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 223494 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 355 # Transaction distribution
system.membus.trans_dist::ReadExReq 42 # Transaction distribution
system.membus.trans_dist::ReadExResp 42 # Transaction distribution
sim_ticks 18821000 # Number of ticks simulated
final_tick 18821000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 77535 # Simulator instruction rate (inst/s)
-host_op_rate 90790 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 317684946 # Simulator tick rate (ticks/s)
-host_mem_usage 305172 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 84019 # Simulator instruction rate (inst/s)
+host_op_rate 98384 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 344256847 # Simulator tick rate (ticks/s)
+host_mem_usage 306884 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
sim_insts 4592 # Number of instructions simulated
sim_ops 5378 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 18560 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8064 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 15229250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 2438 # Number of BP lookups
system.cpu.branchPred.condPredicted 1442 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 524 # Number of conditional branches incorrect
system.cpu.branchPred.indirectMisses 150 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 60 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 18821000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 37643 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.cc_regfile_writes 2921 # number of cc regfile writes
system.cpu.misc_regfile_reads 2562 # number of misc regfile reads
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 1 # number of replacements
system.cpu.dcache.tags.tagsinuse 84.368926 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1930 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 4723 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4723 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 1188 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1188 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 65048.611111 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65048.611111 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 65048.611111 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 44 # number of replacements
system.cpu.icache.tags.tagsinuse 137.890102 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 3540 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 8101 # Number of tag accesses
system.cpu.icache.tags.data_accesses 8101 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 3540 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 3540 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 3540 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 66140.441472 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66140.441472 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 66140.441472 # average overall mshr miss latency
+system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 19.806308 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 11 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.001953 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 7675 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 7675 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 33 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 411 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 370 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 41 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 45 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 385 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 216995 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 412 # Transaction distribution
system.membus.trans_dist::ReadExReq 30 # Transaction distribution
system.membus.trans_dist::ReadExResp 30 # Transaction distribution
sim_ticks 2695000 # Number of ticks simulated
final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 555825 # Simulator instruction rate (inst/s)
-host_op_rate 650110 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 325439975 # Simulator tick rate (ticks/s)
-host_mem_usage 298640 # Number of bytes of host memory used
+host_inst_rate 569364 # Simulator instruction rate (inst/s)
+host_op_rate 666035 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 333433301 # Simulator tick rate (ticks/s)
+host_mem_usage 299296 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 4592 # Number of instructions simulated
sim_ops 5378 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 18420 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory
system.physmem.bytes_read::total 22911 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 6834879406 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3020037106 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9854916512 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states
system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.hits 0 # DTB hits
system.cpu.checker.dtb.misses 0 # DTB misses
system.cpu.checker.dtb.accesses 0 # DTB accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states
system.cpu.checker.itb.walker.walks 0 # Table walker walks requested
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.misses 0 # DTB misses
system.cpu.checker.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
+system.cpu.checker.pwrStateResidencyTicks::ON 2695000 # Cumulative time (in ticks) in various power states
system.cpu.checker.numCycles 0 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.pwrStateResidencyTicks::ON 2695000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 5391 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5391 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 5597 # Transaction distribution
system.membus.trans_dist::ReadResp 5608 # Transaction distribution
system.membus.trans_dist::WriteReq 913 # Transaction distribution
sim_ticks 2695000 # Number of ticks simulated
final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 589705 # Simulator instruction rate (inst/s)
-host_op_rate 689852 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 345334530 # Simulator tick rate (ticks/s)
-host_mem_usage 297616 # Number of bytes of host memory used
+host_inst_rate 625339 # Simulator instruction rate (inst/s)
+host_op_rate 731490 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 366164896 # Simulator tick rate (ticks/s)
+host_mem_usage 298280 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 4592 # Number of instructions simulated
sim_ops 5378 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 18420 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory
system.physmem.bytes_read::total 22911 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 6834879406 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3020037106 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9854916512 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 2695000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 5391 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5391 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 5597 # Transaction distribution
system.membus.trans_dist::ReadResp 5608 # Transaction distribution
system.membus.trans_dist::WriteReq 913 # Transaction distribution
sim_ticks 28298500 # Number of ticks simulated
final_tick 28298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 311400 # Simulator instruction rate (inst/s)
-host_op_rate 363255 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1927478424 # Simulator tick rate (ticks/s)
-host_mem_usage 306584 # Number of bytes of host memory used
+host_inst_rate 377704 # Simulator instruction rate (inst/s)
+host_op_rate 440559 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2337429945 # Simulator tick rate (ticks/s)
+host_mem_usage 308268 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 4566 # Number of instructions simulated
sim_ops 5330 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory
system.physmem.bytes_read::total 22400 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 508860894 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 282700496 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 791561390 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 28298500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 56597 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5391 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 82.647245 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 1 # number of replacements
system.cpu.icache.tags.tagsinuse 114.043293 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 9453 # Number of tag accesses
system.cpu.icache.tags.data_accesses 9453 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 4365 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 4365 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 4365 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 153.328645 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 3406 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 16 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 307 # Transaction distribution
system.membus.trans_dist::ReadExReq 43 # Transaction distribution
system.membus.trans_dist::ReadExResp 43 # Transaction distribution
sim_ticks 22532000 # Number of ticks simulated
final_tick 22532000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 96442 # Simulator instruction rate (inst/s)
-host_op_rate 96403 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 434426491 # Simulator tick rate (ticks/s)
-host_mem_usage 247240 # Number of bytes of host memory used
+host_inst_rate 107418 # Simulator instruction rate (inst/s)
+host_op_rate 107396 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 483974405 # Simulator tick rate (ticks/s)
+host_mem_usage 292720 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
sim_insts 4999 # Number of instructions simulated
sim_ops 4999 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 21056 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory
system.physmem.bytes_read::total 30016 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 15222750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 2183 # Number of BP lookups
system.cpu.branchPred.condPredicted 1455 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 425 # Number of conditional branches incorrect
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 7 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 22532000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 45065 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fp_regfile_reads 3 # number of floating regfile reads
system.cpu.fp_regfile_writes 1 # number of floating regfile writes
system.cpu.misc_regfile_reads 160 # number of misc regfile reads
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 90.625823 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 2393 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 5950 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 5950 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 1837 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1837 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 556 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 83092.850000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83092.850000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 83092.850000 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 17 # number of replacements
system.cpu.icache.tags.tagsinuse 158.780297 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1610 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.153809 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 4426 # Number of tag accesses
system.cpu.icache.tags.data_accesses 4426 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 1610 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1610 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1610 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 78480.421687 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78480.421687 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 78480.421687 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 218.003826 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012787 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4381 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4381 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackClean_hits::writebacks 17 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 17 # number of WritebackClean hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 17 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 210000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 419 # Transaction distribution
system.membus.trans_dist::ReadExReq 50 # Transaction distribution
system.membus.trans_dist::ReadExResp 50 # Transaction distribution
sim_ticks 2820500 # Number of ticks simulated
final_tick 2820500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 876414 # Simulator instruction rate (inst/s)
-host_op_rate 873362 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 435104956 # Simulator tick rate (ticks/s)
-host_mem_usage 235716 # Number of bytes of host memory used
+host_inst_rate 743339 # Simulator instruction rate (inst/s)
+host_op_rate 742439 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 370817863 # Simulator tick rate (ticks/s)
+host_mem_usage 279644 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 5641 # Number of instructions simulated
sim_ops 5641 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2820500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 22568 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 4301 # Number of bytes read from this memory
system.physmem.bytes_read::total 26869 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 8001418188 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2801630917 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10803049105 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 2820500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 7 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 2820500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 5642 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5642 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 2820500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 6777 # Transaction distribution
system.membus.trans_dist::ReadResp 6777 # Transaction distribution
system.membus.trans_dist::WriteReq 901 # Transaction distribution
sim_ticks 100232 # Number of ticks simulated
final_tick 100232 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 97717 # Simulator instruction rate (inst/s)
-host_op_rate 97699 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1735645 # Simulator tick rate (ticks/s)
-host_mem_usage 410048 # Number of bytes of host memory used
+host_inst_rate 93908 # Simulator instruction rate (inst/s)
+host_op_rate 93894 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1668107 # Simulator tick rate (ticks/s)
+host_mem_usage 455812 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
sim_insts 5641 # Number of instructions simulated
sim_ops 5641 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 94208 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 94208 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 93952 # Number of bytes written to this memory
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 90404 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 7 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 100232 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 100232 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5642 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
+system.ruby.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
system.ruby.delayHist::samples 2940 # delay histogram for all message
system.ruby.miss_latency_hist_seqr | 1166 79.21% 79.21% | 253 17.19% 96.40% | 37 2.51% 98.91% | 4 0.27% 99.18% | 6 0.41% 99.59% | 5 0.34% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 1472
system.ruby.Directory.incomplete_times_seqr 1471
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.cacheMemory.demand_hits 6206 # Number of cache demand hits
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1472 # Number of cache demand misses
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7678 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.percent_links_utilized 7.332987
system.ruby.network.routers0.msg_count.Control::2 1472
system.ruby.network.routers0.msg_count.Data::2 1468
system.ruby.network.routers0.msg_bytes.Data::2 105696
system.ruby.network.routers0.msg_bytes.Response_Data::4 105984
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11744
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states
system.ruby.network.routers1.percent_links_utilized 7.332987
system.ruby.network.routers1.msg_count.Control::2 1472
system.ruby.network.routers1.msg_count.Data::2 1468
system.ruby.network.routers1.msg_bytes.Data::2 105696
system.ruby.network.routers1.msg_bytes.Response_Data::4 105984
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11744
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states
system.ruby.network.routers2.percent_links_utilized 7.332987
system.ruby.network.routers2.msg_count.Control::2 1472
system.ruby.network.routers2.msg_count.Data::2 1468
system.ruby.network.routers2.msg_bytes.Data::2 105696
system.ruby.network.routers2.msg_bytes.Response_Data::4 105984
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 11744
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Control 4416
system.ruby.network.msg_count.Data 4404
system.ruby.network.msg_count.Response_Data 4416
system.ruby.network.msg_byte.Data 317088
system.ruby.network.msg_byte.Response_Data 317952
system.ruby.network.msg_byte.Writeback_Control 35232
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.throttle0.link_utilization 7.340969
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1472
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1468
sim_ticks 33932500 # Number of ticks simulated
final_tick 33932500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 431758 # Simulator instruction rate (inst/s)
-host_op_rate 430982 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2588300068 # Simulator tick rate (ticks/s)
-host_mem_usage 244424 # Number of bytes of host memory used
+host_inst_rate 497160 # Simulator instruction rate (inst/s)
+host_op_rate 496749 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2985875640 # Simulator tick rate (ticks/s)
+host_mem_usage 289632 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 5641 # Number of instructions simulated
sim_ops 5641 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 18752 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8768 # Number of bytes read from this memory
system.physmem.bytes_read::total 27520 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 552626538 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 258395344 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 811021882 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 7 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 33932500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 67865 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5642 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 86.030444 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4209 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 13 # number of replacements
system.cpu.icache.tags.tagsinuse 128.953338 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 5348 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.137695 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 11581 # Number of tag accesses
system.cpu.icache.tags.data_accesses 11581 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 5348 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 5348 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 5348 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 183.490494 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011597 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 3990 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 3990 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackClean_hits::writebacks 13 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 13 # number of WritebackClean hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 13 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 205500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 380 # Transaction distribution
system.membus.trans_dist::ReadExReq 50 # Transaction distribution
system.membus.trans_dist::ReadExResp 50 # Transaction distribution
sim_ticks 19908000 # Number of ticks simulated
final_tick 19908000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 120043 # Simulator instruction rate (inst/s)
-host_op_rate 120013 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 412413617 # Simulator tick rate (ticks/s)
-host_mem_usage 245176 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
+host_inst_rate 67828 # Simulator instruction rate (inst/s)
+host_op_rate 67820 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 233087583 # Simulator tick rate (ticks/s)
+host_mem_usage 290888 # Number of bytes of host memory used
+host_seconds 0.09 # Real time elapsed on the host
sim_insts 5792 # Number of instructions simulated
sim_ops 5792 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 21952 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 6400 # Number of bytes read from this memory
system.physmem.bytes_read::total 28352 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 10721750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 2407 # Number of BP lookups
system.cpu.branchPred.condPredicted 1979 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 409 # Number of conditional branches incorrect
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 9 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 19908000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 39817 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.int_regfile_writes 7150 # number of integer regfile writes
system.cpu.fp_regfile_reads 25 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 64.466372 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 2199 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 5374 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 5374 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 81139.403846 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81139.403846 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 81139.403846 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 169.073673 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1420 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 4061 # Number of tag accesses
system.cpu.icache.tags.data_accesses 4061 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 1420 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1420 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1420 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 75925.714286 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75925.714286 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 75925.714286 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 199.665471 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 8 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012085 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4075 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4075 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 6 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 6 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 153000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 396 # Transaction distribution
system.membus.trans_dist::ReadExReq 47 # Transaction distribution
system.membus.trans_dist::ReadExResp 47 # Transaction distribution
sim_ticks 2896000 # Number of ticks simulated
final_tick 2896000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 887311 # Simulator instruction rate (inst/s)
-host_op_rate 885785 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 442112700 # Simulator tick rate (ticks/s)
-host_mem_usage 234416 # Number of bytes of host memory used
+host_inst_rate 806520 # Simulator instruction rate (inst/s)
+host_op_rate 805428 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 402167874 # Simulator tick rate (ticks/s)
+host_mem_usage 277804 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 5793 # Number of instructions simulated
sim_ops 5793 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2896000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 23172 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 3720 # Number of bytes read from this memory
system.physmem.bytes_read::total 26892 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 8001381215 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2737914365 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10739295580 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 2896000 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 9 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 2896000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 5793 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5793 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 2896000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 6754 # Transaction distribution
system.membus.trans_dist::ReadResp 6754 # Transaction distribution
system.membus.trans_dist::WriteReq 1046 # Transaction distribution
sim_ticks 2694500 # Number of ticks simulated
final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 633206 # Simulator instruction rate (inst/s)
-host_op_rate 631372 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 318532177 # Simulator tick rate (ticks/s)
-host_mem_usage 236156 # Number of bytes of host memory used
+host_inst_rate 770174 # Simulator instruction rate (inst/s)
+host_op_rate 769174 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 388618840 # Simulator tick rate (ticks/s)
+host_mem_usage 281084 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2694500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 21480 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 4602 # Number of bytes read from this memory
system.physmem.bytes_read::total 26082 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7971794396 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3587678605 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11559473001 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 2694500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 11 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 2694500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 5390 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5370 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 2694500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 6085 # Transaction distribution
system.membus.trans_dist::ReadResp 6085 # Transaction distribution
system.membus.trans_dist::WriteReq 673 # Transaction distribution
sim_ticks 81703 # Number of ticks simulated
final_tick 81703 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 79389 # Simulator instruction rate (inst/s)
-host_op_rate 79372 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1217125 # Simulator tick rate (ticks/s)
-host_mem_usage 409468 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
+host_inst_rate 107011 # Simulator instruction rate (inst/s)
+host_op_rate 106993 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1640735 # Simulator tick rate (ticks/s)
+host_mem_usage 456212 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 82496 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 82496 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 82240 # Number of bytes written to this memory
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 64875 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.workload.num_syscalls 11 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 81703 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 81703 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5370 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
+system.ruby.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
system.ruby.delayHist::samples 2574 # delay histogram for all message
system.ruby.miss_latency_hist_seqr | 1082 83.94% 83.94% | 169 13.11% 97.05% | 28 2.17% 99.22% | 2 0.16% 99.38% | 5 0.39% 99.77% | 2 0.16% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 1289
system.ruby.Directory.incomplete_times_seqr 1288
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 # Number of cache demand hits
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 # Number of cache demand misses
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.percent_links_utilized 7.876088
system.ruby.network.routers0.msg_count.Control::2 1289
system.ruby.network.routers0.msg_count.Data::2 1285
system.ruby.network.routers0.msg_bytes.Data::2 92520
system.ruby.network.routers0.msg_bytes.Response_Data::4 92808
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10280
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states
system.ruby.network.routers1.percent_links_utilized 7.876088
system.ruby.network.routers1.msg_count.Control::2 1289
system.ruby.network.routers1.msg_count.Data::2 1285
system.ruby.network.routers1.msg_bytes.Data::2 92520
system.ruby.network.routers1.msg_bytes.Response_Data::4 92808
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10280
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states
system.ruby.network.routers2.percent_links_utilized 7.876088
system.ruby.network.routers2.msg_count.Control::2 1289
system.ruby.network.routers2.msg_count.Data::2 1285
system.ruby.network.routers2.msg_bytes.Data::2 92520
system.ruby.network.routers2.msg_bytes.Response_Data::4 92808
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 10280
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Control 3867
system.ruby.network.msg_count.Data 3855
system.ruby.network.msg_count.Response_Data 3867
system.ruby.network.msg_byte.Data 277560
system.ruby.network.msg_byte.Response_Data 278424
system.ruby.network.msg_byte.Writeback_Control 30840
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.throttle0.link_utilization 7.885879
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1289
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1285
sim_ticks 30526500 # Number of ticks simulated
final_tick 30526500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 398653 # Simulator instruction rate (inst/s)
-host_op_rate 397863 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2276293986 # Simulator tick rate (ticks/s)
-host_mem_usage 245124 # Number of bytes of host memory used
+host_inst_rate 412582 # Simulator instruction rate (inst/s)
+host_op_rate 412293 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2361216779 # Simulator tick rate (ticks/s)
+host_mem_usage 290052 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory
system.physmem.bytes_read::total 24896 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 534617464 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 280936236 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 815553699 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 11 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 30526500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 61053 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5370 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 81.961543 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 60644.444444 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60644.444444 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 60644.444444 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 116.865384 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.125488 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 10999 # Number of tag accesses
system.cpu.icache.tags.data_accesses 10999 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 5114 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 5114 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 5114 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 60628.404669 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60628.404669 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 60628.404669 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 141.950442 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009399 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 3525 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 3525 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 308 # Transaction distribution
system.membus.trans_dist::ReadExReq 81 # Transaction distribution
system.membus.trans_dist::ReadExResp 81 # Transaction distribution
sim_ticks 21273500 # Number of ticks simulated
final_tick 21273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 54566 # Simulator instruction rate (inst/s)
-host_op_rate 98846 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 215714601 # Simulator tick rate (ticks/s)
-host_mem_usage 266040 # Number of bytes of host memory used
-host_seconds 0.10 # Real time elapsed on the host
+host_inst_rate 60676 # Simulator instruction rate (inst/s)
+host_op_rate 109916 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 239878032 # Simulator tick rate (ticks/s)
+host_mem_usage 312536 # Number of bytes of host memory used
+host_seconds 0.09 # Real time elapsed on the host
sim_insts 5380 # Number of instructions simulated
sim_ops 9747 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8896 # Number of bytes read from this memory
system.physmem.bytes_read::total 26624 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 15224250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 3510 # Number of BP lookups
system.cpu.branchPred.condPredicted 3510 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 564 # Number of conditional branches incorrect
system.cpu.branchPred.indirectMisses 2441 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 404 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states
system.cpu.workload.num_syscalls 11 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 21273500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 42548 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.cc_regfile_writes 5092 # number of cc regfile writes
system.cpu.misc_regfile_reads 7660 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 81.534494 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 2583 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.033936 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 5685 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 5685 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 1723 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1723 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 860 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 83525.179856 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83525.179856 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 83525.179856 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 130.801873 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1651 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.135742 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 4350 # Number of tag accesses
system.cpu.icache.tags.data_accesses 4350 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 1651 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1651 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1651 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 78663.669065 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78663.669065 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 78663.669065 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 163.058861 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010406 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 3752 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 3752 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 342 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 75 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 75 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 208500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 341 # Transaction distribution
system.membus.trans_dist::ReadExReq 75 # Transaction distribution
system.membus.trans_dist::ReadExResp 75 # Transaction distribution
sim_ticks 5615000 # Number of ticks simulated
final_tick 5615000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 380560 # Simulator instruction rate (inst/s)
-host_op_rate 688269 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 395838528 # Simulator tick rate (ticks/s)
-host_mem_usage 254256 # Number of bytes of host memory used
+host_inst_rate 383826 # Simulator instruction rate (inst/s)
+host_op_rate 694898 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 400042776 # Simulator tick rate (ticks/s)
+host_mem_usage 299464 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 5381 # Number of instructions simulated
sim_ops 9748 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 54912 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7066 # Number of bytes read from this memory
system.physmem.bytes_read::total 61978 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 9779519145 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2525022262 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12304541407 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states
system.cpu.workload.num_syscalls 11 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 5615000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 11231 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 9748 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 7917 # Transaction distribution
system.membus.trans_dist::ReadResp 7917 # Transaction distribution
system.membus.trans_dist::WriteReq 935 # Transaction distribution
sim_ticks 87948 # Number of ticks simulated
final_tick 87948 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 77426 # Simulator instruction rate (inst/s)
-host_op_rate 140230 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1264887 # Simulator tick rate (ticks/s)
-host_mem_usage 428592 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
+host_inst_rate 83700 # Simulator instruction rate (inst/s)
+host_op_rate 151608 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1367648 # Simulator tick rate (ticks/s)
+host_mem_usage 473696 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 5381 # Number of instructions simulated
sim_ops 9748 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 88128 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 88128 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 87872 # Number of bytes written to this memory
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 77782 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states
system.cpu.apic_clk_domain.clock 16 # Clock period in ticks
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states
system.cpu.workload.num_syscalls 11 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 87948 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 87948 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 9748 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
+system.ruby.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
system.ruby.delayHist::samples 2750 # delay histogram for all message
system.ruby.miss_latency_hist_seqr | 1149 83.44% 83.44% | 191 13.87% 97.31% | 24 1.74% 99.06% | 5 0.36% 99.42% | 2 0.15% 99.56% | 6 0.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 1377
system.ruby.Directory.incomplete_times_seqr 1376
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 # Number of cache demand misses
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.percent_links_utilized 7.817119
system.ruby.network.routers0.msg_count.Control::2 1377
system.ruby.network.routers0.msg_count.Data::2 1373
system.ruby.network.routers0.msg_bytes.Data::2 98856
system.ruby.network.routers0.msg_bytes.Response_Data::4 99144
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10984
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states
system.ruby.network.routers1.percent_links_utilized 7.817119
system.ruby.network.routers1.msg_count.Control::2 1377
system.ruby.network.routers1.msg_count.Data::2 1373
system.ruby.network.routers1.msg_bytes.Data::2 98856
system.ruby.network.routers1.msg_bytes.Response_Data::4 99144
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10984
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states
system.ruby.network.routers2.percent_links_utilized 7.817119
system.ruby.network.routers2.msg_count.Control::2 1377
system.ruby.network.routers2.msg_count.Data::2 1373
system.ruby.network.routers2.msg_bytes.Data::2 98856
system.ruby.network.routers2.msg_bytes.Response_Data::4 99144
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 10984
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Control 4131
system.ruby.network.msg_count.Data 4119
system.ruby.network.msg_count.Response_Data 4131
system.ruby.network.msg_byte.Data 296568
system.ruby.network.msg_byte.Response_Data 297432
system.ruby.network.msg_byte.Writeback_Control 32952
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.throttle0.link_utilization 7.826215
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1377
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1373
sim_ticks 30886500 # Number of ticks simulated
final_tick 30886500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 324268 # Simulator instruction rate (inst/s)
-host_op_rate 586988 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1858658321 # Simulator tick rate (ticks/s)
-host_mem_usage 262968 # Number of bytes of host memory used
+host_inst_rate 223066 # Simulator instruction rate (inst/s)
+host_op_rate 403939 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1279464733 # Simulator tick rate (ticks/s)
+host_mem_usage 309460 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
sim_insts 5381 # Number of instructions simulated
sim_ops 9748 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory
system.physmem.bytes_read::total 23104 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 470367313 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 277661762 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 748029074 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
system.cpu.workload.num_syscalls 11 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 30886500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 61773 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 9748 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 80.558239 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 105.267613 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.111328 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 13956 # Number of tag accesses
system.cpu.icache.tags.data_accesses 13956 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 6636 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 6636 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 6636 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60791.666667 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 133.672095 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008606 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 3257 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 3257 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 1.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 282 # Transaction distribution
system.membus.trans_dist::ReadExReq 79 # Transaction distribution
system.membus.trans_dist::ReadExResp 79 # Transaction distribution
sim_ticks 25580500 # Number of ticks simulated
final_tick 25580500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 119260 # Simulator instruction rate (inst/s)
-host_op_rate 119247 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 238851205 # Simulator tick rate (ticks/s)
-host_mem_usage 249876 # Number of bytes of host memory used
-host_seconds 0.11 # Real time elapsed on the host
+host_inst_rate 131467 # Simulator instruction rate (inst/s)
+host_op_rate 131454 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 263302304 # Simulator tick rate (ticks/s)
+host_mem_usage 296128 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
sim_insts 12770 # Number of instructions simulated
sim_ops 12770 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 39680 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 21824 # Number of bytes read from this memory
system.physmem.bytes_read::total 61504 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 22525750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 4883 # Number of BP lookups
system.cpu.branchPred.condPredicted 2924 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 790 # Number of conditional branches incorrect
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload0.num_syscalls 17 # Number of system calls
system.cpu.workload1.num_syscalls 17 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 25580500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 51162 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fp_regfile_writes 4 # number of floating regfile writes
system.cpu.misc_regfile_reads 2 # number of misc regfile reads
system.cpu.misc_regfile_writes 2 # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements::0 0 # number of replacements
system.cpu.dcache.tags.replacements::1 0 # number of replacements
system.cpu.dcache.tags.replacements::total 0 # number of replacements
system.cpu.dcache.tags.occ_task_id_percent::1024 0.083252 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 10889 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 10889 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 3245 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 3245 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 1018 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 87893.233918 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87893.233918 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 87893.233918 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements::0 7 # number of replacements
system.cpu.icache.tags.replacements::1 0 # number of replacements
system.cpu.icache.tags.replacements::total 7 # number of replacements
system.cpu.icache.tags.occ_task_id_percent::1024 0.300781 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 8261 # Number of tag accesses
system.cpu.icache.tags.data_accesses 8261 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 2916 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 2916 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 2916 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 80906.894061 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80906.894061 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 80906.894061 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements::0 0 # number of replacements
system.cpu.l2cache.tags.replacements::1 0 # number of replacements
system.cpu.l2cache.tags.replacements::total 0 # number of replacements
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.024872 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 8737 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 8737 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackClean_hits::writebacks 7 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 7 # number of WritebackClean hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 818 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 3.7 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 511500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 815 # Transaction distribution
system.membus.trans_dist::ReadExReq 146 # Transaction distribution
system.membus.trans_dist::ReadExResp 146 # Transaction distribution
sim_ticks 28845500 # Number of ticks simulated
final_tick 28845500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 50478 # Simulator instruction rate (inst/s)
-host_op_rate 50473 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 100846842 # Simulator tick rate (ticks/s)
-host_mem_usage 247864 # Number of bytes of host memory used
-host_seconds 0.29 # Real time elapsed on the host
+host_inst_rate 97927 # Simulator instruction rate (inst/s)
+host_op_rate 97921 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 195651101 # Simulator tick rate (ticks/s)
+host_mem_usage 293060 # Number of bytes of host memory used
+host_seconds 0.15 # Real time elapsed on the host
sim_insts 14436 # Number of instructions simulated
sim_ops 14436 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory
system.physmem.bytes_read::total 32640 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 21995000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 12618 # Number of BP lookups
system.cpu.branchPred.condPredicted 7653 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1475 # Number of conditional branches incorrect
system.cpu.branchPredindirectMispredicted 897 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 18 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 28845500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 57692 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.int_regfile_writes 20548 # number of integer regfile writes
system.cpu.misc_regfile_reads 8142 # number of misc regfile reads
system.cpu.misc_regfile_writes 569 # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 99.867537 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 4648 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 10540 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 10540 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 3609 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 3609 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 206.414108 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 6949 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 15425 # Number of tag accesses
system.cpu.icache.tags.data_accesses 15425 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 6949 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 6949 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 6949 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 240.923513 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013000 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4613 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4613 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 428 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 219000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 426 # Transaction distribution
system.membus.trans_dist::ReadExReq 83 # Transaction distribution
system.membus.trans_dist::ReadExResp 83 # Transaction distribution
sim_ticks 7612000 # Number of ticks simulated
final_tick 7612000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 353219 # Simulator instruction rate (inst/s)
-host_op_rate 353015 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 177141347 # Simulator tick rate (ticks/s)
-host_mem_usage 236080 # Number of bytes of host memory used
-host_seconds 0.04 # Real time elapsed on the host
+host_inst_rate 696198 # Simulator instruction rate (inst/s)
+host_op_rate 695914 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 349255842 # Simulator tick rate (ticks/s)
+host_mem_usage 279976 # Number of bytes of host memory used
+host_seconds 0.02 # Real time elapsed on the host
sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 7612000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 60828 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 11342 # Number of bytes read from this memory
system.physmem.bytes_read::total 72170 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7991066737 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2677877036 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10668943773 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 7612000 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 18 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 7612000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 15225 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 15207 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 7612000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 17432 # Transaction distribution
system.membus.trans_dist::ReadResp 17432 # Transaction distribution
system.membus.trans_dist::WriteReq 1442 # Transaction distribution
sim_ticks 44282500 # Number of ticks simulated
final_tick 44282500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 282453 # Simulator instruction rate (inst/s)
-host_op_rate 282325 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 824249311 # Simulator tick rate (ticks/s)
-host_mem_usage 245052 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
+host_inst_rate 533053 # Simulator instruction rate (inst/s)
+host_op_rate 532883 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1555927955 # Simulator tick rate (ticks/s)
+host_mem_usage 289976 # Number of bytes of host memory used
+host_seconds 0.03 # Real time elapsed on the host
sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory
system.physmem.bytes_read::total 26624 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 401784000 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 199446734 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 601230734 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 18 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 44282500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 88565 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 15207 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 97.148649 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 151.748662 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.136719 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 30696 # Number of tag accesses
system.cpu.icache.tags.data_accesses 30696 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 182.297739 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010101 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 331 # Transaction distribution
system.membus.trans_dist::ReadExReq 85 # Transaction distribution
system.membus.trans_dist::ReadExResp 85 # Transaction distribution
sim_ticks 405365000 # Number of ticks simulated
final_tick 405365000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 217578 # Simulator instruction rate (inst/s)
-host_op_rate 217432 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 13650898473 # Simulator tick rate (ticks/s)
-host_mem_usage 630716 # Number of bytes of host memory used
-host_seconds 0.03 # Real time elapsed on the host
+host_inst_rate 281711 # Simulator instruction rate (inst/s)
+host_op_rate 281601 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 17683002929 # Simulator tick rate (ticks/s)
+host_mem_usage 675684 # Number of bytes of host memory used
+host_seconds 0.02 # Real time elapsed on the host
sim_insts 6453 # Number of instructions simulated
sim_ops 6453 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 405365000 # Cumulative time (in ticks) in various power states
system.mem_ctrl.bytes_read::cpu.inst 25852 # Number of bytes read from this memory
system.mem_ctrl.bytes_read::cpu.data 8844 # Number of bytes read from this memory
system.mem_ctrl.bytes_read::total 34696 # Number of bytes read from this memory
system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT 324052250 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 405365000 # Cumulative time (in ticks) in various power states
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 405365000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 405365 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6463 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 405365000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 7654 # Transaction distribution
system.membus.trans_dist::ReadResp 7653 # Transaction distribution
system.membus.trans_dist::WriteReq 865 # Transaction distribution
sim_ticks 61470000 # Number of ticks simulated
final_tick 61470000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 556042 # Simulator instruction rate (inst/s)
-host_op_rate 555477 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5286056763 # Simulator tick rate (ticks/s)
-host_mem_usage 634812 # Number of bytes of host memory used
+host_inst_rate 534192 # Simulator instruction rate (inst/s)
+host_op_rate 533574 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5078648410 # Simulator tick rate (ticks/s)
+host_mem_usage 679784 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 6453 # Number of instructions simulated
sim_ops 6453 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states
system.mem_ctrl.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
system.mem_ctrl.bytes_read::cpu.data 10752 # Number of bytes read from this memory
system.mem_ctrl.bytes_read::total 28544 # Number of bytes read from this memory
system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT 51068500 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 61470000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 61470 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6463 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 104.645861 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1887 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.164062 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 4278 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4278 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 1095 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1095 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101452.380952 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 62 # number of replacements
system.cpu.icache.tags.tagsinuse 113.715440 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 6183 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.855469 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 13209 # Number of tag accesses
system.cpu.icache.tags.data_accesses 13209 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 6183 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 6183 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 6183 # number of demand (read+write) hits
system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l2bus.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states
system.l2bus.trans_dist::ReadResp 376 # Transaction distribution
system.l2bus.trans_dist::CleanEvict 62 # Transaction distribution
system.l2bus.trans_dist::ReadExReq 73 # Transaction distribution
system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%)
system.l2bus.respLayer1.occupancy 504000 # Layer occupancy (ticks)
system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%)
+system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states
system.l2cache.tags.replacements 0 # number of replacements
system.l2cache.tags.tagsinuse 185.619069 # Cycle average of tags in use
system.l2cache.tags.total_refs 65 # Total number of references to valid blocks.
system.l2cache.tags.occ_task_id_percent::1024 0.091064 # Percentage of cache occupancy per task id
system.l2cache.tags.tag_accesses 4534 # Number of tag accesses
system.l2cache.tags.data_accesses 4534 # Number of data accesses
+system.l2cache.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states
system.l2cache.ReadSharedReq_hits::cpu.inst 3 # number of ReadSharedReq hits
system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits
system.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75258.992806 # average overall mshr miss latency
system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78452.380952 # average overall mshr miss latency
system.l2cache.overall_avg_mshr_miss_latency::total 76461.883408 # average overall mshr miss latency
+system.membus.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 373 # Transaction distribution
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
sim_ticks 325849000 # Number of ticks simulated
final_tick 325849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 204518 # Simulator instruction rate (inst/s)
-host_op_rate 236491 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 13350749795 # Simulator tick rate (ticks/s)
-host_mem_usage 689808 # Number of bytes of host memory used
+host_inst_rate 301831 # Simulator instruction rate (inst/s)
+host_op_rate 348968 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 19697741357 # Simulator tick rate (ticks/s)
+host_mem_usage 691496 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
sim_insts 4988 # Number of instructions simulated
sim_ops 5770 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states
system.mem_ctrl.bytes_read::cpu.inst 20108 # Number of bytes read from this memory
system.mem_ctrl.bytes_read::cpu.data 4672 # Number of bytes read from this memory
system.mem_ctrl.bytes_read::total 24780 # Number of bytes read from this memory
system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT 256888500 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 325849000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 325849 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5831 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 6078 # Transaction distribution
system.membus.trans_dist::ReadResp 6088 # Transaction distribution
system.membus.trans_dist::WriteReq 925 # Transaction distribution
sim_ticks 49855000 # Number of ticks simulated
final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 372227 # Simulator instruction rate (inst/s)
-host_op_rate 430264 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3715181399 # Simulator tick rate (ticks/s)
-host_mem_usage 693900 # Number of bytes of host memory used
+host_inst_rate 407452 # Simulator instruction rate (inst/s)
+host_op_rate 470980 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4066768251 # Simulator tick rate (ticks/s)
+host_mem_usage 695596 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 4988 # Number of instructions simulated
sim_ops 5770 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
system.mem_ctrl.bytes_read::cpu.inst 14400 # Number of bytes read from this memory
system.mem_ctrl.bytes_read::cpu.data 8064 # Number of bytes read from this memory
system.mem_ctrl.bytes_read::total 22464 # Number of bytes read from this memory
system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT 42873250 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 49855000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 49855 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5831 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 84.288257 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1855 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.138672 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 4136 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4136 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 951 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 951 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 882 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 70 # number of replacements
system.cpu.icache.tags.tagsinuse 96.468360 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 4779 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.699219 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 10305 # Number of tag accesses
system.cpu.icache.tags.data_accesses 10305 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 4779 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 4779 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 4779 # number of demand (read+write) hits
system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l2bus.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
system.l2bus.trans_dist::ReadResp 348 # Transaction distribution
system.l2bus.trans_dist::CleanEvict 70 # Transaction distribution
system.l2bus.trans_dist::ReadExReq 43 # Transaction distribution
system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%)
system.l2bus.respLayer1.occupancy 426000 # Layer occupancy (ticks)
system.l2bus.respLayer1.utilization 0.9 # Layer utilization (%)
+system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
system.l2cache.tags.replacements 0 # number of replacements
system.l2cache.tags.tagsinuse 156.197536 # Cycle average of tags in use
system.l2cache.tags.total_refs 100 # Total number of references to valid blocks.
system.l2cache.tags.occ_task_id_percent::1024 0.075195 # Percentage of cache occupancy per task id
system.l2cache.tags.tag_accesses 3959 # Number of tag accesses
system.l2cache.tags.data_accesses 3959 # Number of data accesses
+system.l2cache.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
system.l2cache.ReadSharedReq_hits::cpu.inst 24 # number of ReadSharedReq hits
system.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits
system.l2cache.ReadSharedReq_hits::total 40 # number of ReadSharedReq hits
system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency
system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency
system.l2cache.overall_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency
+system.membus.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 308 # Transaction distribution
system.membus.trans_dist::ReadExReq 43 # Transaction distribution
system.membus.trans_dist::ReadExResp 43 # Transaction distribution
sim_ticks 368887000 # Number of ticks simulated
final_tick 368887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 294016 # Simulator instruction rate (inst/s)
-host_op_rate 293668 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 19182713753 # Simulator tick rate (ticks/s)
-host_mem_usage 628676 # Number of bytes of host memory used
+host_inst_rate 323597 # Simulator instruction rate (inst/s)
+host_op_rate 323434 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 21140902807 # Simulator tick rate (ticks/s)
+host_mem_usage 672844 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
sim_insts 5641 # Number of instructions simulated
sim_ops 5641 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 368887000 # Cumulative time (in ticks) in various power states
system.mem_ctrl.bytes_read::cpu.inst 22568 # Number of bytes read from this memory
system.mem_ctrl.bytes_read::cpu.data 4301 # Number of bytes read from this memory
system.mem_ctrl.bytes_read::total 26869 # Number of bytes read from this memory
system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT 350555250 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 368887000 # Cumulative time (in ticks) in various power states
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 7 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 368887000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 368887 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5642 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 368887000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 6778 # Transaction distribution
system.membus.trans_dist::ReadResp 6777 # Transaction distribution
system.membus.trans_dist::WriteReq 901 # Transaction distribution
sim_ticks 58892000 # Number of ticks simulated
final_tick 58892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 509573 # Simulator instruction rate (inst/s)
-host_op_rate 509069 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5309891860 # Simulator tick rate (ticks/s)
-host_mem_usage 632772 # Number of bytes of host memory used
+host_inst_rate 486513 # Simulator instruction rate (inst/s)
+host_op_rate 486102 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5071440381 # Simulator tick rate (ticks/s)
+host_mem_usage 676956 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 5641 # Number of instructions simulated
sim_ops 5641 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states
system.mem_ctrl.bytes_read::cpu.inst 18752 # Number of bytes read from this memory
system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory
system.mem_ctrl.bytes_read::total 27520 # Number of bytes read from this memory
system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT 52812500 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 7 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 58892000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 58892 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5642 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 86.268662 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.133789 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4209 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101459.854015 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 94 # number of replacements
system.cpu.icache.tags.tagsinuse 110.145403 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 5346 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 11583 # Number of tag accesses
system.cpu.icache.tags.data_accesses 11583 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 5346 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 5346 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 5346 # number of demand (read+write) hits
system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l2bus.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states
system.l2bus.trans_dist::ReadResp 384 # Transaction distribution
system.l2bus.trans_dist::CleanEvict 94 # Transaction distribution
system.l2bus.trans_dist::ReadExReq 50 # Transaction distribution
system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%)
system.l2bus.respLayer1.occupancy 411000 # Layer occupancy (ticks)
system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%)
+system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states
system.l2cache.tags.replacements 0 # number of replacements
system.l2cache.tags.tagsinuse 183.861903 # Cycle average of tags in use
system.l2cache.tags.total_refs 98 # Total number of references to valid blocks.
system.l2cache.tags.occ_task_id_percent::1024 0.092773 # Percentage of cache occupancy per task id
system.l2cache.tags.tag_accesses 4654 # Number of tag accesses
system.l2cache.tags.data_accesses 4654 # Number of data accesses
+system.l2cache.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states
system.l2cache.ReadSharedReq_hits::cpu.inst 4 # number of ReadSharedReq hits
system.l2cache.ReadSharedReq_hits::total 4 # number of ReadSharedReq hits
system.l2cache.demand_hits::cpu.inst 4 # number of demand (read+write) hits
system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77819.112628 # average overall mshr miss latency
system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency
system.l2cache.overall_avg_mshr_miss_latency::total 78023.255814 # average overall mshr miss latency
+system.membus.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 380 # Transaction distribution
system.membus.trans_dist::ReadExReq 50 # Transaction distribution
system.membus.trans_dist::ReadExResp 50 # Transaction distribution
sim_ticks 333033000 # Number of ticks simulated
final_tick 333033000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 348800 # Simulator instruction rate (inst/s)
-host_op_rate 348537 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 20908249754 # Simulator tick rate (ticks/s)
-host_mem_usage 629116 # Number of bytes of host memory used
+host_inst_rate 352196 # Simulator instruction rate (inst/s)
+host_op_rate 351993 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 21118670028 # Simulator tick rate (ticks/s)
+host_mem_usage 673252 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
sim_insts 5548 # Number of instructions simulated
sim_ops 5548 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 333033000 # Cumulative time (in ticks) in various power states
system.mem_ctrl.bytes_read::cpu.inst 22364 # Number of bytes read from this memory
system.mem_ctrl.bytes_read::cpu.data 4640 # Number of bytes read from this memory
system.mem_ctrl.bytes_read::total 27004 # Number of bytes read from this memory
system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT 229634250 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 333033000 # Cumulative time (in ticks) in various power states
system.cpu.workload.num_syscalls 11 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 333033000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 333033 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5591 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 333033000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 6310 # Transaction distribution
system.membus.trans_dist::ReadResp 6309 # Transaction distribution
system.membus.trans_dist::WriteReq 673 # Transaction distribution
sim_ticks 53334000 # Number of ticks simulated
final_tick 53334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 429905 # Simulator instruction rate (inst/s)
-host_op_rate 429380 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4122052129 # Simulator tick rate (ticks/s)
-host_mem_usage 633208 # Number of bytes of host memory used
+host_inst_rate 483647 # Simulator instruction rate (inst/s)
+host_op_rate 483274 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4642649843 # Simulator tick rate (ticks/s)
+host_mem_usage 677372 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 5548 # Number of instructions simulated
sim_ops 5548 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states
system.mem_ctrl.bytes_read::cpu.inst 16448 # Number of bytes read from this memory
system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory
system.mem_ctrl.bytes_read::total 25216 # Number of bytes read from this memory
system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT 41660500 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states
system.cpu.workload.num_syscalls 11 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 53334000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 53334 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5591 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 83.743129 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.134766 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 2920 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 2920 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 662 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 662 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 591 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 71 # number of replacements
system.cpu.icache.tags.tagsinuse 98.062907 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 5333 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.734375 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 11443 # Number of tag accesses
system.cpu.icache.tags.data_accesses 11443 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 5333 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 5333 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 5333 # number of demand (read+write) hits
system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l2bus.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states
system.l2bus.trans_dist::ReadResp 315 # Transaction distribution
system.l2bus.trans_dist::CleanEvict 71 # Transaction distribution
system.l2bus.trans_dist::ReadExReq 82 # Transaction distribution
system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%)
system.l2bus.respLayer1.occupancy 414000 # Layer occupancy (ticks)
system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%)
+system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states
system.l2cache.tags.replacements 0 # number of replacements
system.l2cache.tags.tagsinuse 144.000978 # Cycle average of tags in use
system.l2cache.tags.total_refs 73 # Total number of references to valid blocks.
system.l2cache.tags.occ_task_id_percent::1024 0.076172 # Percentage of cache occupancy per task id
system.l2cache.tags.tag_accesses 4130 # Number of tag accesses
system.l2cache.tags.data_accesses 4130 # Number of data accesses
+system.l2cache.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states
system.l2cache.ReadSharedReq_hits::cpu.inst 2 # number of ReadSharedReq hits
system.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits
system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits
system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency
system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency
system.l2cache.overall_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency
+system.membus.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 312 # Transaction distribution
system.membus.trans_dist::ReadExReq 82 # Transaction distribution
system.membus.trans_dist::ReadExResp 82 # Transaction distribution
sim_ticks 445082000 # Number of ticks simulated
final_tick 445082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 211115 # Simulator instruction rate (inst/s)
-host_op_rate 380995 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 16432986499 # Simulator tick rate (ticks/s)
-host_mem_usage 647212 # Number of bytes of host memory used
+host_inst_rate 219197 # Simulator instruction rate (inst/s)
+host_op_rate 395662 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 17068456983 # Simulator tick rate (ticks/s)
+host_mem_usage 691636 # Number of bytes of host memory used
host_seconds 0.03 # Real time elapsed on the host
sim_insts 5712 # Number of instructions simulated
sim_ops 10314 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 445082000 # Cumulative time (in ticks) in various power states
system.mem_ctrl.bytes_read::cpu.inst 58264 # Number of bytes read from this memory
system.mem_ctrl.bytes_read::cpu.data 7167 # Number of bytes read from this memory
system.mem_ctrl.bytes_read::total 65431 # Number of bytes read from this memory
system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT 377923250 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 445082000 # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 445082000 # Cumulative time (in ticks) in various power states
system.cpu.apic_clk_domain.clock 16000 # Clock period in ticks
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 445082000 # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 445082000 # Cumulative time (in ticks) in various power states
system.cpu.workload.num_syscalls 11 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 445082000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 445082 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 10314 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 445082000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 8367 # Transaction distribution
system.membus.trans_dist::ReadResp 8367 # Transaction distribution
system.membus.trans_dist::WriteReq 941 # Transaction distribution
sim_ticks 55844000 # Number of ticks simulated
final_tick 55844000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 299396 # Simulator instruction rate (inst/s)
-host_op_rate 540174 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2922543083 # Simulator tick rate (ticks/s)
-host_mem_usage 651308 # Number of bytes of host memory used
+host_inst_rate 304150 # Simulator instruction rate (inst/s)
+host_op_rate 548931 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2970813002 # Simulator tick rate (ticks/s)
+host_mem_usage 696756 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
sim_insts 5712 # Number of instructions simulated
sim_ops 10314 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
system.mem_ctrl.bytes_read::cpu.inst 14656 # Number of bytes read from this memory
system.mem_ctrl.bytes_read::cpu.data 8640 # Number of bytes read from this memory
system.mem_ctrl.bytes_read::total 23296 # Number of bytes read from this memory
system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT 51070000 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
system.cpu.apic_clk_domain.clock 16000 # Clock period in ticks
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
system.cpu.workload.num_syscalls 11 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 55844000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 55844 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 10314 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 81.671640 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1890 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.131836 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 4185 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4185 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 1028 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1028 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 862 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 103674.074074 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 58 # number of replacements
system.cpu.icache.tags.tagsinuse 91.239705 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 7048 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 14801 # Number of tag accesses
system.cpu.icache.tags.data_accesses 14801 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 7048 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 7048 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 7048 # number of demand (read+write) hits
system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l2bus.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
system.l2bus.trans_dist::ReadResp 291 # Transaction distribution
system.l2bus.trans_dist::CleanEvict 58 # Transaction distribution
system.l2bus.trans_dist::ReadExReq 79 # Transaction distribution
system.l2bus.respLayer0.utilization 1.3 # Layer utilization (%)
system.l2bus.respLayer1.occupancy 405000 # Layer occupancy (ticks)
system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%)
+system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
system.l2cache.tags.replacements 0 # number of replacements
system.l2cache.tags.tagsinuse 135.848259 # Cycle average of tags in use
system.l2cache.tags.total_refs 64 # Total number of references to valid blocks.
system.l2cache.tags.occ_task_id_percent::1024 0.069580 # Percentage of cache occupancy per task id
system.l2cache.tags.tag_accesses 3788 # Number of tag accesses
system.l2cache.tags.data_accesses 3788 # Number of data accesses
+system.l2cache.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
system.l2cache.ReadSharedReq_hits::cpu.inst 6 # number of ReadSharedReq hits
system.l2cache.ReadSharedReq_hits::total 6 # number of ReadSharedReq hits
system.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits
system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77812.227074 # average overall mshr miss latency
system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency
system.l2cache.overall_avg_mshr_miss_latency::total 78873.626374 # average overall mshr miss latency
+system.membus.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 285 # Transaction distribution
system.membus.trans_dist::ReadExReq 79 # Transaction distribution
system.membus.trans_dist::ReadExResp 79 # Transaction distribution
sim_ticks 663454500 # Number of ticks simulated
final_tick 663454500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 153021 # Simulator instruction rate (inst/s)
-host_op_rate 314663 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1515963159 # Simulator tick rate (ticks/s)
-host_mem_usage 1308268 # Number of bytes of host memory used
-host_seconds 0.44 # Real time elapsed on the host
+host_inst_rate 237471 # Simulator instruction rate (inst/s)
+host_op_rate 488329 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2352682974 # Simulator tick rate (ticks/s)
+host_mem_usage 1358064 # Number of bytes of host memory used
+host_seconds 0.28 # Real time elapsed on the host
sim_insts 66963 # Number of instructions simulated
sim_ops 137705 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::dir_cntrl0 99264 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 99264 # Number of bytes read from this memory
system.mem_ctrls.num_reads::dir_cntrl0 1551 # Number of read requests responded to by this memory
system.mem_ctrls_1.memoryStateTime::ACT 524145250 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.ruby.clk_domain.clock 500 # Clock period in ticks
+system.ruby.phys_mem.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.ruby.phys_mem.bytes_read::cpu0.inst 696760 # Number of bytes read from this memory
system.ruby.phys_mem.bytes_read::cpu0.data 119832 # Number of bytes read from this memory
system.ruby.phys_mem.bytes_read::cpu1.CUs0.ComputeUnit 3280 # Number of bytes read from this memory
system.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit 5329680 # Total bandwidth to/from this memory (bytes/s)
system.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit 5329680 # Total bandwidth to/from this memory (bytes/s)
system.ruby.phys_mem.bw_total::total 1351156711 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
+system.ruby.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
system.ruby.outstanding_req_hist_seqr::samples 114203
system.cp_cntrl0.L2cache.num_data_array_writes 11982 # number of data array writes
system.cp_cntrl0.L2cache.num_tag_array_reads 12059 # number of tag array reads
system.cp_cntrl0.L2cache.num_tag_array_writes 1649 # number of tag array writes
+system.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
+system.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
+system.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.cpu0.clk_domain.clock 500 # Clock period in ticks
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks
+system.cpu0.interrupts.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.cpu0.workload.num_syscalls 21 # Number of system calls
+system.cpu0.numPwrStateTransitions 2 # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples 1 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean 2615501 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10 1 100.00% 100.00% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::min_value 2615501 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::max_value 2615501 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total 1 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON 660838999 # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 2615501 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 1326909 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.op_class::total 137705 # Class of executed instruction
system.cpu1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.cpu1.clk_domain.clock 1000 # Clock period in ticks
+system.cpu1.CUs0.localDataStore.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.cpu1.CUs0.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs0.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 307 # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
+system.cpu1.CUs0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs0.num_CAS_ops 0 # number of compare and swap operations
system.cpu1.CUs0.num_failed_CAS_ops 0 # number of compare and swap operations that failed
system.cpu1.CUs0.num_completed_wfs 4 # number of completed wavefronts
+system.cpu1.CUs1.localDataStore.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.cpu1.CUs1.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability
system.cpu1.CUs1.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies
system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 401 # number of times the wf's instructions are blocked due to RAW dependencies
system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands
system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands
+system.cpu1.CUs1.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it
system.cpu1.CUs1.num_CAS_ops 0 # number of compare and swap operations
system.cpu1.CUs1.num_failed_CAS_ops 0 # number of compare and swap operations that failed
system.cpu1.CUs1.num_completed_wfs 4 # number of completed wavefronts
+system.cpu1.CUs0.ldsBus.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
+system.cpu1.CUs1.ldsBus.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
+system.cpu2.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.cpu2.num_kernel_launched 1 # number of kernel launched
system.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits
system.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses
system.dir_cntrl0.L3CacheMemory.num_data_array_writes 1551 # number of data array writes
system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 1551 # number of tag array reads
system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 1551 # number of tag array writes
+system.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.dispatcher_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.dispatcher_coalescer.clk_domain.clock 1000 # Clock period in ticks
+system.dispatcher_coalescer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.dispatcher_coalescer.uncoalesced_accesses 0 # Number of uncoalesced TLB accesses
system.dispatcher_coalescer.coalesced_accesses 0 # Number of coalesced TLB accesses
system.dispatcher_coalescer.queuing_cycles 0 # Number of cycles spent in queue
system.dispatcher_coalescer.local_latency nan # Avg. latency over all incoming pkts
system.dispatcher_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.dispatcher_tlb.clk_domain.clock 1000 # Clock period in ticks
+system.dispatcher_tlb.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.dispatcher_tlb.local_TLB_accesses 0 # Number of TLB accesses
system.dispatcher_tlb.local_TLB_hits 0 # Number of TLB hits
system.dispatcher_tlb.local_TLB_misses 0 # Number of TLB misses
system.dispatcher_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
system.l1_coalescer0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.l1_coalescer0.clk_domain.clock 1000 # Clock period in ticks
+system.l1_coalescer0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.l1_coalescer0.uncoalesced_accesses 778 # Number of uncoalesced TLB accesses
system.l1_coalescer0.coalesced_accesses 0 # Number of coalesced TLB accesses
system.l1_coalescer0.queuing_cycles 0 # Number of cycles spent in queue
system.l1_coalescer0.local_latency 0 # Avg. latency over all incoming pkts
system.l1_coalescer1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.l1_coalescer1.clk_domain.clock 1000 # Clock period in ticks
+system.l1_coalescer1.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.l1_coalescer1.uncoalesced_accesses 769 # Number of uncoalesced TLB accesses
system.l1_coalescer1.coalesced_accesses 0 # Number of coalesced TLB accesses
system.l1_coalescer1.queuing_cycles 0 # Number of cycles spent in queue
system.l1_coalescer1.local_latency 0 # Avg. latency over all incoming pkts
system.l1_tlb0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.l1_tlb0.clk_domain.clock 1000 # Clock period in ticks
+system.l1_tlb0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.l1_tlb0.local_TLB_accesses 778 # Number of TLB accesses
system.l1_tlb0.local_TLB_hits 774 # Number of TLB hits
system.l1_tlb0.local_TLB_misses 4 # Number of TLB misses
system.l1_tlb0.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
system.l1_tlb1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.l1_tlb1.clk_domain.clock 1000 # Clock period in ticks
+system.l1_tlb1.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.l1_tlb1.local_TLB_accesses 769 # Number of TLB accesses
system.l1_tlb1.local_TLB_hits 766 # Number of TLB hits
system.l1_tlb1.local_TLB_misses 3 # Number of TLB misses
system.l1_tlb1.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
system.l2_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.l2_coalescer.clk_domain.clock 1000 # Clock period in ticks
+system.l2_coalescer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.l2_coalescer.uncoalesced_accesses 8 # Number of uncoalesced TLB accesses
system.l2_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses
system.l2_coalescer.queuing_cycles 8000 # Number of cycles spent in queue
system.l2_coalescer.local_latency 125 # Avg. latency over all incoming pkts
system.l2_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.l2_tlb.clk_domain.clock 1000 # Clock period in ticks
+system.l2_tlb.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.l2_tlb.local_TLB_accesses 8 # Number of TLB accesses
system.l2_tlb.local_TLB_hits 3 # Number of TLB hits
system.l2_tlb.local_TLB_misses 5 # Number of TLB misses
system.l2_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
system.l3_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.l3_coalescer.clk_domain.clock 1000 # Clock period in ticks
+system.l3_coalescer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.l3_coalescer.uncoalesced_accesses 5 # Number of uncoalesced TLB accesses
system.l3_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses
system.l3_coalescer.queuing_cycles 8000 # Number of cycles spent in queue
system.l3_coalescer.local_latency 200 # Avg. latency over all incoming pkts
system.l3_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.l3_tlb.clk_domain.clock 1000 # Clock period in ticks
+system.l3_tlb.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.l3_tlb.local_TLB_accesses 5 # Number of TLB accesses
system.l3_tlb.local_TLB_hits 0 # Number of TLB hits
system.l3_tlb.local_TLB_misses 5 # Number of TLB misses
system.l3_tlb.local_cycles 150000 # Number of cycles spent in queue for all incoming reqs
system.l3_tlb.local_latency 30000 # Avg. latency over incoming coalesced reqs
system.l3_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
+system.piobus.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.piobus.trans_dist::WriteReq 94 # Transaction distribution
system.piobus.trans_dist::WriteResp 94 # Transaction distribution
system.piobus.pkt_count_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 188 # Packet count per connected master and slave (bytes)
system.piobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.piobus.respLayer0.occupancy 94000 # Layer occupancy (ticks)
system.piobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.ruby.network.ext_links0.int_node.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.ruby.network.ext_links0.int_node.percent_links_utilized 0.007952
system.ruby.network.ext_links0.int_node.msg_count.Control::0 1551
system.ruby.network.ext_links0.int_node.msg_count.Request_Control::0 1551
system.ruby.network.ext_links0.int_node.msg_bytes.Response_Data::2 112536
system.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::2 12312
system.ruby.network.ext_links0.int_node.msg_bytes.Unblock_Control::4 12408
+system.ruby.network.ext_links1.int_node.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.ruby.network.ext_links1.int_node.percent_links_utilized 0.009970
system.ruby.network.ext_links1.int_node.msg_count.Control::0 16
system.ruby.network.ext_links1.int_node.msg_count.Request_Control::0 1535
system.tcp_cntrl0.L1cache.num_tag_array_reads 26 # number of tag array reads
system.tcp_cntrl0.L1cache.num_tag_array_writes 18 # number of tag array writes
system.tcp_cntrl0.L1cache.num_data_array_stalls 2 # number of stalls caused by data array
+system.tcp_cntrl0.coalescer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 2 # loads that hit in the TCP
system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers
system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
system.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
system.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
system.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU
+system.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
+system.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
+system.ruby.network.ext_links2.int_node.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.ruby.network.ext_links2.int_node.percent_links_utilized 0.000721
system.ruby.network.ext_links2.int_node.msg_count.Control::0 1535
system.ruby.network.ext_links2.int_node.msg_count.Control::1 14
system.tcp_cntrl1.L1cache.num_tag_array_writes 18 # number of tag array writes
system.tcp_cntrl1.L1cache.num_tag_array_stalls 2 # number of stalls caused by tag array
system.tcp_cntrl1.L1cache.num_data_array_stalls 2 # number of stalls caused by data array
+system.tcp_cntrl1.coalescer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 3 # loads that hit in the TCP
system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 2 # TCP to TCP load transfers
system.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
system.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
system.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
system.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU
+system.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
+system.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits
system.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses
system.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses
system.sqc_cntrl0.L1cache.num_tag_array_reads 86 # number of tag array reads
system.sqc_cntrl0.L1cache.num_tag_array_writes 5 # number of tag array writes
system.sqc_cntrl0.L1cache.num_data_array_stalls 47 # number of stalls caused by data array
+system.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.sqc_cntrl0.sequencer.load_waiting_on_load 120 # Number of times a load aliased with a pending load
+system.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits
system.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses
system.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses
+system.tcc_cntrl0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.tccdir_cntrl0.directory.demand_hits 0 # Number of cache demand hits
system.tccdir_cntrl0.directory.demand_misses 0 # Number of cache demand misses
system.tccdir_cntrl0.directory.demand_accesses 0 # Number of cache demand accesses
system.tccdir_cntrl0.directory.num_tag_array_reads 1554 # number of tag array reads
system.tccdir_cntrl0.directory.num_tag_array_writes 27 # number of tag array writes
+system.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Control 3116
system.ruby.network.msg_count.Request_Control 3121
system.ruby.network.msg_count.Response_Data 3159
system.ruby.network.msg_byte.Unblock_Control 24968
system.sqc_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.sqc_coalescer.clk_domain.clock 1000 # Clock period in ticks
+system.sqc_coalescer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.sqc_coalescer.uncoalesced_accesses 86 # Number of uncoalesced TLB accesses
system.sqc_coalescer.coalesced_accesses 60 # Number of coalesced TLB accesses
system.sqc_coalescer.queuing_cycles 108000 # Number of cycles spent in queue
system.sqc_coalescer.local_latency 1255.813953 # Avg. latency over all incoming pkts
system.sqc_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.sqc_tlb.clk_domain.clock 1000 # Clock period in ticks
+system.sqc_tlb.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.sqc_tlb.local_TLB_accesses 60 # Number of TLB accesses
system.sqc_tlb.local_TLB_hits 59 # Number of TLB hits
system.sqc_tlb.local_TLB_misses 1 # Number of TLB misses
system.sqc_tlb.local_cycles 60001 # Number of cycles spent in queue for all incoming reqs
system.sqc_tlb.local_latency 1000.016667 # Avg. latency over incoming coalesced reqs
system.sqc_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks)
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states
system.ruby.network.ext_links0.int_node.throttle0.link_utilization 0.005592
system.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::0 1551
system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Data::2 12
sim_ticks 54141000500 # Number of ticks simulated
final_tick 54141000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2133242 # Simulator instruction rate (inst/s)
-host_op_rate 2143866 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1274754382 # Simulator tick rate (ticks/s)
-host_mem_usage 434732 # Number of bytes of host memory used
-host_seconds 42.47 # Real time elapsed on the host
+host_inst_rate 2060319 # Simulator instruction rate (inst/s)
+host_op_rate 2070580 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1231177946 # Simulator tick rate (ticks/s)
+host_mem_usage 436424 # Number of bytes of host memory used
+host_seconds 43.98 # Real time elapsed on the host
sim_insts 90602408 # Number of instructions simulated
sim_ops 91053639 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 431323084 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 90016598 # Number of bytes read from this memory
system.physmem.bytes_read::total 521339682 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7966662604 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2011871502 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9978534106 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 54141000500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 108282002 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 91054081 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 130287906 # Transaction distribution
system.membus.trans_dist::ReadResp 130291793 # Transaction distribution
system.membus.trans_dist::WriteReq 4734981 # Transaction distribution
sim_ticks 147148719500 # Number of ticks simulated
final_tick 147148719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1356153 # Simulator instruction rate (inst/s)
-host_op_rate 1362892 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2203169070 # Simulator tick rate (ticks/s)
-host_mem_usage 444740 # Number of bytes of host memory used
-host_seconds 66.79 # Real time elapsed on the host
+host_inst_rate 1337875 # Simulator instruction rate (inst/s)
+host_op_rate 1344524 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2173475460 # Simulator tick rate (ticks/s)
+host_mem_usage 445404 # Number of bytes of host memory used
+host_seconds 67.70 # Real time elapsed on the host
sim_insts 90576862 # Number of instructions simulated
sim_ops 91026991 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 36928 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 944832 # Number of bytes read from this memory
system.physmem.bytes_read::total 981760 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 250957 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 6420933 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6671890 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 147148719500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 294297439 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 91054081 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 942702 # number of replacements
system.cpu.dcache.tags.tagsinuse 3565.478025 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 55347598 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 21556948 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 21556948 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12764.311704 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12764.412789 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12764.412789 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 2 # number of replacements
system.cpu.icache.tags.tagsinuse 510.111710 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 107830173 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.291504 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 215662143 # Number of tag accesses
system.cpu.icache.tags.data_accesses 215662143 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 107830173 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 107830173 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 107830173 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 9564.658425 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1827433 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.467621 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 15181828 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 15181828 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 942334 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 942334 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 942334 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1420197000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 792 # Transaction distribution
system.membus.trans_dist::ReadExReq 14548 # Transaction distribution
system.membus.trans_dist::ReadExResp 14548 # Transaction distribution
sim_ticks 122215823500 # Number of ticks simulated
final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1393980 # Simulator instruction rate (inst/s)
-host_op_rate 1394037 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 698723411 # Simulator tick rate (ticks/s)
-host_mem_usage 370524 # Number of bytes of host memory used
-host_seconds 174.91 # Real time elapsed on the host
+host_inst_rate 2850562 # Simulator instruction rate (inst/s)
+host_op_rate 2850680 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1428826010 # Simulator tick rate (ticks/s)
+host_mem_usage 416224 # Number of bytes of host memory used
+host_seconds 85.54 # Real time elapsed on the host
sim_insts 243825150 # Number of instructions simulated
sim_ops 243835265 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 122215823500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 977685992 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 328674008 # Number of bytes read from this memory
system.physmem.bytes_read::total 1306360000 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7999667834 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3438835373 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11438503207 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 122215823500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 443 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 122215823500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 244431648 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 244431613 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 122215823500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 326641931 # Transaction distribution
system.membus.trans_dist::ReadResp 326641931 # Transaction distribution
system.membus.trans_dist::WriteReq 22901951 # Transaction distribution
sim_ticks 168950040000 # Number of ticks simulated
final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 769614 # Simulator instruction rate (inst/s)
-host_op_rate 1355167 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 823011137 # Simulator tick rate (ticks/s)
-host_mem_usage 396564 # Number of bytes of host memory used
-host_seconds 205.28 # Real time elapsed on the host
+host_inst_rate 1541579 # Simulator instruction rate (inst/s)
+host_op_rate 2714473 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1648535817 # Simulator tick rate (ticks/s)
+host_mem_usage 443832 # Number of bytes of host memory used
+host_seconds 102.49 # Real time elapsed on the host
sim_insts 157988548 # Number of instructions simulated
sim_ops 278192465 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 168950040000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 1741569312 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 717246013 # Number of bytes read from this memory
system.physmem.bytes_read::total 2458815325 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 10308191179 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5684633931 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 15992825110 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 168950040000 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 168950040000 # Cumulative time (in ticks) in various power states
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 168950040000 # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 168950040000 # Cumulative time (in ticks) in various power states
system.cpu.workload.num_syscalls 444 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 168950040000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 337900081 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 278192465 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 168950040000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 308475611 # Transaction distribution
system.membus.trans_dist::ReadResp 308475611 # Transaction distribution
system.membus.trans_dist::WriteReq 31439752 # Transaction distribution
sim_ticks 199332411500 # Number of ticks simulated
final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1428598 # Simulator instruction rate (inst/s)
-host_op_rate 1428597 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 714299076 # Simulator tick rate (ticks/s)
-host_mem_usage 244476 # Number of bytes of host memory used
-host_seconds 279.06 # Real time elapsed on the host
+host_inst_rate 3079687 # Simulator instruction rate (inst/s)
+host_op_rate 3079687 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1539844146 # Simulator tick rate (ticks/s)
+host_mem_usage 290224 # Number of bytes of host memory used
+host_seconds 129.45 # Real time elapsed on the host
sim_insts 398664595 # Number of instructions simulated
sim_ops 398664595 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 199332411500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 1594658604 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 662449271 # Number of bytes read from this memory
system.physmem.bytes_read::total 2257107875 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7999996548 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5793368275 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13793364824 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 199332411500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 199332411500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 398664824 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 398664651 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 199332411500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 493419140 # Transaction distribution
system.membus.trans_dist::ReadResp 493419140 # Transaction distribution
system.membus.trans_dist::WriteReq 73520729 # Transaction distribution
sim_ticks 124523000 # Number of ticks simulated
final_tick 124523000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 139641 # Simulator instruction rate (inst/s)
-host_op_rate 139640 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 15068671 # Simulator tick rate (ticks/s)
-host_mem_usage 262532 # Number of bytes of host memory used
-host_seconds 8.26 # Real time elapsed on the host
+host_inst_rate 259079 # Simulator instruction rate (inst/s)
+host_op_rate 259078 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 27957290 # Simulator tick rate (ticks/s)
+host_mem_usage 308636 # Number of bytes of host memory used
+host_seconds 4.45 # Real time elapsed on the host
sim_insts 1153943 # Number of instructions simulated
sim_ops 1153943 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.inst 24000 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 10880 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 5888 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 70805750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
system.cpu0.branchPred.lookups 98739 # Number of BP lookups
system.cpu0.branchPred.condPredicted 94242 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 1562 # Number of conditional branches incorrect
system.cpu0.branchPredindirectMispredicted 1035 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.workload.num_syscalls 89 # Number of system calls
+system.cpu0.pwrStateResidencyTicks::ON 124523000 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 249047 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
system.cpu0.misc_regfile_reads 269052 # number of misc regfile reads
system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 2 # number of replacements
system.cpu0.dcache.tags.tagsinuse 142.724931 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 178078 # Total number of references to valid blocks.
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.332031 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 717658 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 717658 # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 90413 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 90413 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 87748 # number of WriteReq hits
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 43486.111111 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 43486.111111 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 43486.111111 # average overall mshr miss latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 394 # number of replacements
system.cpu0.icache.tags.tagsinuse 248.905102 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 7041 # Total number of references to valid blocks.
system.cpu0.icache.tags.occ_task_id_percent::1024 0.587891 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 8647 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 8647 # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 7041 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 7041 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 7041 # number of demand (read+write) hits
system.cpu1.branchPred.indirectHits 52196 # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses 9917 # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted 1232 # Number of mispredicted indirect branches.
+system.cpu1.pwrStateResidencyTicks::ON 124523000 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 193493 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
system.cpu1.misc_regfile_reads 146210 # number of misc regfile reads
system.cpu1.misc_regfile_writes 648 # number of misc regfile writes
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements 0 # number of replacements
system.cpu1.dcache.tags.tagsinuse 26.604916 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 52484 # Total number of references to valid blocks.
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.060547 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 405985 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 405985 # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data 55568 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 55568 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 45140 # number of WriteReq hits
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13806.985294 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13806.985294 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13806.985294 # average overall mshr miss latency
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements 579 # number of replacements
system.cpu1.icache.tags.tagsinuse 98.515696 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 22662 # Total number of references to valid blocks.
system.cpu1.icache.tags.occ_task_id_percent::1024 0.261719 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 24245 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 24245 # Number of data accesses
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst 22662 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 22662 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 22662 # number of demand (read+write) hits
system.cpu2.branchPred.indirectHits 44645 # Number of indirect target hits.
system.cpu2.branchPred.indirectMisses 10961 # Number of indirect misses.
system.cpu2.branchPredindirectMispredicted 1342 # Number of mispredicted indirect branches.
+system.cpu2.pwrStateResidencyTicks::ON 124523000 # Cumulative time (in ticks) in various power states
system.cpu2.numCycles 193104 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
system.cpu2.misc_regfile_reads 119022 # number of misc regfile reads
system.cpu2.misc_regfile_writes 648 # number of misc regfile writes
+system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
system.cpu2.dcache.tags.replacements 0 # number of replacements
system.cpu2.dcache.tags.tagsinuse 25.641689 # Cycle average of tags in use
system.cpu2.dcache.tags.total_refs 42500 # Total number of references to valid blocks.
system.cpu2.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id
system.cpu2.dcache.tags.tag_accesses 336580 # Number of tag accesses
system.cpu2.dcache.tags.data_accesses 336580 # Number of data accesses
+system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
system.cpu2.dcache.ReadReq_hits::cpu2.data 48215 # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total 48215 # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data 35154 # number of WriteReq hits
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12723.880597 # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12723.880597 # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12723.880597 # average overall mshr miss latency
+system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
system.cpu2.icache.tags.replacements 598 # number of replacements
system.cpu2.icache.tags.tagsinuse 95.853337 # Cycle average of tags in use
system.cpu2.icache.tags.total_refs 28564 # Total number of references to valid blocks.
system.cpu2.icache.tags.occ_task_id_percent::1024 0.263672 # Percentage of cache occupancy per task id
system.cpu2.icache.tags.tag_accesses 30149 # Number of tag accesses
system.cpu2.icache.tags.data_accesses 30149 # Number of data accesses
+system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
system.cpu2.icache.ReadReq_hits::cpu2.inst 28564 # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total 28564 # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst 28564 # number of demand (read+write) hits
system.cpu3.branchPred.indirectHits 43109 # Number of indirect target hits.
system.cpu3.branchPred.indirectMisses 10392 # Number of indirect misses.
system.cpu3.branchPredindirectMispredicted 1225 # Number of mispredicted indirect branches.
+system.cpu3.pwrStateResidencyTicks::ON 124523000 # Cumulative time (in ticks) in various power states
system.cpu3.numCycles 192748 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
system.cpu3.misc_regfile_reads 112177 # number of misc regfile reads
system.cpu3.misc_regfile_writes 648 # number of misc regfile writes
+system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
system.cpu3.dcache.tags.replacements 0 # number of replacements
system.cpu3.dcache.tags.tagsinuse 24.465247 # Cycle average of tags in use
system.cpu3.dcache.tags.total_refs 40069 # Total number of references to valid blocks.
system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
system.cpu3.dcache.tags.tag_accesses 319388 # Number of tag accesses
system.cpu3.dcache.tags.data_accesses 319388 # Number of data accesses
+system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
system.cpu3.dcache.ReadReq_hits::cpu3.data 46353 # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total 46353 # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data 32769 # number of WriteReq hits
system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12147.727273 # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12147.727273 # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12147.727273 # average overall mshr miss latency
+system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
system.cpu3.icache.tags.replacements 563 # number of replacements
system.cpu3.icache.tags.tagsinuse 93.764815 # Cycle average of tags in use
system.cpu3.icache.tags.total_refs 29516 # Total number of references to valid blocks.
system.cpu3.icache.tags.occ_task_id_percent::1024 0.269531 # Percentage of cache occupancy per task id
system.cpu3.icache.tags.tag_accesses 31038 # Number of tag accesses
system.cpu3.icache.tags.data_accesses 31038 # Number of data accesses
+system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
system.cpu3.icache.ReadReq_hits::cpu3.inst 29516 # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total 29516 # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst 29516 # number of demand (read+write) hits
system.cpu3.icache.demand_avg_mshr_miss_latency::total 14331.669044 # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 14331.669044 # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::total 14331.669044 # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 0 # number of replacements
system.l2c.tags.tagsinuse 455.287968 # Cycle average of tags in use
system.l2c.tags.total_refs 3075 # Total number of references to valid blocks.
system.l2c.tags.occ_task_id_percent::1024 0.008850 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 31874 # Number of tag accesses
system.l2c.tags.data_accesses 31874 # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 709 # number of WritebackClean hits
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 582 # Transaction distribution
system.membus.trans_dist::UpgradeReq 274 # Transaction distribution
system.membus.trans_dist::ReadExReq 186 # Transaction distribution
system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadResp 3517 # Transaction distribution
system.toL2Bus.trans_dist::ReadRespWithInvalidate 9 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution
sim_ticks 87707000 # Number of ticks simulated
final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 856943 # Simulator instruction rate (inst/s)
-host_op_rate 856930 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 110961270 # Simulator tick rate (ticks/s)
-host_mem_usage 258436 # Number of bytes of host memory used
-host_seconds 0.79 # Real time elapsed on the host
+host_inst_rate 1934217 # Simulator instruction rate (inst/s)
+host_op_rate 1934165 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 250446535 # Simulator tick rate (ticks/s)
+host_mem_usage 303372 # Number of bytes of host memory used
+host_seconds 0.35 # Real time elapsed on the host
sim_insts 677333 # Number of instructions simulated
sim_ops 677333 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory
system.physmem.bw_total::cpu3.inst 729702 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.workload.num_syscalls 89 # Number of system calls
+system.cpu0.pwrStateResidencyTicks::ON 87707000 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 175415 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 175388 # Class of executed instruction
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 2 # number of replacements
system.cpu0.dcache.tags.tagsinuse 150.745705 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 81882 # Total number of references to valid blocks.
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 329804 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 329804 # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
system.cpu0.dcache.writebacks::total 1 # number of writebacks
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 215 # number of replacements
system.cpu0.icache.tags.tagsinuse 222.772732 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks.
system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 175855 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 175855 # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks 215 # number of writebacks
system.cpu0.icache.writebacks::total 215 # number of writebacks
+system.cpu1.pwrStateResidencyTicks::ON 87707000 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 173297 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 167432 # Class of executed instruction
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements 0 # number of replacements
system.cpu1.dcache.tags.tagsinuse 30.295170 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 21529 # Total number of references to valid blocks.
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 198211 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 198211 # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data 39152 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 39152 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 9968 # number of WriteReq hits
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements 278 # number of replacements
system.cpu1.icache.tags.tagsinuse 76.752158 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 167074 # Total number of references to valid blocks.
system.cpu1.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 167790 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 167790 # Number of data accesses
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst 167074 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 167074 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 167074 # number of demand (read+write) hits
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks 278 # number of writebacks
system.cpu1.icache.writebacks::total 278 # number of writebacks
+system.cpu2.pwrStateResidencyTicks::ON 87707000 # Cumulative time (in ticks) in various power states
system.cpu2.numCycles 173296 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu2.op_class::total 167367 # Class of executed instruction
+system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
system.cpu2.dcache.tags.replacements 0 # number of replacements
system.cpu2.dcache.tags.tagsinuse 29.575165 # Cycle average of tags in use
system.cpu2.dcache.tags.total_refs 35457 # Total number of references to valid blocks.
system.cpu2.dcache.tags.occ_task_id_percent::1024 0.052734 # Percentage of cache occupancy per task id
system.cpu2.dcache.tags.tag_accesses 239521 # Number of tag accesses
system.cpu2.dcache.tags.data_accesses 239521 # Number of data accesses
+system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
system.cpu2.dcache.ReadReq_hits::cpu2.data 42635 # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total 42635 # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data 16864 # number of WriteReq hits
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
system.cpu2.icache.tags.replacements 278 # number of replacements
system.cpu2.icache.tags.tagsinuse 74.781471 # Cycle average of tags in use
system.cpu2.icache.tags.total_refs 167009 # Total number of references to valid blocks.
system.cpu2.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id
system.cpu2.icache.tags.tag_accesses 167725 # Number of tag accesses
system.cpu2.icache.tags.data_accesses 167725 # Number of data accesses
+system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
system.cpu2.icache.ReadReq_hits::cpu2.inst 167009 # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total 167009 # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst 167009 # number of demand (read+write) hits
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.icache.writebacks::writebacks 278 # number of writebacks
system.cpu2.icache.writebacks::total 278 # number of writebacks
+system.cpu3.pwrStateResidencyTicks::ON 87707000 # Cumulative time (in ticks) in various power states
system.cpu3.numCycles 173297 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu3.op_class::total 167304 # Class of executed instruction
+system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
system.cpu3.dcache.tags.replacements 0 # number of replacements
system.cpu3.dcache.tags.tagsinuse 28.848199 # Cycle average of tags in use
system.cpu3.dcache.tags.total_refs 33595 # Total number of references to valid blocks.
system.cpu3.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id
system.cpu3.dcache.tags.tag_accesses 234241 # Number of tag accesses
system.cpu3.dcache.tags.data_accesses 234241 # Number of data accesses
+system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
system.cpu3.dcache.ReadReq_hits::cpu3.data 42185 # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total 42185 # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data 15991 # number of WriteReq hits
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
system.cpu3.icache.tags.replacements 279 # number of replacements
system.cpu3.icache.tags.tagsinuse 72.874953 # Cycle average of tags in use
system.cpu3.icache.tags.total_refs 166945 # Total number of references to valid blocks.
system.cpu3.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id
system.cpu3.icache.tags.tag_accesses 167663 # Number of tag accesses
system.cpu3.icache.tags.data_accesses 167663 # Number of data accesses
+system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
system.cpu3.icache.ReadReq_hits::cpu3.inst 166945 # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total 166945 # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst 166945 # number of demand (read+write) hits
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.icache.writebacks::writebacks 279 # number of writebacks
system.cpu3.icache.writebacks::total 279 # number of writebacks
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 0 # number of replacements
system.l2c.tags.tagsinuse 367.545675 # Cycle average of tags in use
system.l2c.tags.total_refs 1716 # Total number of references to valid blocks.
system.l2c.tags.occ_task_id_percent::1024 0.006439 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 19424 # Number of tag accesses
system.l2c.tags.data_accesses 19424 # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 423 # Transaction distribution
system.membus.trans_dist::UpgradeReq 273 # Transaction distribution
system.membus.trans_dist::UpgradeResp 80 # Transaction distribution
system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean 1050 # Transaction distribution
sim_ticks 264174500 # Number of ticks simulated
final_tick 264174500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 587931 # Simulator instruction rate (inst/s)
-host_op_rate 587915 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 234112560 # Simulator tick rate (ticks/s)
-host_mem_usage 258432 # Number of bytes of host memory used
-host_seconds 1.13 # Real time elapsed on the host
+host_inst_rate 1178179 # Simulator instruction rate (inst/s)
+host_op_rate 1178160 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 469155398 # Simulator tick rate (ticks/s)
+host_mem_usage 303372 # Number of bytes of host memory used
+host_seconds 0.56 # Real time elapsed on the host
sim_insts 663394 # Number of instructions simulated
sim_ops 663394 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory
system.physmem.bw_total::cpu3.inst 969056 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data 3633962 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 138575071 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.workload.num_syscalls 89 # Number of system calls
+system.cpu0.pwrStateResidencyTicks::ON 264174500 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 528349 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 158330 # Class of executed instruction
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 2 # number of replacements
system.cpu0.dcache.tags.tagsinuse 144.970648 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 73336 # Total number of references to valid blocks.
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 295705 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 295705 # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 48725 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 48725 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 24729 # number of WriteReq hits
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 33036.827195 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33036.827195 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 33036.827195 # average overall mshr miss latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 215 # number of replacements
system.cpu0.icache.tags.tagsinuse 211.220090 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 157864 # Total number of references to valid blocks.
system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 158798 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 158798 # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 157864 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 157864 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 157864 # number of demand (read+write) hits
system.cpu0.icache.demand_avg_mshr_miss_latency::total 42739.828694 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42739.828694 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 42739.828694 # average overall mshr miss latency
+system.cpu1.pwrStateResidencyTicks::ON 264174500 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 528348 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 170032 # Class of executed instruction
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements 0 # number of replacements
system.cpu1.dcache.tags.tagsinuse 26.444551 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 27473 # Total number of references to valid blocks.
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 215113 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 215113 # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data 41008 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 41008 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 12359 # number of WriteReq hits
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12262.773723 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12262.773723 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12262.773723 # average overall mshr miss latency
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements 280 # number of replacements
system.cpu1.icache.tags.tagsinuse 66.843295 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 169667 # Total number of references to valid blocks.
system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 170399 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 170399 # Number of data accesses
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst 169667 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 169667 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 169667 # number of demand (read+write) hits
system.cpu1.icache.demand_avg_mshr_miss_latency::total 14560.109290 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14560.109290 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 14560.109290 # average overall mshr miss latency
+system.cpu2.pwrStateResidencyTicks::ON 264174500 # Cumulative time (in ticks) in various power states
system.cpu2.numCycles 528349 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu2.op_class::total 165719 # Class of executed instruction
+system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
system.cpu2.dcache.tags.replacements 0 # number of replacements
system.cpu2.dcache.tags.tagsinuse 27.447331 # Cycle average of tags in use
system.cpu2.dcache.tags.total_refs 30642 # Total number of references to valid blocks.
system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
system.cpu2.dcache.tags.tag_accesses 220669 # Number of tag accesses
system.cpu2.dcache.tags.data_accesses 220669 # Number of data accesses
+system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
system.cpu2.dcache.ReadReq_hits::cpu2.data 40751 # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total 40751 # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data 14004 # number of WriteReq hits
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13405.109489 # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13405.109489 # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13405.109489 # average overall mshr miss latency
+system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
system.cpu2.icache.tags.replacements 280 # number of replacements
system.cpu2.icache.tags.tagsinuse 69.258301 # Cycle average of tags in use
system.cpu2.icache.tags.total_refs 165354 # Total number of references to valid blocks.
system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
system.cpu2.icache.tags.tag_accesses 166086 # Number of tag accesses
system.cpu2.icache.tags.data_accesses 166086 # Number of data accesses
+system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
system.cpu2.icache.ReadReq_hits::cpu2.inst 165354 # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total 165354 # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst 165354 # number of demand (read+write) hits
system.cpu2.icache.demand_avg_mshr_miss_latency::total 21310.109290 # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21310.109290 # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::total 21310.109290 # average overall mshr miss latency
+system.cpu3.pwrStateResidencyTicks::ON 264174500 # Cumulative time (in ticks) in various power states
system.cpu3.numCycles 528348 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu3.op_class::total 169471 # Class of executed instruction
+system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
system.cpu3.dcache.tags.replacements 0 # number of replacements
system.cpu3.dcache.tags.tagsinuse 25.601960 # Cycle average of tags in use
system.cpu3.dcache.tags.total_refs 28504 # Total number of references to valid blocks.
system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
system.cpu3.dcache.tags.tag_accesses 218004 # Number of tag accesses
system.cpu3.dcache.tags.data_accesses 218004 # Number of data accesses
+system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
system.cpu3.dcache.ReadReq_hits::cpu3.data 41179 # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total 41179 # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data 12939 # number of WriteReq hits
system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12324.218750 # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12324.218750 # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12324.218750 # average overall mshr miss latency
+system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
system.cpu3.icache.tags.replacements 281 # number of replacements
system.cpu3.icache.tags.tagsinuse 64.834449 # Cycle average of tags in use
system.cpu3.icache.tags.total_refs 169105 # Total number of references to valid blocks.
system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
system.cpu3.icache.tags.tag_accesses 169839 # Number of tag accesses
system.cpu3.icache.tags.data_accesses 169839 # Number of data accesses
+system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
system.cpu3.icache.ReadReq_hits::cpu3.inst 169105 # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total 169105 # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst 169105 # number of demand (read+write) hits
system.cpu3.icache.demand_avg_mshr_miss_latency::total 13935.967302 # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13935.967302 # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::total 13935.967302 # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 0 # number of replacements
system.l2c.tags.tagsinuse 346.893205 # Cycle average of tags in use
system.l2c.tags.total_refs 1714 # Total number of references to valid blocks.
system.l2c.tags.occ_task_id_percent::1024 0.006546 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 19677 # Number of tag accesses
system.l2c.tags.data_accesses 19677 # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 430 # Transaction distribution
system.membus.trans_dist::UpgradeReq 272 # Transaction distribution
system.membus.trans_dist::ReadExReq 208 # Transaction distribution
system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean 1056 # Transaction distribution
sim_ticks 10021833 # Number of ticks simulated
final_tick 10021833 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 162199 # Simulator tick rate (ticks/s)
-host_mem_usage 417868 # Number of bytes of host memory used
-host_seconds 61.79 # Real time elapsed on the host
+host_tick_rate 187111 # Simulator tick rate (ticks/s)
+host_mem_usage 467772 # Number of bytes of host memory used
+host_seconds 53.56 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39622272 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 39622272 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14218944 # Number of bytes written to this memory
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 1 # Clock period in ticks
+system.cpu0.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.cpu0.num_reads 99423 # number of read accesses completed
system.cpu0.num_writes 55170 # number of write accesses completed
+system.cpu1.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.cpu1.num_reads 98761 # number of read accesses completed
system.cpu1.num_writes 54523 # number of write accesses completed
+system.cpu2.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.cpu2.num_reads 100000 # number of read accesses completed
system.cpu2.num_writes 55115 # number of write accesses completed
+system.cpu3.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.cpu3.num_reads 99531 # number of read accesses completed
system.cpu3.num_writes 55151 # number of write accesses completed
+system.cpu4.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.cpu4.num_reads 99248 # number of read accesses completed
system.cpu4.num_writes 55036 # number of write accesses completed
+system.cpu5.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.cpu5.num_reads 99097 # number of read accesses completed
system.cpu5.num_writes 55621 # number of write accesses completed
+system.cpu6.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.cpu6.num_reads 99456 # number of read accesses completed
system.cpu6.num_writes 55200 # number of write accesses completed
+system.cpu7.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.cpu7.num_reads 99560 # number of read accesses completed
system.cpu7.num_writes 55285 # number of write accesses completed
system.ruby.clk_domain.clock 1 # Clock period in ticks
+system.ruby.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.ruby.delayHist::bucket_size 32 # delay histogram for all message
system.ruby.delayHist::max_bucket 319 # delay histogram for all message
system.ruby.delayHist::samples 4985028 # delay histogram for all message
system.ruby.miss_latency_hist_seqr::stdev 1206.840773
system.ruby.miss_latency_hist_seqr | 164661 26.36% 26.36% | 154480 24.73% 51.08% | 150906 24.16% 75.24% | 129850 20.78% 96.02% | 24588 3.94% 99.96% | 246 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 624731
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.L1Dcache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 78237 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78237 # Number of cache demand accesses
system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl1.L1Dcache.demand_hits 3 # Number of cache demand hits
system.ruby.l1_cntrl1.L1Dcache.demand_misses 77673 # Number of cache demand misses
system.ruby.l1_cntrl1.L1Dcache.demand_accesses 77676 # Number of cache demand accesses
system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
+system.ruby.l1_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl1.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl2.L1Dcache.demand_hits 1 # Number of cache demand hits
system.ruby.l1_cntrl2.L1Dcache.demand_misses 78377 # Number of cache demand misses
system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78378 # Number of cache demand accesses
system.ruby.l1_cntrl2.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl2.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl2.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
+system.ruby.l1_cntrl2.sequencer.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl2.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl3.L1Dcache.demand_hits 1 # Number of cache demand hits
system.ruby.l1_cntrl3.L1Dcache.demand_misses 78097 # Number of cache demand misses
system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78098 # Number of cache demand accesses
system.ruby.l1_cntrl3.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl3.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl3.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
+system.ruby.l1_cntrl3.sequencer.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl3.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl4.L1Dcache.demand_hits 1 # Number of cache demand hits
system.ruby.l1_cntrl4.L1Dcache.demand_misses 78248 # Number of cache demand misses
system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78249 # Number of cache demand accesses
system.ruby.l1_cntrl4.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl4.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl4.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
+system.ruby.l1_cntrl4.sequencer.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl4.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl5.L1Dcache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl5.L1Dcache.demand_misses 77823 # Number of cache demand misses
system.ruby.l1_cntrl5.L1Dcache.demand_accesses 77823 # Number of cache demand accesses
system.ruby.l1_cntrl5.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl5.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl5.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
+system.ruby.l1_cntrl5.sequencer.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl5.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl6.L1Dcache.demand_hits 2 # Number of cache demand hits
system.ruby.l1_cntrl6.L1Dcache.demand_misses 78233 # Number of cache demand misses
system.ruby.l1_cntrl6.L1Dcache.demand_accesses 78235 # Number of cache demand accesses
system.ruby.l1_cntrl6.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl6.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl6.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
+system.ruby.l1_cntrl6.sequencer.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl6.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl7.L1Dcache.demand_hits 2 # Number of cache demand hits
system.ruby.l1_cntrl7.L1Dcache.demand_misses 78071 # Number of cache demand misses
system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78073 # Number of cache demand accesses
system.ruby.l1_cntrl7.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl7.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl7.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
+system.ruby.l1_cntrl7.sequencer.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl7.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.ruby.l2_cntrl0.L2cache.demand_hits 35 # Number of cache demand hits
system.ruby.l2_cntrl0.L2cache.demand_misses 624702 # Number of cache demand misses
system.ruby.l2_cntrl0.L2cache.demand_accesses 624737 # Number of cache demand accesses
+system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.ruby.l2_cntrl0.fully_busy_cycles 3 # cycles for which number of transistions == max transitions
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
+system.ruby.network.routers00.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.ruby.network.routers00.percent_links_utilized 4.083916
system.ruby.network.routers00.msg_count.Control::0 78237
system.ruby.network.routers00.msg_count.Request_Control::2 76723
system.ruby.network.routers00.msg_bytes.Writeback_Data::0 1062792
system.ruby.network.routers00.msg_bytes.Writeback_Data::1 3769848
system.ruby.network.routers00.msg_bytes.Writeback_Control::0 210944
+system.ruby.network.routers01.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.ruby.network.routers01.percent_links_utilized 4.041267
system.ruby.network.routers01.msg_count.Control::0 77673
system.ruby.network.routers01.msg_count.Request_Control::2 76172
system.ruby.network.routers01.msg_bytes.Writeback_Data::0 1049904
system.ruby.network.routers01.msg_bytes.Writeback_Data::1 3712104
system.ruby.network.routers01.msg_bytes.Writeback_Control::0 206776
+system.ruby.network.routers02.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.ruby.network.routers02.percent_links_utilized 4.088773
system.ruby.network.routers02.msg_count.Control::0 78377
system.ruby.network.routers02.msg_count.Request_Control::2 76766
system.ruby.network.routers02.msg_bytes.Writeback_Data::0 1071288
system.ruby.network.routers02.msg_bytes.Writeback_Data::1 3762576
system.ruby.network.routers02.msg_bytes.Writeback_Control::0 210960
+system.ruby.network.routers03.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.ruby.network.routers03.percent_links_utilized 4.065454
system.ruby.network.routers03.msg_count.Control::0 78097
system.ruby.network.routers03.msg_count.Request_Control::2 76565
system.ruby.network.routers03.msg_bytes.Writeback_Data::0 1051848
system.ruby.network.routers03.msg_bytes.Writeback_Data::1 3735792
system.ruby.network.routers03.msg_bytes.Writeback_Control::0 209704
+system.ruby.network.routers04.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.ruby.network.routers04.percent_links_utilized 4.076620
system.ruby.network.routers04.msg_count.Control::0 78248
system.ruby.network.routers04.msg_count.Request_Control::2 76737
system.ruby.network.routers04.msg_bytes.Writeback_Data::0 1053288
system.ruby.network.routers04.msg_bytes.Writeback_Data::1 3754656
system.ruby.network.routers04.msg_bytes.Writeback_Control::0 211016
+system.ruby.network.routers05.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.ruby.network.routers05.percent_links_utilized 4.060382
system.ruby.network.routers05.msg_count.Control::0 77823
system.ruby.network.routers05.msg_count.Request_Control::2 76343
system.ruby.network.routers05.msg_bytes.Writeback_Data::0 1064016
system.ruby.network.routers05.msg_bytes.Writeback_Data::1 3742560
system.ruby.network.routers05.msg_bytes.Writeback_Control::0 206368
+system.ruby.network.routers06.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.ruby.network.routers06.percent_links_utilized 4.079877
system.ruby.network.routers06.msg_count.Control::0 78233
system.ruby.network.routers06.msg_count.Request_Control::2 76715
system.ruby.network.routers06.msg_bytes.Writeback_Data::0 1060488
system.ruby.network.routers06.msg_bytes.Writeback_Data::1 3756816
system.ruby.network.routers06.msg_bytes.Writeback_Control::0 211304
+system.ruby.network.routers07.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.ruby.network.routers07.percent_links_utilized 4.070416
system.ruby.network.routers07.msg_count.Control::0 78071
system.ruby.network.routers07.msg_count.Request_Control::2 76560
system.ruby.network.routers07.msg_bytes.Writeback_Data::0 1061712
system.ruby.network.routers07.msg_bytes.Writeback_Data::1 3745296
system.ruby.network.routers07.msg_bytes.Writeback_Control::0 208768
+system.ruby.network.routers08.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.ruby.network.routers08.percent_links_utilized 55.328626
system.ruby.network.routers08.msg_count.Control::0 1243860
system.ruby.network.routers08.msg_count.Request_Control::2 608794
system.ruby.network.routers08.msg_bytes.Writeback_Data::0 8475336
system.ruby.network.routers08.msg_bytes.Writeback_Data::1 29979648
system.ruby.network.routers08.msg_bytes.Writeback_Control::0 1675840
+system.ruby.network.routers09.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.ruby.network.routers09.percent_links_utilized 22.966170
system.ruby.network.routers09.msg_count.Control::0 619101
system.ruby.network.routers09.msg_count.Response_Data::1 841268
system.ruby.network.routers09.msg_bytes.Control::0 4952808
system.ruby.network.routers09.msg_bytes.Response_Data::1 60571296
system.ruby.network.routers09.msg_bytes.Response_Control::1 8128120
+system.ruby.network.routers10.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.ruby.network.routers10.percent_links_utilized 11.092782
system.ruby.network.routers10.msg_count.Control::0 1243860
system.ruby.network.routers10.msg_count.Request_Control::2 612581
system.ruby.network.routers10.msg_bytes.Writeback_Data::0 8475336
system.ruby.network.routers10.msg_bytes.Writeback_Data::1 29979648
system.ruby.network.routers10.msg_bytes.Writeback_Control::0 1675840
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Control 3731580
system.ruby.network.msg_count.Request_Control 1833956
system.ruby.network.msg_count.Response_Data 4399208
system.ruby.network.msg_byte.Response_Control 51743816
system.ruby.network.msg_byte.Writeback_Data 115364952
system.ruby.network.msg_byte.Writeback_Control 5027520
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 10021833 # Cumulative time (in ticks) in various power states
system.ruby.network.routers00.throttle0.link_utilization 4.100802
system.ruby.network.routers00.throttle0.msg_count.Request_Control::2 76723
system.ruby.network.routers00.throttle0.msg_count.Response_Data::1 78233
sim_ticks 7436579 # Number of ticks simulated
final_tick 7436579 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 74529 # Simulator tick rate (ticks/s)
-host_mem_usage 420508 # Number of bytes of host memory used
-host_seconds 99.78 # Real time elapsed on the host
+host_tick_rate 82813 # Simulator tick rate (ticks/s)
+host_mem_usage 469820 # Number of bytes of host memory used
+host_seconds 89.80 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39411840 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 39411840 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14207680 # Number of bytes written to this memory
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 1 # Clock period in ticks
+system.cpu0.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.cpu0.num_reads 99533 # number of read accesses completed
system.cpu0.num_writes 55594 # number of write accesses completed
+system.cpu1.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.cpu1.num_reads 99397 # number of read accesses completed
system.cpu1.num_writes 55662 # number of write accesses completed
+system.cpu2.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.cpu2.num_reads 99976 # number of read accesses completed
system.cpu2.num_writes 55789 # number of write accesses completed
+system.cpu3.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.cpu3.num_reads 99413 # number of read accesses completed
system.cpu3.num_writes 55629 # number of write accesses completed
+system.cpu4.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.cpu4.num_reads 99342 # number of read accesses completed
system.cpu4.num_writes 55223 # number of write accesses completed
+system.cpu5.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.cpu5.num_reads 100000 # number of read accesses completed
system.cpu5.num_writes 55687 # number of write accesses completed
+system.cpu6.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.cpu6.num_reads 99314 # number of read accesses completed
system.cpu6.num_writes 55046 # number of write accesses completed
+system.cpu7.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.cpu7.num_reads 99437 # number of read accesses completed
system.cpu7.num_writes 55128 # number of write accesses completed
system.ruby.clk_domain.clock 1 # Clock period in ticks
+system.ruby.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.ruby.outstanding_req_hist_seqr::bucket_size 2
system.ruby.outstanding_req_hist_seqr::max_bucket 19
system.ruby.outstanding_req_hist_seqr::samples 627422
system.ruby.miss_latency_hist_seqr::stdev 1631.335046
system.ruby.miss_latency_hist_seqr | 473768 75.54% 75.54% | 104367 16.64% 92.18% | 33291 5.31% 97.49% | 11023 1.76% 99.25% | 3421 0.55% 99.80% | 948 0.15% 99.95% | 243 0.04% 99.99% | 74 0.01% 100.00% | 12 0.00% 100.00% | 6 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 627153
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.L1Dcache.demand_hits 22 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 78254 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78276 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl1.L1Dcache.demand_hits 9 # Number of cache demand hits
system.ruby.l1_cntrl1.L1Dcache.demand_misses 78372 # Number of cache demand misses
system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78381 # Number of cache demand accesses
system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses
+system.ruby.l1_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl1.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl2.L1Dcache.demand_hits 19 # Number of cache demand hits
system.ruby.l1_cntrl2.L1Dcache.demand_misses 78709 # Number of cache demand misses
system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78728 # Number of cache demand accesses
system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses
+system.ruby.l1_cntrl2.sequencer.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl2.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl3.L1Dcache.demand_hits 17 # Number of cache demand hits
system.ruby.l1_cntrl3.L1Dcache.demand_misses 78281 # Number of cache demand misses
system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78298 # Number of cache demand accesses
system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses
+system.ruby.l1_cntrl3.sequencer.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl3.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl4.L1Dcache.demand_hits 23 # Number of cache demand hits
system.ruby.l1_cntrl4.L1Dcache.demand_misses 78290 # Number of cache demand misses
system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78313 # Number of cache demand accesses
system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses
+system.ruby.l1_cntrl4.sequencer.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl4.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl5.L1Dcache.demand_hits 11 # Number of cache demand hits
system.ruby.l1_cntrl5.L1Dcache.demand_misses 78570 # Number of cache demand misses
system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78581 # Number of cache demand accesses
system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses
+system.ruby.l1_cntrl5.sequencer.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl5.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl6.L1Dcache.demand_hits 23 # Number of cache demand hits
system.ruby.l1_cntrl6.L1Dcache.demand_misses 78475 # Number of cache demand misses
system.ruby.l1_cntrl6.L1Dcache.demand_accesses 78498 # Number of cache demand accesses
system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses
+system.ruby.l1_cntrl6.sequencer.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl6.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl7.L1Dcache.demand_hits 17 # Number of cache demand hits
system.ruby.l1_cntrl7.L1Dcache.demand_misses 78224 # Number of cache demand misses
system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78241 # Number of cache demand accesses
system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses
+system.ruby.l1_cntrl7.sequencer.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl7.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.ruby.l2_cntrl0.L2cache.demand_hits 4647 # Number of cache demand hits
system.ruby.l2_cntrl0.L2cache.demand_misses 622511 # Number of cache demand misses
system.ruby.l2_cntrl0.L2cache.demand_accesses 627158 # Number of cache demand accesses
+system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
+system.ruby.network.routers00.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.ruby.network.routers00.percent_links_utilized 5.789295
system.ruby.network.routers00.msg_count.Request_Control::0 78254
system.ruby.network.routers00.msg_count.Response_Data::2 76885
system.ruby.network.routers00.msg_bytes.Forwarded_Control::0 6984
system.ruby.network.routers00.msg_bytes.Invalidate_Control::0 1912
system.ruby.network.routers00.msg_bytes.Unblock_Control::2 632264
+system.ruby.network.routers01.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.ruby.network.routers01.percent_links_utilized 5.798120
system.ruby.network.routers01.msg_count.Request_Control::0 78372
system.ruby.network.routers01.msg_count.Response_Data::2 76915
system.ruby.network.routers01.msg_bytes.Forwarded_Control::0 7176
system.ruby.network.routers01.msg_bytes.Invalidate_Control::0 1824
system.ruby.network.routers01.msg_bytes.Unblock_Control::2 633568
+system.ruby.network.routers02.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.ruby.network.routers02.percent_links_utilized 5.822099
system.ruby.network.routers02.msg_count.Request_Control::0 78709
system.ruby.network.routers02.msg_count.Response_Data::2 77304
system.ruby.network.routers02.msg_bytes.Forwarded_Control::0 6656
system.ruby.network.routers02.msg_bytes.Invalidate_Control::0 1920
system.ruby.network.routers02.msg_bytes.Unblock_Control::2 635792
+system.ruby.network.routers03.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.ruby.network.routers03.percent_links_utilized 5.790606
system.ruby.network.routers03.msg_count.Request_Control::0 78281
system.ruby.network.routers03.msg_count.Response_Data::2 76851
system.ruby.network.routers03.msg_bytes.Forwarded_Control::0 6880
system.ruby.network.routers03.msg_bytes.Invalidate_Control::0 1792
system.ruby.network.routers03.msg_bytes.Unblock_Control::2 632632
+system.ruby.network.routers04.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.ruby.network.routers04.percent_links_utilized 5.791907
system.ruby.network.routers04.msg_count.Request_Control::0 78290
system.ruby.network.routers04.msg_count.Response_Data::2 76878
system.ruby.network.routers04.msg_bytes.Forwarded_Control::0 6824
system.ruby.network.routers04.msg_bytes.Invalidate_Control::0 1720
system.ruby.network.routers04.msg_bytes.Unblock_Control::2 632680
+system.ruby.network.routers05.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.ruby.network.routers05.percent_links_utilized 5.809960
system.ruby.network.routers05.msg_count.Request_Control::0 78570
system.ruby.network.routers05.msg_count.Response_Data::2 77119
system.ruby.network.routers05.msg_bytes.Forwarded_Control::0 6280
system.ruby.network.routers05.msg_bytes.Invalidate_Control::0 2112
system.ruby.network.routers05.msg_bytes.Unblock_Control::2 634616
+system.ruby.network.routers06.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.ruby.network.routers06.percent_links_utilized 5.804383
system.ruby.network.routers06.msg_count.Request_Control::0 78475
system.ruby.network.routers06.msg_count.Response_Data::2 77081
system.ruby.network.routers06.msg_bytes.Forwarded_Control::0 6584
system.ruby.network.routers06.msg_bytes.Invalidate_Control::0 1776
system.ruby.network.routers06.msg_bytes.Unblock_Control::2 634088
+system.ruby.network.routers07.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.ruby.network.routers07.percent_links_utilized 5.784636
system.ruby.network.routers07.msg_count.Request_Control::0 78224
system.ruby.network.routers07.msg_count.Response_Data::2 76772
system.ruby.network.routers07.msg_bytes.Forwarded_Control::0 6224
system.ruby.network.routers07.msg_bytes.Invalidate_Control::0 1808
system.ruby.network.routers07.msg_bytes.Unblock_Control::2 632056
+system.ruby.network.routers08.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.ruby.network.routers08.percent_links_utilized 76.954202
system.ruby.network.routers08.msg_count.Request_Control::0 627158
system.ruby.network.routers08.msg_count.Request_Control::1 615810
system.ruby.network.routers08.msg_bytes.Forwarded_Control::0 53608
system.ruby.network.routers08.msg_bytes.Invalidate_Control::0 14816
system.ruby.network.routers08.msg_bytes.Unblock_Control::2 9993920
+system.ruby.network.routers09.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.ruby.network.routers09.percent_links_utilized 30.981463
system.ruby.network.routers09.msg_count.Request_Control::1 615810
system.ruby.network.routers09.msg_count.Response_Data::2 615809
system.ruby.network.routers09.msg_bytes.Writeback_Data::2 15983640
system.ruby.network.routers09.msg_bytes.Writeback_Control::1 3552064
system.ruby.network.routers09.msg_bytes.Unblock_Control::2 4926320
+system.ruby.network.routers10.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.ruby.network.routers10.percent_links_utilized 15.432642
system.ruby.network.routers10.msg_count.Request_Control::0 627158
system.ruby.network.routers10.msg_count.Request_Control::1 615810
system.ruby.network.routers10.msg_bytes.Forwarded_Control::0 53608
system.ruby.network.routers10.msg_bytes.Invalidate_Control::0 14864
system.ruby.network.routers10.msg_bytes.Unblock_Control::2 9993920
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Request_Control 3728921
system.ruby.network.msg_count.Response_Data 3694837
system.ruby.network.msg_count.ResponseL2hit_Data 13941
system.ruby.network.msg_byte.Forwarded_Control 160824
system.ruby.network.msg_byte.Invalidate_Control 44544
system.ruby.network.msg_byte.Unblock_Control 29981856
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 7436579 # Cumulative time (in ticks) in various power states
system.ruby.network.routers00.throttle0.link_utilization 5.270831
system.ruby.network.routers00.throttle0.msg_count.Response_Data::2 76885
system.ruby.network.routers00.throttle0.msg_count.ResponseL2hit_Data::2 587
sim_ticks 6099346 # Number of ticks simulated
final_tick 6099346 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 81040 # Simulator tick rate (ticks/s)
-host_mem_usage 421980 # Number of bytes of host memory used
-host_seconds 75.26 # Real time elapsed on the host
+host_tick_rate 91228 # Simulator tick rate (ticks/s)
+host_mem_usage 473028 # Number of bytes of host memory used
+host_seconds 66.86 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39765376 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 39765376 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 19455168 # Number of bytes written to this memory
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 1 # Clock period in ticks
+system.cpu0.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.cpu0.num_reads 99731 # number of read accesses completed
system.cpu0.num_writes 55103 # number of write accesses completed
+system.cpu1.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.cpu1.num_reads 99468 # number of read accesses completed
system.cpu1.num_writes 55228 # number of write accesses completed
+system.cpu2.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.cpu2.num_reads 100000 # number of read accesses completed
system.cpu2.num_writes 55518 # number of write accesses completed
+system.cpu3.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.cpu3.num_reads 99696 # number of read accesses completed
system.cpu3.num_writes 55953 # number of write accesses completed
+system.cpu4.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.cpu4.num_reads 98851 # number of read accesses completed
system.cpu4.num_writes 55227 # number of write accesses completed
+system.cpu5.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.cpu5.num_reads 98859 # number of read accesses completed
system.cpu5.num_writes 55313 # number of write accesses completed
+system.cpu6.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.cpu6.num_reads 99329 # number of read accesses completed
system.cpu6.num_writes 55461 # number of write accesses completed
+system.cpu7.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.cpu7.num_reads 99244 # number of read accesses completed
system.cpu7.num_writes 55110 # number of write accesses completed
system.ruby.clk_domain.clock 1 # Clock period in ticks
+system.ruby.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.ruby.outstanding_req_hist_seqr::bucket_size 2
system.ruby.outstanding_req_hist_seqr::max_bucket 19
system.ruby.outstanding_req_hist_seqr::samples 626716
system.ruby.miss_latency_hist_seqr::total 623627
system.ruby.L1Cache.incomplete_times_seqr 2150
system.ruby.Directory.incomplete_times_seqr 621474
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.L1Dcache.demand_hits 20 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 78435 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78455 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.fully_busy_cycles 12 # cycles for which number of transistions == max transitions
system.ruby.l1_cntrl1.L1Dcache.demand_hits 26 # Number of cache demand hits
system.ruby.l1_cntrl1.L1Dcache.demand_misses 78293 # Number of cache demand misses
system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses
+system.ruby.l1_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl1.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl1.fully_busy_cycles 8 # cycles for which number of transistions == max transitions
system.ruby.l1_cntrl2.L1Dcache.demand_hits 21 # Number of cache demand hits
system.ruby.l1_cntrl2.L1Dcache.demand_misses 78389 # Number of cache demand misses
system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses
+system.ruby.l1_cntrl2.sequencer.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl2.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl2.fully_busy_cycles 6 # cycles for which number of transistions == max transitions
system.ruby.l1_cntrl3.L1Dcache.demand_hits 20 # Number of cache demand hits
system.ruby.l1_cntrl3.L1Dcache.demand_misses 78553 # Number of cache demand misses
system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses
+system.ruby.l1_cntrl3.sequencer.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl3.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl3.fully_busy_cycles 6 # cycles for which number of transistions == max transitions
system.ruby.l1_cntrl4.L1Dcache.demand_hits 24 # Number of cache demand hits
system.ruby.l1_cntrl4.L1Dcache.demand_misses 78168 # Number of cache demand misses
system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses
+system.ruby.l1_cntrl4.sequencer.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl4.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl4.fully_busy_cycles 12 # cycles for which number of transistions == max transitions
system.ruby.l1_cntrl5.L1Dcache.demand_hits 31 # Number of cache demand hits
system.ruby.l1_cntrl5.L1Dcache.demand_misses 78418 # Number of cache demand misses
system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses
+system.ruby.l1_cntrl5.sequencer.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl5.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl5.fully_busy_cycles 8 # cycles for which number of transistions == max transitions
system.ruby.l1_cntrl6.L1Dcache.demand_hits 32 # Number of cache demand hits
system.ruby.l1_cntrl6.L1Dcache.demand_misses 78003 # Number of cache demand misses
system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses
+system.ruby.l1_cntrl6.sequencer.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl6.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl6.fully_busy_cycles 7 # cycles for which number of transistions == max transitions
system.ruby.l1_cntrl7.L1Dcache.demand_hits 24 # Number of cache demand hits
system.ruby.l1_cntrl7.L1Dcache.demand_misses 78156 # Number of cache demand misses
system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses
+system.ruby.l1_cntrl7.sequencer.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl7.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl7.fully_busy_cycles 7 # cycles for which number of transistions == max transitions
system.ruby.l2_cntrl0.L2cache.demand_hits 1651 # Number of cache demand hits
system.ruby.l2_cntrl0.L2cache.demand_misses 624764 # Number of cache demand misses
system.ruby.l2_cntrl0.L2cache.demand_accesses 626415 # Number of cache demand accesses
+system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
+system.ruby.network.routers00.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.ruby.network.routers00.percent_links_utilized 11.233413
system.ruby.network.routers00.msg_count.Request_Control::1 78435
system.ruby.network.routers00.msg_count.Response_Data::4 81785
system.ruby.network.routers00.msg_bytes.Writeback_Data::4 7742088
system.ruby.network.routers00.msg_bytes.Broadcast_Control::1 5011320
system.ruby.network.routers00.msg_bytes.Persistent_Control::3 2626808
+system.ruby.network.routers01.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.ruby.network.routers01.percent_links_utilized 11.216772
system.ruby.network.routers01.msg_count.Request_Control::1 78293
system.ruby.network.routers01.msg_count.Response_Data::4 81463
system.ruby.network.routers01.msg_bytes.Writeback_Data::4 7733808
system.ruby.network.routers01.msg_bytes.Broadcast_Control::1 5011320
system.ruby.network.routers01.msg_bytes.Persistent_Control::3 2627240
+system.ruby.network.routers02.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.ruby.network.routers02.percent_links_utilized 11.235213
system.ruby.network.routers02.msg_count.Request_Control::1 78389
system.ruby.network.routers02.msg_count.Response_Data::4 81630
system.ruby.network.routers02.msg_bytes.Writeback_Data::4 7755264
system.ruby.network.routers02.msg_bytes.Broadcast_Control::1 5011320
system.ruby.network.routers02.msg_bytes.Persistent_Control::3 2629448
+system.ruby.network.routers03.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.ruby.network.routers03.percent_links_utilized 11.269241
system.ruby.network.routers03.msg_count.Request_Control::1 78553
system.ruby.network.routers03.msg_count.Response_Data::4 82027
system.ruby.network.routers03.msg_bytes.Writeback_Data::4 7790256
system.ruby.network.routers03.msg_bytes.Broadcast_Control::1 5011320
system.ruby.network.routers03.msg_bytes.Persistent_Control::3 2630952
+system.ruby.network.routers04.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.ruby.network.routers04.percent_links_utilized 11.220096
system.ruby.network.routers04.msg_count.Request_Control::1 78168
system.ruby.network.routers04.msg_count.Response_Data::4 81565
system.ruby.network.routers04.msg_bytes.Writeback_Data::4 7733736
system.ruby.network.routers04.msg_bytes.Broadcast_Control::1 5011320
system.ruby.network.routers04.msg_bytes.Persistent_Control::3 2627576
+system.ruby.network.routers05.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.ruby.network.routers05.percent_links_utilized 11.228085
system.ruby.network.routers05.msg_count.Request_Control::1 78418
system.ruby.network.routers05.msg_count.Response_Data::4 81763
system.ruby.network.routers05.msg_bytes.Writeback_Control::4 16
system.ruby.network.routers05.msg_bytes.Broadcast_Control::1 5011320
system.ruby.network.routers05.msg_bytes.Persistent_Control::3 2627096
+system.ruby.network.routers06.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.ruby.network.routers06.percent_links_utilized 11.201853
system.ruby.network.routers06.msg_count.Request_Control::1 78003
system.ruby.network.routers06.msg_count.Response_Data::4 81441
system.ruby.network.routers06.msg_bytes.Writeback_Data::4 7705872
system.ruby.network.routers06.msg_bytes.Broadcast_Control::1 5011320
system.ruby.network.routers06.msg_bytes.Persistent_Control::3 2626824
+system.ruby.network.routers07.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.ruby.network.routers07.percent_links_utilized 11.201172
system.ruby.network.routers07.msg_count.Request_Control::1 78156
system.ruby.network.routers07.msg_count.Response_Data::4 81436
system.ruby.network.routers07.msg_bytes.Writeback_Data::4 7704936
system.ruby.network.routers07.msg_bytes.Broadcast_Control::1 5011320
system.ruby.network.routers07.msg_bytes.Persistent_Control::3 2625032
+system.ruby.network.routers08.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.ruby.network.routers08.percent_links_utilized 42.049426
system.ruby.network.routers08.msg_count.Request_Control::1 626415
system.ruby.network.routers08.msg_count.Request_Control::2 624764
system.ruby.network.routers08.msg_bytes.Writeback_Data::4 65968992
system.ruby.network.routers08.msg_bytes.Writeback_Control::4 2544984
system.ruby.network.routers08.msg_bytes.Persistent_Control::3 2335664
+system.ruby.network.routers09.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.ruby.network.routers09.percent_links_utilized 39.472142
system.ruby.network.routers09.msg_count.Request_Control::2 624764
system.ruby.network.routers09.msg_count.Response_Data::4 635954
system.ruby.network.routers09.msg_bytes.Writeback_Data::4 21367296
system.ruby.network.routers09.msg_bytes.Writeback_Control::4 2545000
system.ruby.network.routers09.msg_bytes.Persistent_Control::3 2335664
+system.ruby.network.routers10.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.ruby.network.routers10.percent_links_utilized 19.510945
system.ruby.network.routers10.msg_count.Request_Control::1 626415
system.ruby.network.routers10.msg_count.Request_Control::2 624764
system.ruby.network.routers10.msg_bytes.Writeback_Control::4 2545000
system.ruby.network.routers10.msg_bytes.Broadcast_Control::1 35079240
system.ruby.network.routers10.msg_bytes.Persistent_Control::3 21020976
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Request_Control 3753537
system.ruby.network.msg_count.Response_Data 1956209
system.ruby.network.msg_count.ResponseL2hit_Data 5226
system.ruby.network.msg_byte.Writeback_Control 7635000
system.ruby.network.msg_byte.Broadcast_Control 75169800
system.ruby.network.msg_byte.Persistent_Control 46713280
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 6099346 # Cumulative time (in ticks) in various power states
system.ruby.network.routers00.throttle0.link_utilization 13.880578
system.ruby.network.routers00.throttle0.msg_count.Response_Data::4 79888
system.ruby.network.routers00.throttle0.msg_count.ResponseL2hit_Data::4 199
sim_ticks 4722948 # Number of ticks simulated
final_tick 4722948 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 53510 # Simulator tick rate (ticks/s)
-host_mem_usage 421672 # Number of bytes of host memory used
-host_seconds 88.26 # Real time elapsed on the host
+host_tick_rate 61998 # Simulator tick rate (ticks/s)
+host_mem_usage 471708 # Number of bytes of host memory used
+host_seconds 76.18 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 38973248 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 38973248 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14131456 # Number of bytes written to this memory
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 1 # Clock period in ticks
+system.cpu0.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
system.cpu0.num_reads 99221 # number of read accesses completed
system.cpu0.num_writes 55233 # number of write accesses completed
+system.cpu1.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
system.cpu1.num_reads 99634 # number of read accesses completed
system.cpu1.num_writes 55697 # number of write accesses completed
+system.cpu2.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
system.cpu2.num_reads 99089 # number of read accesses completed
system.cpu2.num_writes 55519 # number of write accesses completed
+system.cpu3.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
system.cpu3.num_reads 100000 # number of read accesses completed
system.cpu3.num_writes 55486 # number of write accesses completed
+system.cpu4.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
system.cpu4.num_reads 99397 # number of read accesses completed
system.cpu4.num_writes 55450 # number of write accesses completed
+system.cpu5.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
system.cpu5.num_reads 99838 # number of read accesses completed
system.cpu5.num_writes 55386 # number of write accesses completed
+system.cpu6.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
system.cpu6.num_reads 99890 # number of read accesses completed
system.cpu6.num_writes 55532 # number of write accesses completed
+system.cpu7.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
system.cpu7.num_reads 99124 # number of read accesses completed
system.cpu7.num_writes 55205 # number of write accesses completed
system.ruby.clk_domain.clock 1 # Clock period in ticks
+system.ruby.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
system.ruby.outstanding_req_hist_seqr::bucket_size 2
system.ruby.outstanding_req_hist_seqr::max_bucket 19
system.ruby.outstanding_req_hist_seqr::samples 630039
system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits
system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses
system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.L1Dcache.demand_hits 10 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 78639 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78649 # Number of cache demand accesses
system.ruby.l1_cntrl0.L2cache.demand_hits 70 # Number of cache demand hits
system.ruby.l1_cntrl0.L2cache.demand_misses 78569 # Number of cache demand misses
system.ruby.l1_cntrl0.L2cache.demand_accesses 78639 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.fully_busy_cycles 19 # cycles for which number of transistions == max transitions
system.ruby.l1_cntrl1.L1Dcache.demand_hits 13 # Number of cache demand hits
system.ruby.l1_cntrl1.L1Dcache.demand_misses 78770 # Number of cache demand misses
system.ruby.l1_cntrl1.L2cache.demand_hits 66 # Number of cache demand hits
system.ruby.l1_cntrl1.L2cache.demand_misses 78704 # Number of cache demand misses
system.ruby.l1_cntrl1.L2cache.demand_accesses 78770 # Number of cache demand accesses
+system.ruby.l1_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl1.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl1.fully_busy_cycles 15 # cycles for which number of transistions == max transitions
system.ruby.l1_cntrl2.L1Dcache.demand_hits 19 # Number of cache demand hits
system.ruby.l1_cntrl2.L1Dcache.demand_misses 78920 # Number of cache demand misses
system.ruby.l1_cntrl2.L2cache.demand_hits 68 # Number of cache demand hits
system.ruby.l1_cntrl2.L2cache.demand_misses 78852 # Number of cache demand misses
system.ruby.l1_cntrl2.L2cache.demand_accesses 78920 # Number of cache demand accesses
+system.ruby.l1_cntrl2.sequencer.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl2.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl2.fully_busy_cycles 16 # cycles for which number of transistions == max transitions
system.ruby.l1_cntrl3.L1Dcache.demand_hits 12 # Number of cache demand hits
system.ruby.l1_cntrl3.L1Dcache.demand_misses 78627 # Number of cache demand misses
system.ruby.l1_cntrl3.L2cache.demand_hits 62 # Number of cache demand hits
system.ruby.l1_cntrl3.L2cache.demand_misses 78565 # Number of cache demand misses
system.ruby.l1_cntrl3.L2cache.demand_accesses 78627 # Number of cache demand accesses
+system.ruby.l1_cntrl3.sequencer.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl3.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl3.fully_busy_cycles 14 # cycles for which number of transistions == max transitions
system.ruby.l1_cntrl4.L1Dcache.demand_hits 19 # Number of cache demand hits
system.ruby.l1_cntrl4.L1Dcache.demand_misses 78575 # Number of cache demand misses
system.ruby.l1_cntrl4.L2cache.demand_hits 52 # Number of cache demand hits
system.ruby.l1_cntrl4.L2cache.demand_misses 78523 # Number of cache demand misses
system.ruby.l1_cntrl4.L2cache.demand_accesses 78575 # Number of cache demand accesses
+system.ruby.l1_cntrl4.sequencer.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl4.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl4.fully_busy_cycles 17 # cycles for which number of transistions == max transitions
system.ruby.l1_cntrl5.L1Dcache.demand_hits 19 # Number of cache demand hits
system.ruby.l1_cntrl5.L1Dcache.demand_misses 78844 # Number of cache demand misses
system.ruby.l1_cntrl5.L2cache.demand_hits 64 # Number of cache demand hits
system.ruby.l1_cntrl5.L2cache.demand_misses 78780 # Number of cache demand misses
system.ruby.l1_cntrl5.L2cache.demand_accesses 78844 # Number of cache demand accesses
+system.ruby.l1_cntrl5.sequencer.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl5.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl5.fully_busy_cycles 18 # cycles for which number of transistions == max transitions
system.ruby.l1_cntrl6.L1Dcache.demand_hits 20 # Number of cache demand hits
system.ruby.l1_cntrl6.L1Dcache.demand_misses 78880 # Number of cache demand misses
system.ruby.l1_cntrl6.L2cache.demand_hits 70 # Number of cache demand hits
system.ruby.l1_cntrl6.L2cache.demand_misses 78810 # Number of cache demand misses
system.ruby.l1_cntrl6.L2cache.demand_accesses 78880 # Number of cache demand accesses
+system.ruby.l1_cntrl6.sequencer.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl6.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl6.fully_busy_cycles 21 # cycles for which number of transistions == max transitions
system.ruby.l1_cntrl7.L1Dcache.demand_hits 14 # Number of cache demand hits
system.ruby.l1_cntrl7.L1Dcache.demand_misses 78558 # Number of cache demand misses
system.ruby.l1_cntrl7.L2cache.demand_hits 84 # Number of cache demand hits
system.ruby.l1_cntrl7.L2cache.demand_misses 78474 # Number of cache demand misses
system.ruby.l1_cntrl7.L2cache.demand_accesses 78558 # Number of cache demand accesses
+system.ruby.l1_cntrl7.sequencer.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl7.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl7.fully_busy_cycles 9 # cycles for which number of transistions == max transitions
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.percent_links_utilized 15.732330
system.ruby.network.routers0.msg_count.Request_Control::2 78569
system.ruby.network.routers0.msg_count.Request_Control::3 120
system.ruby.network.routers0.msg_bytes.Writeback_Control::5 371040
system.ruby.network.routers0.msg_bytes.Broadcast_Control::3 4398864
system.ruby.network.routers0.msg_bytes.Unblock_Control::5 630016
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
system.ruby.network.routers1.percent_links_utilized 15.771198
system.ruby.network.routers1.msg_count.Request_Control::2 78704
system.ruby.network.routers1.msg_count.Request_Control::3 125
system.ruby.network.routers1.msg_bytes.Writeback_Control::5 370416
system.ruby.network.routers1.msg_bytes.Broadcast_Control::3 4397704
system.ruby.network.routers1.msg_bytes.Unblock_Control::5 631088
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
system.ruby.network.routers2.percent_links_utilized 15.778059
system.ruby.network.routers2.msg_count.Request_Control::2 78852
system.ruby.network.routers2.msg_count.Request_Control::3 126
system.ruby.network.routers2.msg_bytes.Writeback_Control::5 372080
system.ruby.network.routers2.msg_bytes.Broadcast_Control::3 4396552
system.ruby.network.routers2.msg_bytes.Unblock_Control::5 632224
+system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
system.ruby.network.routers3.percent_links_utilized 15.737131
system.ruby.network.routers3.msg_count.Request_Control::2 78565
system.ruby.network.routers3.msg_count.Request_Control::3 100
system.ruby.network.routers3.msg_bytes.Writeback_Control::5 370360
system.ruby.network.routers3.msg_bytes.Broadcast_Control::3 4398936
system.ruby.network.routers3.msg_bytes.Unblock_Control::5 629800
+system.ruby.network.routers4.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
system.ruby.network.routers4.percent_links_utilized 15.736924
system.ruby.network.routers4.msg_count.Request_Control::2 78523
system.ruby.network.routers4.msg_count.Request_Control::3 120
system.ruby.network.routers4.msg_bytes.Writeback_Control::5 371136
system.ruby.network.routers4.msg_bytes.Broadcast_Control::3 4399192
system.ruby.network.routers4.msg_bytes.Unblock_Control::5 629616
+system.ruby.network.routers5.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
system.ruby.network.routers5.percent_links_utilized 15.767186
system.ruby.network.routers5.msg_count.Request_Control::2 78780
system.ruby.network.routers5.msg_count.Request_Control::3 112
system.ruby.network.routers5.msg_bytes.Writeback_Control::5 371664
system.ruby.network.routers5.msg_bytes.Broadcast_Control::3 4397184
system.ruby.network.routers5.msg_bytes.Unblock_Control::5 631696
+system.ruby.network.routers6.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
system.ruby.network.routers6.percent_links_utilized 15.767377
system.ruby.network.routers6.msg_count.Request_Control::2 78810
system.ruby.network.routers6.msg_count.Request_Control::3 118
system.ruby.network.routers6.msg_bytes.Writeback_Control::5 373176
system.ruby.network.routers6.msg_bytes.Broadcast_Control::3 4397000
system.ruby.network.routers6.msg_bytes.Unblock_Control::5 631896
+system.ruby.network.routers7.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
system.ruby.network.routers7.percent_links_utilized 15.733208
system.ruby.network.routers7.msg_count.Request_Control::2 78474
system.ruby.network.routers7.msg_count.Request_Control::3 141
system.ruby.network.routers7.msg_bytes.Writeback_Control::5 370352
system.ruby.network.routers7.msg_bytes.Broadcast_Control::3 4399536
system.ruby.network.routers7.msg_bytes.Unblock_Control::5 629248
+system.ruby.network.routers8.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
system.ruby.network.routers8.percent_links_utilized 57.778553
system.ruby.network.routers8.msg_count.Request_Control::2 629277
system.ruby.network.routers8.msg_count.Request_Control::3 962
system.ruby.network.routers8.msg_bytes.Writeback_Control::5 2970224
system.ruby.network.routers8.msg_bytes.Broadcast_Control::3 5026424
system.ruby.network.routers8.msg_bytes.Unblock_Control::5 5045576
+system.ruby.network.routers9.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
system.ruby.network.routers9.percent_links_utilized 22.639639
system.ruby.network.routers9.msg_count.Request_Control::2 629277
system.ruby.network.routers9.msg_count.Request_Control::3 962
system.ruby.network.routers9.msg_bytes.Writeback_Control::5 2970224
system.ruby.network.routers9.msg_bytes.Broadcast_Control::3 35184968
system.ruby.network.routers9.msg_bytes.Unblock_Control::5 5045576
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Request_Control 1890717
system.ruby.network.msg_count.Response_Data 1887741
system.ruby.network.msg_count.Response_Control 13136322
system.ruby.network.msg_byte.Writeback_Control 37400648
system.ruby.network.msg_byte.Broadcast_Control 75396360
system.ruby.network.msg_byte.Unblock_Control 15136736
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 4722948 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.throttle0.link_utilization 19.878030
system.ruby.network.routers0.throttle0.msg_count.Request_Control::3 120
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 78565
sim_ticks 7678882 # Number of ticks simulated
final_tick 7678882 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 120821 # Simulator tick rate (ticks/s)
-host_mem_usage 418672 # Number of bytes of host memory used
-host_seconds 63.56 # Real time elapsed on the host
+host_tick_rate 172641 # Simulator tick rate (ticks/s)
+host_mem_usage 467856 # Number of bytes of host memory used
+host_seconds 44.48 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39687936 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 39687936 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 39686592 # Number of bytes written to this memory
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 1 # Clock period in ticks
+system.cpu0.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
system.cpu0.num_reads 99754 # number of read accesses completed
system.cpu0.num_writes 55550 # number of write accesses completed
+system.cpu1.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
system.cpu1.num_reads 99722 # number of read accesses completed
system.cpu1.num_writes 55422 # number of write accesses completed
+system.cpu2.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
system.cpu2.num_reads 99859 # number of read accesses completed
system.cpu2.num_writes 56114 # number of write accesses completed
+system.cpu3.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
system.cpu3.num_reads 99399 # number of read accesses completed
system.cpu3.num_writes 55238 # number of write accesses completed
+system.cpu4.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
system.cpu4.num_reads 99564 # number of read accesses completed
system.cpu4.num_writes 55685 # number of write accesses completed
+system.cpu5.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
system.cpu5.num_reads 100000 # number of read accesses completed
system.cpu5.num_writes 55705 # number of write accesses completed
+system.cpu6.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
system.cpu6.num_reads 99381 # number of read accesses completed
system.cpu6.num_writes 55293 # number of write accesses completed
+system.cpu7.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
system.cpu7.num_reads 99930 # number of read accesses completed
system.cpu7.num_writes 55169 # number of write accesses completed
system.ruby.clk_domain.clock 1 # Clock period in ticks
+system.ruby.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
system.ruby.delayHist::bucket_size 32 # delay histogram for all message
system.ruby.delayHist::max_bucket 319 # delay histogram for all message
system.ruby.delayHist::samples 1260795 # delay histogram for all message
system.ruby.miss_latency_hist_seqr::total 628456
system.ruby.L1Cache.incomplete_times_seqr 8337
system.ruby.Directory.incomplete_times_seqr 620116
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.cacheMemory.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl0.cacheMemory.demand_misses 78526 # Number of cache demand misses
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 78526 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl1.cacheMemory.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl1.cacheMemory.demand_misses 78474 # Number of cache demand misses
system.ruby.l1_cntrl1.cacheMemory.demand_accesses 78474 # Number of cache demand accesses
+system.ruby.l1_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl1.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl2.cacheMemory.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl2.cacheMemory.demand_misses 78844 # Number of cache demand misses
system.ruby.l1_cntrl2.cacheMemory.demand_accesses 78844 # Number of cache demand accesses
+system.ruby.l1_cntrl2.sequencer.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl2.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl3.cacheMemory.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl3.cacheMemory.demand_misses 78573 # Number of cache demand misses
system.ruby.l1_cntrl3.cacheMemory.demand_accesses 78573 # Number of cache demand accesses
+system.ruby.l1_cntrl3.sequencer.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl3.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl4.cacheMemory.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl4.cacheMemory.demand_misses 78575 # Number of cache demand misses
system.ruby.l1_cntrl4.cacheMemory.demand_accesses 78575 # Number of cache demand accesses
+system.ruby.l1_cntrl4.sequencer.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl4.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl5.cacheMemory.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl5.cacheMemory.demand_misses 78529 # Number of cache demand misses
system.ruby.l1_cntrl5.cacheMemory.demand_accesses 78529 # Number of cache demand accesses
+system.ruby.l1_cntrl5.sequencer.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl5.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl6.cacheMemory.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl6.cacheMemory.demand_misses 78440 # Number of cache demand misses
system.ruby.l1_cntrl6.cacheMemory.demand_accesses 78440 # Number of cache demand accesses
+system.ruby.l1_cntrl6.sequencer.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl6.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl7.cacheMemory.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl7.cacheMemory.demand_misses 78515 # Number of cache demand misses
system.ruby.l1_cntrl7.cacheMemory.demand_accesses 78515 # Number of cache demand accesses
+system.ruby.l1_cntrl7.sequencer.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl7.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.percent_links_utilized 5.128100
system.ruby.network.routers0.msg_count.Control::2 78526
system.ruby.network.routers0.msg_count.Data::2 77981
system.ruby.network.routers0.msg_bytes.Data::2 5614632
system.ruby.network.routers0.msg_bytes.Response_Data::4 5726232
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 631912
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
system.ruby.network.routers1.percent_links_utilized 5.125007
system.ruby.network.routers1.msg_count.Control::2 78474
system.ruby.network.routers1.msg_count.Data::2 77933
system.ruby.network.routers1.msg_bytes.Data::2 5611176
system.ruby.network.routers1.msg_bytes.Response_Data::4 5722848
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 631568
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
system.ruby.network.routers2.percent_links_utilized 5.149581
system.ruby.network.routers2.msg_count.Control::2 78844
system.ruby.network.routers2.msg_count.Data::2 78287
system.ruby.network.routers2.msg_bytes.Data::2 5636664
system.ruby.network.routers2.msg_bytes.Response_Data::4 5751720
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 634632
+system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
system.ruby.network.routers3.percent_links_utilized 5.132918
system.ruby.network.routers3.msg_count.Control::2 78573
system.ruby.network.routers3.msg_count.Data::2 78015
system.ruby.network.routers3.msg_bytes.Data::2 5617080
system.ruby.network.routers3.msg_bytes.Response_Data::4 5734440
system.ruby.network.routers3.msg_bytes.Writeback_Control::3 632720
+system.ruby.network.routers4.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
system.ruby.network.routers4.percent_links_utilized 5.131284
system.ruby.network.routers4.msg_count.Control::2 78575
system.ruby.network.routers4.msg_count.Data::2 78023
system.ruby.network.routers4.msg_bytes.Data::2 5617656
system.ruby.network.routers4.msg_bytes.Response_Data::4 5730264
system.ruby.network.routers4.msg_bytes.Writeback_Control::3 632288
+system.ruby.network.routers5.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
system.ruby.network.routers5.percent_links_utilized 5.129285
system.ruby.network.routers5.msg_count.Control::2 78525
system.ruby.network.routers5.msg_count.Data::2 77953
system.ruby.network.routers5.msg_bytes.Data::2 5612616
system.ruby.network.routers5.msg_bytes.Response_Data::4 5730912
system.ruby.network.routers5.msg_bytes.Writeback_Control::3 632192
+system.ruby.network.routers6.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
system.ruby.network.routers6.percent_links_utilized 5.123636
system.ruby.network.routers6.msg_count.Control::2 78440
system.ruby.network.routers6.msg_count.Data::2 77859
system.ruby.network.routers6.msg_bytes.Data::2 5605848
system.ruby.network.routers6.msg_bytes.Response_Data::4 5725152
system.ruby.network.routers6.msg_bytes.Writeback_Control::3 631496
+system.ruby.network.routers7.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
system.ruby.network.routers7.percent_links_utilized 5.127709
system.ruby.network.routers7.msg_count.Control::2 78515
system.ruby.network.routers7.msg_count.Data::2 77951
system.ruby.network.routers7.msg_bytes.Data::2 5612472
system.ruby.network.routers7.msg_bytes.Response_Data::4 5727528
system.ruby.network.routers7.msg_bytes.Writeback_Control::3 631904
+system.ruby.network.routers8.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
system.ruby.network.routers8.percent_links_utilized 40.558977
system.ruby.network.routers8.msg_count.Control::2 628472
system.ruby.network.routers8.msg_count.Data::2 624002
system.ruby.network.routers8.msg_bytes.Data::2 44928144
system.ruby.network.routers8.msg_bytes.Response_Data::4 44648640
system.ruby.network.routers8.msg_bytes.Writeback_Control::3 5058712
+system.ruby.network.routers9.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
system.ruby.network.routers9.percent_links_utilized 9.067388
system.ruby.network.routers9.msg_count.Control::2 628472
system.ruby.network.routers9.msg_count.Data::2 624002
system.ruby.network.routers9.msg_bytes.Data::2 44928144
system.ruby.network.routers9.msg_bytes.Response_Data::4 45248832
system.ruby.network.routers9.msg_bytes.Writeback_Control::3 5058712
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Control 1885416
system.ruby.network.msg_count.Data 1872006
system.ruby.network.msg_count.Response_Data 1885369
system.ruby.network.msg_byte.Data 134784432
system.ruby.network.msg_byte.Response_Data 135746568
system.ruby.network.msg_byte.Writeback_Control 15176136
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 7678882 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.throttle0.link_utilization 5.115953
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 78523
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 78989
sim_ticks 501584000 # Number of ticks simulated
final_tick 501584000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 82658959 # Simulator tick rate (ticks/s)
-host_mem_usage 231728 # Number of bytes of host memory used
-host_seconds 6.07 # Real time elapsed on the host
+host_tick_rate 130273139 # Simulator tick rate (ticks/s)
+host_mem_usage 277304 # Number of bytes of host memory used
+host_seconds 3.85 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0 77173 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1 79943 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2 80467 # Number of bytes read from this memory
system.physmem.bw_total::cpu6 169419280 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu7 163206960 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2146087196 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu0.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states
system.cpu0.num_reads 99682 # number of read accesses completed
system.cpu0.num_writes 55240 # number of write accesses completed
+system.cpu0.l1c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states
system.cpu0.l1c.tags.replacements 22392 # number of replacements
system.cpu0.l1c.tags.tagsinuse 393.390751 # Cycle average of tags in use
system.cpu0.l1c.tags.total_refs 13565 # Total number of references to valid blocks.
system.cpu0.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id
system.cpu0.l1c.tags.tag_accesses 339133 # Number of tag accesses
system.cpu0.l1c.tags.data_accesses 339133 # Number of data accesses
+system.cpu0.l1c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states
system.cpu0.l1c.ReadReq_hits::cpu0 8847 # number of ReadReq hits
system.cpu0.l1c.ReadReq_hits::total 8847 # number of ReadReq hits
system.cpu0.l1c.WriteReq_hits::cpu0 1120 # number of WriteReq hits
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76081.849950 # average ReadReq mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 49324.292359 # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 49324.292359 # average overall mshr uncacheable latency
+system.cpu1.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states
system.cpu1.num_reads 99541 # number of read accesses completed
system.cpu1.num_writes 55028 # number of write accesses completed
+system.cpu1.l1c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states
system.cpu1.l1c.tags.replacements 22314 # number of replacements
system.cpu1.l1c.tags.tagsinuse 393.210618 # Cycle average of tags in use
system.cpu1.l1c.tags.total_refs 13573 # Total number of references to valid blocks.
system.cpu1.l1c.tags.occ_task_id_percent::1024 0.796875 # Percentage of cache occupancy per task id
system.cpu1.l1c.tags.tag_accesses 338638 # Number of tag accesses
system.cpu1.l1c.tags.data_accesses 338638 # Number of data accesses
+system.cpu1.l1c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states
system.cpu1.l1c.ReadReq_hits::cpu1 8704 # number of ReadReq hits
system.cpu1.l1c.ReadReq_hits::total 8704 # number of ReadReq hits
system.cpu1.l1c.WriteReq_hits::cpu1 1149 # number of WriteReq hits
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76088.624594 # average ReadReq mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 48764.745176 # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 48764.745176 # average overall mshr uncacheable latency
+system.cpu2.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states
system.cpu2.num_reads 99993 # number of read accesses completed
system.cpu2.num_writes 55211 # number of write accesses completed
+system.cpu2.l1c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states
system.cpu2.l1c.tags.replacements 22333 # number of replacements
system.cpu2.l1c.tags.tagsinuse 392.533782 # Cycle average of tags in use
system.cpu2.l1c.tags.total_refs 13552 # Total number of references to valid blocks.
system.cpu2.l1c.tags.occ_task_id_percent::1024 0.828125 # Percentage of cache occupancy per task id
system.cpu2.l1c.tags.tag_accesses 338842 # Number of tag accesses
system.cpu2.l1c.tags.data_accesses 338842 # Number of data accesses
+system.cpu2.l1c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states
system.cpu2.l1c.ReadReq_hits::cpu2 8700 # number of ReadReq hits
system.cpu2.l1c.ReadReq_hits::total 8700 # number of ReadReq hits
system.cpu2.l1c.WriteReq_hits::cpu2 1131 # number of WriteReq hits
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75960.835082 # average ReadReq mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 49072.651579 # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 49072.651579 # average overall mshr uncacheable latency
+system.cpu3.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states
system.cpu3.num_reads 99085 # number of read accesses completed
system.cpu3.num_writes 55606 # number of write accesses completed
+system.cpu3.l1c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states
system.cpu3.l1c.tags.replacements 22528 # number of replacements
system.cpu3.l1c.tags.tagsinuse 391.624901 # Cycle average of tags in use
system.cpu3.l1c.tags.total_refs 13493 # Total number of references to valid blocks.
system.cpu3.l1c.tags.occ_task_id_percent::1024 0.744141 # Percentage of cache occupancy per task id
system.cpu3.l1c.tags.tag_accesses 339302 # Number of tag accesses
system.cpu3.l1c.tags.data_accesses 339302 # Number of data accesses
+system.cpu3.l1c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states
system.cpu3.l1c.ReadReq_hits::cpu3 8770 # number of ReadReq hits
system.cpu3.l1c.ReadReq_hits::total 8770 # number of ReadReq hits
system.cpu3.l1c.WriteReq_hits::cpu3 1134 # number of WriteReq hits
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76104.905863 # average ReadReq mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 48577.705245 # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 48577.705245 # average overall mshr uncacheable latency
+system.cpu4.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states
system.cpu4.num_reads 99978 # number of read accesses completed
system.cpu4.num_writes 55474 # number of write accesses completed
+system.cpu4.l1c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states
system.cpu4.l1c.tags.replacements 22223 # number of replacements
system.cpu4.l1c.tags.tagsinuse 391.899958 # Cycle average of tags in use
system.cpu4.l1c.tags.total_refs 13858 # Total number of references to valid blocks.
system.cpu4.l1c.tags.occ_task_id_percent::1024 0.791016 # Percentage of cache occupancy per task id
system.cpu4.l1c.tags.tag_accesses 340964 # Number of tag accesses
system.cpu4.l1c.tags.data_accesses 340964 # Number of data accesses
+system.cpu4.l1c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states
system.cpu4.l1c.ReadReq_hits::cpu4 8890 # number of ReadReq hits
system.cpu4.l1c.ReadReq_hits::total 8890 # number of ReadReq hits
system.cpu4.l1c.WriteReq_hits::cpu4 1171 # number of WriteReq hits
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76323.866340 # average ReadReq mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 48895.366625 # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 48895.366625 # average overall mshr uncacheable latency
+system.cpu5.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states
system.cpu5.num_reads 100000 # number of read accesses completed
system.cpu5.num_writes 55110 # number of write accesses completed
+system.cpu5.l1c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states
system.cpu5.l1c.tags.replacements 22358 # number of replacements
system.cpu5.l1c.tags.tagsinuse 391.816568 # Cycle average of tags in use
system.cpu5.l1c.tags.total_refs 13630 # Total number of references to valid blocks.
system.cpu5.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id
system.cpu5.l1c.tags.tag_accesses 340100 # Number of tag accesses
system.cpu5.l1c.tags.data_accesses 340100 # Number of data accesses
+system.cpu5.l1c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states
system.cpu5.l1c.ReadReq_hits::cpu5 8821 # number of ReadReq hits
system.cpu5.l1c.ReadReq_hits::total 8821 # number of ReadReq hits
system.cpu5.l1c.WriteReq_hits::cpu5 1107 # number of WriteReq hits
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76212.561495 # average ReadReq mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 49035.755617 # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 49035.755617 # average overall mshr uncacheable latency
+system.cpu6.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states
system.cpu6.num_reads 99774 # number of read accesses completed
system.cpu6.num_writes 55185 # number of write accesses completed
+system.cpu6.l1c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states
system.cpu6.l1c.tags.replacements 22542 # number of replacements
system.cpu6.l1c.tags.tagsinuse 391.726459 # Cycle average of tags in use
system.cpu6.l1c.tags.total_refs 13419 # Total number of references to valid blocks.
system.cpu6.l1c.tags.occ_task_id_percent::1024 0.755859 # Percentage of cache occupancy per task id
system.cpu6.l1c.tags.tag_accesses 339673 # Number of tag accesses
system.cpu6.l1c.tags.data_accesses 339673 # Number of data accesses
+system.cpu6.l1c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states
system.cpu6.l1c.ReadReq_hits::cpu6 8710 # number of ReadReq hits
system.cpu6.l1c.ReadReq_hits::total 8710 # number of ReadReq hits
system.cpu6.l1c.WriteReq_hits::cpu6 1147 # number of WriteReq hits
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76198.851155 # average ReadReq mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 48973.532326 # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 48973.532326 # average overall mshr uncacheable latency
+system.cpu7.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states
system.cpu7.num_reads 99703 # number of read accesses completed
system.cpu7.num_writes 55656 # number of write accesses completed
+system.cpu7.l1c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states
system.cpu7.l1c.tags.replacements 22447 # number of replacements
system.cpu7.l1c.tags.tagsinuse 392.675740 # Cycle average of tags in use
system.cpu7.l1c.tags.total_refs 13542 # Total number of references to valid blocks.
system.cpu7.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id
system.cpu7.l1c.tags.tag_accesses 338950 # Number of tag accesses
system.cpu7.l1c.tags.data_accesses 338950 # Number of data accesses
+system.cpu7.l1c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states
system.cpu7.l1c.ReadReq_hits::cpu7 8682 # number of ReadReq hits
system.cpu7.l1c.ReadReq_hits::total 8682 # number of ReadReq hits
system.cpu7.l1c.WriteReq_hits::cpu7 1173 # number of WriteReq hits
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76167.022510 # average ReadReq mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 49319.237441 # average overall mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 49319.237441 # average overall mshr uncacheable latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 13600 # number of replacements
system.l2c.tags.tagsinuse 785.994901 # Cycle average of tags in use
system.l2c.tags.total_refs 164496 # Total number of references to valid blocks.
system.l2c.tags.occ_task_id_percent::1024 0.772461 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 2102241 # Number of tag accesses
system.l2c.tags.data_accesses 2102241 # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 77703 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 77703 # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0 290 # number of UpgradeReq hits
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 78845 # Transaction distribution
system.membus.trans_dist::ReadResp 84388 # Transaction distribution
system.membus.trans_dist::WriteReq 43678 # Transaction distribution
system.toL2Bus.snoop_filter.tot_snoops 12239 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 5805 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 6434 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 78849 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 372013 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 43679 # Transaction distribution
sim_ticks 500337000 # Number of ticks simulated
final_tick 500337000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 90464630 # Simulator tick rate (ticks/s)
-host_mem_usage 231728 # Number of bytes of host memory used
-host_seconds 5.53 # Real time elapsed on the host
+host_tick_rate 117513072 # Simulator tick rate (ticks/s)
+host_mem_usage 278328 # Number of bytes of host memory used
+host_seconds 4.26 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0 75919 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1 81043 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2 80577 # Number of bytes read from this memory
system.physmem.bw_total::cpu6 177978043 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu7 166783588 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2162126727 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu0.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states
system.cpu0.num_reads 99905 # number of read accesses completed
system.cpu0.num_writes 55400 # number of write accesses completed
+system.cpu0.l1c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states
system.cpu0.l1c.tags.replacements 22463 # number of replacements
system.cpu0.l1c.tags.tagsinuse 391.153981 # Cycle average of tags in use
system.cpu0.l1c.tags.total_refs 13877 # Total number of references to valid blocks.
system.cpu0.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id
system.cpu0.l1c.tags.tag_accesses 340651 # Number of tag accesses
system.cpu0.l1c.tags.data_accesses 340651 # Number of data accesses
+system.cpu0.l1c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states
system.cpu0.l1c.ReadReq_hits::cpu0 8894 # number of ReadReq hits
system.cpu0.l1c.ReadReq_hits::total 8894 # number of ReadReq hits
system.cpu0.l1c.WriteReq_hits::cpu0 1261 # number of WriteReq hits
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75003.675562 # average ReadReq mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 48257.334148 # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 48257.334148 # average overall mshr uncacheable latency
+system.cpu1.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states
system.cpu1.num_reads 99552 # number of read accesses completed
system.cpu1.num_writes 55243 # number of write accesses completed
+system.cpu1.l1c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states
system.cpu1.l1c.tags.replacements 22440 # number of replacements
system.cpu1.l1c.tags.tagsinuse 392.475962 # Cycle average of tags in use
system.cpu1.l1c.tags.total_refs 13641 # Total number of references to valid blocks.
system.cpu1.l1c.tags.occ_task_id_percent::1024 0.802734 # Percentage of cache occupancy per task id
system.cpu1.l1c.tags.tag_accesses 339640 # Number of tag accesses
system.cpu1.l1c.tags.data_accesses 339640 # Number of data accesses
+system.cpu1.l1c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states
system.cpu1.l1c.ReadReq_hits::cpu1 8906 # number of ReadReq hits
system.cpu1.l1c.ReadReq_hits::total 8906 # number of ReadReq hits
system.cpu1.l1c.WriteReq_hits::cpu1 1136 # number of WriteReq hits
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74878.985934 # average ReadReq mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 48081.532234 # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 48081.532234 # average overall mshr uncacheable latency
+system.cpu2.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states
system.cpu2.num_reads 100001 # number of read accesses completed
system.cpu2.num_writes 55556 # number of write accesses completed
+system.cpu2.l1c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states
system.cpu2.l1c.tags.replacements 22129 # number of replacements
system.cpu2.l1c.tags.tagsinuse 390.469202 # Cycle average of tags in use
system.cpu2.l1c.tags.total_refs 13617 # Total number of references to valid blocks.
system.cpu2.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id
system.cpu2.l1c.tags.tag_accesses 339163 # Number of tag accesses
system.cpu2.l1c.tags.data_accesses 339163 # Number of data accesses
+system.cpu2.l1c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states
system.cpu2.l1c.ReadReq_hits::cpu2 8741 # number of ReadReq hits
system.cpu2.l1c.ReadReq_hits::total 8741 # number of ReadReq hits
system.cpu2.l1c.WriteReq_hits::cpu2 1177 # number of WriteReq hits
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74755.242364 # average ReadReq mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 48431.812549 # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 48431.812549 # average overall mshr uncacheable latency
+system.cpu3.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states
system.cpu3.num_reads 99831 # number of read accesses completed
system.cpu3.num_writes 55461 # number of write accesses completed
+system.cpu3.l1c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states
system.cpu3.l1c.tags.replacements 22291 # number of replacements
system.cpu3.l1c.tags.tagsinuse 391.006782 # Cycle average of tags in use
system.cpu3.l1c.tags.total_refs 13350 # Total number of references to valid blocks.
system.cpu3.l1c.tags.occ_task_id_percent::1024 0.761719 # Percentage of cache occupancy per task id
system.cpu3.l1c.tags.tag_accesses 338050 # Number of tag accesses
system.cpu3.l1c.tags.data_accesses 338050 # Number of data accesses
+system.cpu3.l1c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states
system.cpu3.l1c.ReadReq_hits::cpu3 8529 # number of ReadReq hits
system.cpu3.l1c.ReadReq_hits::total 8529 # number of ReadReq hits
system.cpu3.l1c.WriteReq_hits::cpu3 1176 # number of WriteReq hits
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75018.386537 # average ReadReq mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 47881.283715 # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 47881.283715 # average overall mshr uncacheable latency
+system.cpu4.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states
system.cpu4.num_reads 99911 # number of read accesses completed
system.cpu4.num_writes 55300 # number of write accesses completed
+system.cpu4.l1c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states
system.cpu4.l1c.tags.replacements 22364 # number of replacements
system.cpu4.l1c.tags.tagsinuse 391.705900 # Cycle average of tags in use
system.cpu4.l1c.tags.total_refs 13535 # Total number of references to valid blocks.
system.cpu4.l1c.tags.occ_task_id_percent::1024 0.798828 # Percentage of cache occupancy per task id
system.cpu4.l1c.tags.tag_accesses 339861 # Number of tag accesses
system.cpu4.l1c.tags.data_accesses 339861 # Number of data accesses
+system.cpu4.l1c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states
system.cpu4.l1c.ReadReq_hits::cpu4 8886 # number of ReadReq hits
system.cpu4.l1c.ReadReq_hits::total 8886 # number of ReadReq hits
system.cpu4.l1c.WriteReq_hits::cpu4 1168 # number of WriteReq hits
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74866.678445 # average ReadReq mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 48019.883304 # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 48019.883304 # average overall mshr uncacheable latency
+system.cpu5.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states
system.cpu5.num_reads 99665 # number of read accesses completed
system.cpu5.num_writes 55439 # number of write accesses completed
+system.cpu5.l1c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states
system.cpu5.l1c.tags.replacements 22286 # number of replacements
system.cpu5.l1c.tags.tagsinuse 391.859990 # Cycle average of tags in use
system.cpu5.l1c.tags.total_refs 13458 # Total number of references to valid blocks.
system.cpu5.l1c.tags.occ_task_id_percent::1024 0.814453 # Percentage of cache occupancy per task id
system.cpu5.l1c.tags.tag_accesses 338594 # Number of tag accesses
system.cpu5.l1c.tags.data_accesses 338594 # Number of data accesses
+system.cpu5.l1c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states
system.cpu5.l1c.ReadReq_hits::cpu5 8649 # number of ReadReq hits
system.cpu5.l1c.ReadReq_hits::total 8649 # number of ReadReq hits
system.cpu5.l1c.WriteReq_hits::cpu5 1196 # number of WriteReq hits
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74875.790313 # average ReadReq mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 48305.389102 # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 48305.389102 # average overall mshr uncacheable latency
+system.cpu6.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states
system.cpu6.num_reads 99712 # number of read accesses completed
system.cpu6.num_writes 55282 # number of write accesses completed
+system.cpu6.l1c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states
system.cpu6.l1c.tags.replacements 22239 # number of replacements
system.cpu6.l1c.tags.tagsinuse 392.046110 # Cycle average of tags in use
system.cpu6.l1c.tags.total_refs 13503 # Total number of references to valid blocks.
system.cpu6.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id
system.cpu6.l1c.tags.tag_accesses 338073 # Number of tag accesses
system.cpu6.l1c.tags.data_accesses 338073 # Number of data accesses
+system.cpu6.l1c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states
system.cpu6.l1c.ReadReq_hits::cpu6 8758 # number of ReadReq hits
system.cpu6.l1c.ReadReq_hits::total 8758 # number of ReadReq hits
system.cpu6.l1c.WriteReq_hits::cpu6 1067 # number of WriteReq hits
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74822.857824 # average ReadReq mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 47746.599431 # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 47746.599431 # average overall mshr uncacheable latency
+system.cpu7.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states
system.cpu7.num_reads 99031 # number of read accesses completed
system.cpu7.num_writes 54931 # number of write accesses completed
+system.cpu7.l1c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states
system.cpu7.l1c.tags.replacements 22638 # number of replacements
system.cpu7.l1c.tags.tagsinuse 391.993848 # Cycle average of tags in use
system.cpu7.l1c.tags.total_refs 13556 # Total number of references to valid blocks.
system.cpu7.l1c.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id
system.cpu7.l1c.tags.tag_accesses 339734 # Number of tag accesses
system.cpu7.l1c.tags.data_accesses 339734 # Number of data accesses
+system.cpu7.l1c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states
system.cpu7.l1c.ReadReq_hits::cpu7 8818 # number of ReadReq hits
system.cpu7.l1c.ReadReq_hits::total 8818 # number of ReadReq hits
system.cpu7.l1c.WriteReq_hits::cpu7 1148 # number of WriteReq hits
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75003.057084 # average ReadReq mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 48382.659514 # average overall mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 48382.659514 # average overall mshr uncacheable latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 13688 # number of replacements
system.l2c.tags.tagsinuse 782.559938 # Cycle average of tags in use
system.l2c.tags.total_refs 164623 # Total number of references to valid blocks.
system.l2c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 2107372 # Number of tag accesses
system.l2c.tags.data_accesses 2107372 # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 77671 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 77671 # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0 272 # number of UpgradeReq hits
system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 33149.271115 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 33500.900238 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 33381.197903 # average overall mshr uncacheable latency
+system.membus.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 78773 # Transaction distribution
system.membus.trans_dist::ReadResp 84410 # Transaction distribution
system.membus.trans_dist::WriteReq 43787 # Transaction distribution
system.toL2Bus.snoop_filter.tot_snoops 12293 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 5765 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 6528 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 78775 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 371396 # Transaction distribution
system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution
sim_ticks 44221003000 # Number of ticks simulated
final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1535738 # Simulator instruction rate (inst/s)
-host_op_rate 1535737 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 768748978 # Simulator tick rate (ticks/s)
-host_mem_usage 246592 # Number of bytes of host memory used
-host_seconds 57.52 # Real time elapsed on the host
+host_inst_rate 3085186 # Simulator instruction rate (inst/s)
+host_op_rate 3085185 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1544361453 # Simulator tick rate (ticks/s)
+host_mem_usage 293364 # Number of bytes of host memory used
+host_seconds 28.63 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 44221003000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 353752292 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 126702647 # Number of bytes read from this memory
system.physmem.bytes_read::total 480454939 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7999644241 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4937824296 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12937468537 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 44221003000 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 44221003000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 88442007 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 88438073 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 44221003000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 108714711 # Transaction distribution
system.membus.trans_dist::ReadResp 108714711 # Transaction distribution
system.membus.trans_dist::WriteReq 14613377 # Transaction distribution
sim_ticks 134741611500 # Number of ticks simulated
final_tick 134741611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 882134 # Simulator instruction rate (inst/s)
-host_op_rate 882134 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1345475029 # Simulator tick rate (ticks/s)
-host_mem_usage 255564 # Number of bytes of host memory used
-host_seconds 100.14 # Real time elapsed on the host
+host_inst_rate 1731648 # Simulator instruction rate (inst/s)
+host_op_rate 1731647 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2641194476 # Simulator tick rate (ticks/s)
+host_mem_usage 302344 # Number of bytes of host memory used
+host_seconds 51.02 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 367360 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10138112 # Number of bytes read from this memory
system.physmem.bytes_read::total 10505472 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 2726403 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 75241137 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 132297067 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 134741611500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 269483223 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 88438073 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 200248 # number of replacements
system.cpu.dcache.tags.tagsinuse 4078.397630 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 69984374 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 69984374 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 49986.498258 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49986.498258 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 49986.498258 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 74391 # number of replacements
system.cpu.icache.tags.tagsinuse 1870.507754 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.998535 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 176952584 # Number of tag accesses
system.cpu.icache.tags.data_accesses 176952584 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 15687.405149 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15687.405149 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 15687.405149 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 131998 # number of replacements
system.cpu.l2cache.tags.tagsinuse 30708.485304 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 247404 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978882 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4751004 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4751004 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 168278 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 168278 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 74391 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 3875 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3875 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 282660 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 74391 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 306516000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 33266 # Transaction distribution
system.membus.trans_dist::WritebackDirty 114382 # Transaction distribution
system.membus.trans_dist::CleanEvict 13845 # Transaction distribution
sim_ticks 48960022500 # Number of ticks simulated
final_tick 48960022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1798045 # Simulator instruction rate (inst/s)
-host_op_rate 2299450 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1241408996 # Simulator tick rate (ticks/s)
-host_mem_usage 309432 # Number of bytes of host memory used
-host_seconds 39.44 # Real time elapsed on the host
+host_inst_rate 1718625 # Simulator instruction rate (inst/s)
+host_op_rate 2197882 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1186575552 # Simulator tick rate (ticks/s)
+host_mem_usage 310104 # Number of bytes of host memory used
+host_seconds 41.26 # Real time elapsed on the host
sim_insts 70913204 # Number of instructions simulated
sim_ops 90688159 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 312580364 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 106573345 # Number of bytes read from this memory
system.physmem.bytes_read::total 419153709 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 6384399925 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3783363376 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10167763301 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 48960022500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 97920046 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 90690106 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 100925158 # Transaction distribution
system.membus.trans_dist::ReadResp 100941077 # Transaction distribution
system.membus.trans_dist::WriteReq 19849901 # Transaction distribution
sim_ticks 128076834500 # Number of ticks simulated
final_tick 128076834500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1113892 # Simulator instruction rate (inst/s)
-host_op_rate 1422128 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2027232976 # Simulator tick rate (ticks/s)
-host_mem_usage 319564 # Number of bytes of host memory used
-host_seconds 63.18 # Real time elapsed on the host
+host_inst_rate 1093594 # Simulator instruction rate (inst/s)
+host_op_rate 1396212 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1990290276 # Simulator tick rate (ticks/s)
+host_mem_usage 320240 # Number of bytes of host memory used
+host_seconds 64.35 # Real time elapsed on the host
sim_insts 70373651 # Number of instructions simulated
sim_ops 89847385 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 233152 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7925248 # Number of bytes read from this memory
system.physmem.bytes_read::total 8158400 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 1820407 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 61878856 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 106748422 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 128076834500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 256153669 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 90690106 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 155902 # number of replacements
system.cpu.dcache.tags.tagsinuse 4075.927155 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 42601677 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 22743361 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 22743361 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 49898.108565 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49964.608933 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 49964.608933 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 16890 # number of replacements
system.cpu.icache.tags.tagsinuse 1732.356634 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 78126184 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 156309092 # Number of tag accesses
system.cpu.icache.tags.data_accesses 156309092 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 78126184 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 78126184 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 78126184 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 95333 # number of replacements
system.cpu.l2cache.tags.tagsinuse 30336.891531 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 114380 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949768 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 3017503 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 3017503 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 128175 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 128175 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 15790 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 3119 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3089 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 214325 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 16890 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 25194 # Transaction distribution
system.membus.trans_dist::WritebackDirty 86150 # Transaction distribution
system.membus.trans_dist::CleanEvict 6168 # Transaction distribution
sim_ticks 68148677000 # Number of ticks simulated
final_tick 68148677000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1339454 # Simulator instruction rate (inst/s)
-host_op_rate 1356797 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 679186650 # Simulator tick rate (ticks/s)
-host_mem_usage 246572 # Number of bytes of host memory used
-host_seconds 100.34 # Real time elapsed on the host
+host_inst_rate 2845356 # Simulator instruction rate (inst/s)
+host_op_rate 2882198 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1442772972 # Simulator tick rate (ticks/s)
+host_mem_usage 292276 # Number of bytes of host memory used
+host_seconds 47.23 # Real time elapsed on the host
sim_insts 134398959 # Number of instructions simulated
sim_ops 136139187 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 68148677000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 538214320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 147559360 # Number of bytes read from this memory
system.physmem.bytes_read::total 685773680 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7897648842 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3484180771 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11381829614 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 68148677000 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 1946 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 68148677000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 136297355 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 136293808 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 68148677000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 171784880 # Transaction distribution
system.membus.trans_dist::ReadResp 171784880 # Transaction distribution
system.membus.trans_dist::WriteReq 20864304 # Transaction distribution
sim_ticks 203115946500 # Number of ticks simulated
final_tick 203115946500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 790551 # Simulator instruction rate (inst/s)
-host_op_rate 800787 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1194752753 # Simulator tick rate (ticks/s)
-host_mem_usage 255284 # Number of bytes of host memory used
-host_seconds 170.01 # Real time elapsed on the host
+host_inst_rate 1546845 # Simulator instruction rate (inst/s)
+host_op_rate 1566874 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2337732587 # Simulator tick rate (ticks/s)
+host_mem_usage 302284 # Number of bytes of host memory used
+host_seconds 86.89 # Real time elapsed on the host
sim_insts 134398959 # Number of instructions simulated
sim_ops 136139187 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 525056 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7828352 # Number of bytes read from this memory
system.physmem.bytes_read::total 8353408 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 2585006 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 38541297 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 67994110 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 1946 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 203115946500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 406231893 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 136293808 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 146583 # number of replacements
system.cpu.dcache.tags.tagsinuse 4087.268923 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 57960841 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 116373719 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 116373719 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 37185800 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 37185800 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 184976 # number of replacements
system.cpu.icache.tags.tagsinuse 2004.181265 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 134366557 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 269294186 # Number of tag accesses
system.cpu.icache.tags.data_accesses 269294186 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 134366557 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 134366557 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 134366557 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 99022 # number of replacements
system.cpu.l2cache.tags.tagsinuse 30843.699683 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 433832 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.947357 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 5588812 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 5588812 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 123865 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 123865 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 184923 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 3547 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3547 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 232524 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 209135 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 184976 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 226018500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 29258 # Transaction distribution
system.membus.trans_dist::WritebackDirty 85270 # Transaction distribution
system.membus.trans_dist::CleanEvict 10301 # Transaction distribution
sim_ticks 10000000000 # Number of ticks simulated
final_tick 10000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 621801419 # Simulator tick rate (ticks/s)
-host_mem_usage 1442452 # Number of bytes of host memory used
-host_seconds 16.08 # Real time elapsed on the host
+host_tick_rate 757790256 # Simulator tick rate (ticks/s)
+host_mem_usage 1498684 # Number of bytes of host memory used
+host_seconds 13.20 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::l0subsys0.tester0 2151552 # Number of bytes read from this memory
system.physmem.bytes_read::l0subsys0.tester1 2168960 # Number of bytes read from this memory
system.physmem.bytes_read::l0subsys1.tester0 2107520 # Number of bytes read from this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 9620586338 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
+system.l0subsys0.checkers0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
+system.l0subsys0.checkers1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
+system.l0subsys0.tester0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l0subsys0.tester0.numPackets 67424 # Number of packets generated
system.l0subsys0.tester0.numRetries 2732 # Number of retries
system.l0subsys0.tester0.retryTicks 71787172 # Time spent waiting due to back-pressure (ticks)
+system.l0subsys0.tester1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l0subsys0.tester1.numPackets 67451 # Number of packets generated
system.l0subsys0.tester1.numRetries 2817 # Number of retries
system.l0subsys0.tester1.retryTicks 69161680 # Time spent waiting due to back-pressure (ticks)
system.l0subsys0.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.l0subsys0.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.l0subsys0.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l0subsys0.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l0subsys0.xbar.trans_dist::ReadReq 86409 # Transaction distribution
system.l0subsys0.xbar.trans_dist::ReadResp 82049 # Transaction distribution
system.l0subsys0.xbar.trans_dist::ReadRespWithInvalidate 4359 # Transaction distribution
system.l0subsys0.xbar.respLayer0.utilization 1.2 # Layer utilization (%)
system.l0subsys0.xbar.respLayer1.occupancy 116411811 # Layer occupancy (ticks)
system.l0subsys0.xbar.respLayer1.utilization 1.2 # Layer utilization (%)
+system.l0subsys1.checkers0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
+system.l0subsys1.checkers1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
+system.l0subsys1.tester0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l0subsys1.tester0.numPackets 65180 # Number of packets generated
system.l0subsys1.tester0.numRetries 2851 # Number of retries
system.l0subsys1.tester0.retryTicks 74729692 # Time spent waiting due to back-pressure (ticks)
+system.l0subsys1.tester1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l0subsys1.tester1.numPackets 68174 # Number of packets generated
system.l0subsys1.tester1.numRetries 2790 # Number of retries
system.l0subsys1.tester1.retryTicks 74335880 # Time spent waiting due to back-pressure (ticks)
system.l0subsys1.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.l0subsys1.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.l0subsys1.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l0subsys1.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l0subsys1.xbar.trans_dist::ReadReq 85972 # Transaction distribution
system.l0subsys1.xbar.trans_dist::ReadResp 82000 # Transaction distribution
system.l0subsys1.xbar.trans_dist::ReadRespWithInvalidate 3972 # Transaction distribution
system.l0subsys1.xbar.respLayer0.utilization 1.1 # Layer utilization (%)
system.l0subsys1.xbar.respLayer1.occupancy 118377078 # Layer occupancy (ticks)
system.l0subsys1.xbar.respLayer1.utilization 1.2 # Layer utilization (%)
+system.l0subsys2.checkers0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
+system.l0subsys2.checkers1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
+system.l0subsys2.tester0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l0subsys2.tester0.numPackets 65223 # Number of packets generated
system.l0subsys2.tester0.numRetries 2584 # Number of retries
system.l0subsys2.tester0.retryTicks 64900705 # Time spent waiting due to back-pressure (ticks)
+system.l0subsys2.tester1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l0subsys2.tester1.numPackets 65256 # Number of packets generated
system.l0subsys2.tester1.numRetries 2558 # Number of retries
system.l0subsys2.tester1.retryTicks 64249844 # Time spent waiting due to back-pressure (ticks)
system.l0subsys2.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.l0subsys2.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.l0subsys2.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l0subsys2.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l0subsys2.xbar.trans_dist::ReadReq 84127 # Transaction distribution
system.l0subsys2.xbar.trans_dist::ReadResp 80122 # Transaction distribution
system.l0subsys2.xbar.trans_dist::ReadRespWithInvalidate 4004 # Transaction distribution
system.l0subsys2.xbar.respLayer0.utilization 1.1 # Layer utilization (%)
system.l0subsys2.xbar.respLayer1.occupancy 113314488 # Layer occupancy (ticks)
system.l0subsys2.xbar.respLayer1.utilization 1.1 # Layer utilization (%)
+system.l0subsys3.checkers0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
+system.l0subsys3.checkers1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
+system.l0subsys3.tester0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l0subsys3.tester0.numPackets 66015 # Number of packets generated
system.l0subsys3.tester0.numRetries 2474 # Number of retries
system.l0subsys3.tester0.retryTicks 61325178 # Time spent waiting due to back-pressure (ticks)
+system.l0subsys3.tester1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l0subsys3.tester1.numPackets 63774 # Number of packets generated
system.l0subsys3.tester1.numRetries 2406 # Number of retries
system.l0subsys3.tester1.retryTicks 60532485 # Time spent waiting due to back-pressure (ticks)
system.l0subsys3.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.l0subsys3.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.l0subsys3.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l0subsys3.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l0subsys3.xbar.trans_dist::ReadReq 83355 # Transaction distribution
system.l0subsys3.xbar.trans_dist::ReadResp 78973 # Transaction distribution
system.l0subsys3.xbar.trans_dist::ReadRespWithInvalidate 4382 # Transaction distribution
system.l0subsys3.xbar.respLayer0.utilization 1.1 # Layer utilization (%)
system.l0subsys3.xbar.respLayer1.occupancy 110374985 # Layer occupancy (ticks)
system.l0subsys3.xbar.respLayer1.utilization 1.1 # Layer utilization (%)
+system.l0subsys4.checkers0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
+system.l0subsys4.checkers1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
+system.l0subsys4.tester0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l0subsys4.tester0.numPackets 67184 # Number of packets generated
system.l0subsys4.tester0.numRetries 2523 # Number of retries
system.l0subsys4.tester0.retryTicks 66430147 # Time spent waiting due to back-pressure (ticks)
+system.l0subsys4.tester1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l0subsys4.tester1.numPackets 65756 # Number of packets generated
system.l0subsys4.tester1.numRetries 2580 # Number of retries
system.l0subsys4.tester1.retryTicks 67683660 # Time spent waiting due to back-pressure (ticks)
system.l0subsys4.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.l0subsys4.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.l0subsys4.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l0subsys4.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l0subsys4.xbar.trans_dist::ReadReq 85507 # Transaction distribution
system.l0subsys4.xbar.trans_dist::ReadResp 81442 # Transaction distribution
system.l0subsys4.xbar.trans_dist::ReadRespWithInvalidate 4064 # Transaction distribution
system.l0subsys4.xbar.respLayer0.utilization 1.2 # Layer utilization (%)
system.l0subsys4.xbar.respLayer1.occupancy 114597175 # Layer occupancy (ticks)
system.l0subsys4.xbar.respLayer1.utilization 1.1 # Layer utilization (%)
+system.l0subsys5.checkers0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
+system.l0subsys5.checkers1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
+system.l0subsys5.tester0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l0subsys5.tester0.numPackets 67119 # Number of packets generated
system.l0subsys5.tester0.numRetries 2560 # Number of retries
system.l0subsys5.tester0.retryTicks 65403498 # Time spent waiting due to back-pressure (ticks)
+system.l0subsys5.tester1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l0subsys5.tester1.numPackets 65308 # Number of packets generated
system.l0subsys5.tester1.numRetries 2642 # Number of retries
system.l0subsys5.tester1.retryTicks 65659220 # Time spent waiting due to back-pressure (ticks)
system.l0subsys5.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.l0subsys5.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.l0subsys5.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l0subsys5.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l0subsys5.xbar.trans_dist::ReadReq 85511 # Transaction distribution
system.l0subsys5.xbar.trans_dist::ReadResp 81276 # Transaction distribution
system.l0subsys5.xbar.trans_dist::ReadRespWithInvalidate 4233 # Transaction distribution
system.l0subsys5.xbar.respLayer0.utilization 1.2 # Layer utilization (%)
system.l0subsys5.xbar.respLayer1.occupancy 112976792 # Layer occupancy (ticks)
system.l0subsys5.xbar.respLayer1.utilization 1.1 # Layer utilization (%)
+system.l1subsys0.cache0.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l1subsys0.cache0.tags.replacements 67551 # number of replacements
system.l1subsys0.cache0.tags.tagsinuse 502.758409 # Cycle average of tags in use
system.l1subsys0.cache0.tags.total_refs 31003 # Total number of references to valid blocks.
system.l1subsys0.cache0.tags.occ_task_id_percent::1024 0.990234 # Percentage of cache occupancy per task id
system.l1subsys0.cache0.tags.tag_accesses 641417 # Number of tag accesses
system.l1subsys0.cache0.tags.data_accesses 641417 # Number of data accesses
+system.l1subsys0.cache0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l1subsys0.cache0.ReadReq_hits::l0subsys0.tester0 9938 # number of ReadReq hits
system.l1subsys0.cache0.ReadReq_hits::l0subsys0.tester1 9361 # number of ReadReq hits
system.l1subsys0.cache0.ReadReq_hits::total 19299 # number of ReadReq hits
system.l1subsys0.cache0.overall_avg_mshr_miss_latency::l0subsys0.tester0 90387.265234 # average overall mshr miss latency
system.l1subsys0.cache0.overall_avg_mshr_miss_latency::l0subsys0.tester1 89727.019386 # average overall mshr miss latency
system.l1subsys0.cache0.overall_avg_mshr_miss_latency::total 90055.037917 # average overall mshr miss latency
+system.l1subsys0.cache1.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l1subsys0.cache1.tags.replacements 68848 # number of replacements
system.l1subsys0.cache1.tags.tagsinuse 504.594743 # Cycle average of tags in use
system.l1subsys0.cache1.tags.total_refs 31105 # Total number of references to valid blocks.
system.l1subsys0.cache1.tags.occ_task_id_percent::1024 0.976562 # Percentage of cache occupancy per task id
system.l1subsys0.cache1.tags.tag_accesses 633805 # Number of tag accesses
system.l1subsys0.cache1.tags.data_accesses 633805 # Number of data accesses
+system.l1subsys0.cache1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l1subsys0.cache1.ReadReq_hits::l0subsys1.tester0 9817 # number of ReadReq hits
system.l1subsys0.cache1.ReadReq_hits::l0subsys1.tester1 9861 # number of ReadReq hits
system.l1subsys0.cache1.ReadReq_hits::total 19678 # number of ReadReq hits
system.l1subsys0.xbar.snoop_filter.tot_snoops 114062 # Total number of snoops made to the snoop filter.
system.l1subsys0.xbar.snoop_filter.hit_single_snoops 98725 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.l1subsys0.xbar.snoop_filter.hit_multi_snoops 15337 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l1subsys0.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l1subsys0.xbar.trans_dist::ReadResp 154200 # Transaction distribution
system.l1subsys0.xbar.trans_dist::ReadRespWithInvalidate 3741 # Transaction distribution
system.l1subsys0.xbar.trans_dist::WritebackDirty 97097 # Transaction distribution
system.l1subsys0.xbar.respLayer0.utilization 3.2 # Layer utilization (%)
system.l1subsys0.xbar.respLayer1.occupancy 314273952 # Layer occupancy (ticks)
system.l1subsys0.xbar.respLayer1.utilization 3.1 # Layer utilization (%)
+system.l1subsys1.cache0.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l1subsys1.cache0.tags.replacements 64055 # number of replacements
system.l1subsys1.cache0.tags.tagsinuse 501.915078 # Cycle average of tags in use
system.l1subsys1.cache0.tags.total_refs 31614 # Total number of references to valid blocks.
system.l1subsys1.cache0.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
system.l1subsys1.cache0.tags.tag_accesses 619158 # Number of tag accesses
system.l1subsys1.cache0.tags.data_accesses 619158 # Number of data accesses
+system.l1subsys1.cache0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l1subsys1.cache0.ReadReq_hits::l0subsys2.tester0 10039 # number of ReadReq hits
system.l1subsys1.cache0.ReadReq_hits::l0subsys2.tester1 9798 # number of ReadReq hits
system.l1subsys1.cache0.ReadReq_hits::total 19837 # number of ReadReq hits
system.l1subsys1.cache0.overall_avg_mshr_miss_latency::l0subsys2.tester0 90126.933848 # average overall mshr miss latency
system.l1subsys1.cache0.overall_avg_mshr_miss_latency::l0subsys2.tester1 89266.884167 # average overall mshr miss latency
system.l1subsys1.cache0.overall_avg_mshr_miss_latency::total 89695.571963 # average overall mshr miss latency
+system.l1subsys1.cache1.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l1subsys1.cache1.tags.replacements 63731 # number of replacements
system.l1subsys1.cache1.tags.tagsinuse 503.303418 # Cycle average of tags in use
system.l1subsys1.cache1.tags.total_refs 29004 # Total number of references to valid blocks.
system.l1subsys1.cache1.tags.occ_task_id_percent::1024 0.982422 # Percentage of cache occupancy per task id
system.l1subsys1.cache1.tags.tag_accesses 617940 # Number of tag accesses
system.l1subsys1.cache1.tags.data_accesses 617940 # Number of data accesses
+system.l1subsys1.cache1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l1subsys1.cache1.ReadReq_hits::l0subsys3.tester0 9182 # number of ReadReq hits
system.l1subsys1.cache1.ReadReq_hits::l0subsys3.tester1 9019 # number of ReadReq hits
system.l1subsys1.cache1.ReadReq_hits::total 18201 # number of ReadReq hits
system.l1subsys1.xbar.snoop_filter.tot_snoops 114270 # Total number of snoops made to the snoop filter.
system.l1subsys1.xbar.snoop_filter.hit_single_snoops 97861 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.l1subsys1.xbar.snoop_filter.hit_multi_snoops 16409 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l1subsys1.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l1subsys1.xbar.trans_dist::ReadResp 151000 # Transaction distribution
system.l1subsys1.xbar.trans_dist::ReadRespWithInvalidate 3767 # Transaction distribution
system.l1subsys1.xbar.trans_dist::WritebackDirty 90510 # Transaction distribution
system.l1subsys1.xbar.respLayer0.utilization 3.1 # Layer utilization (%)
system.l1subsys1.xbar.respLayer1.occupancy 309946184 # Layer occupancy (ticks)
system.l1subsys1.xbar.respLayer1.utilization 3.1 # Layer utilization (%)
+system.l1subsys2.cache0.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l1subsys2.cache0.tags.replacements 65353 # number of replacements
system.l1subsys2.cache0.tags.tagsinuse 504.458871 # Cycle average of tags in use
system.l1subsys2.cache0.tags.total_refs 33188 # Total number of references to valid blocks.
system.l1subsys2.cache0.tags.occ_task_id_percent::1024 0.986328 # Percentage of cache occupancy per task id
system.l1subsys2.cache0.tags.tag_accesses 629863 # Number of tag accesses
system.l1subsys2.cache0.tags.data_accesses 629863 # Number of data accesses
+system.l1subsys2.cache0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l1subsys2.cache0.ReadReq_hits::l0subsys4.tester0 10527 # number of ReadReq hits
system.l1subsys2.cache0.ReadReq_hits::l0subsys4.tester1 10271 # number of ReadReq hits
system.l1subsys2.cache0.ReadReq_hits::total 20798 # number of ReadReq hits
system.l1subsys2.cache0.overall_avg_mshr_miss_latency::l0subsys4.tester0 91822.941718 # average overall mshr miss latency
system.l1subsys2.cache0.overall_avg_mshr_miss_latency::l0subsys4.tester1 89290.677324 # average overall mshr miss latency
system.l1subsys2.cache0.overall_avg_mshr_miss_latency::total 90569.637316 # average overall mshr miss latency
+system.l1subsys2.cache1.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l1subsys2.cache1.tags.replacements 67065 # number of replacements
system.l1subsys2.cache1.tags.tagsinuse 502.741649 # Cycle average of tags in use
system.l1subsys2.cache1.tags.total_refs 30001 # Total number of references to valid blocks.
system.l1subsys2.cache1.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id
system.l1subsys2.cache1.tags.tag_accesses 630788 # Number of tag accesses
system.l1subsys2.cache1.tags.data_accesses 630788 # Number of data accesses
+system.l1subsys2.cache1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l1subsys2.cache1.ReadReq_hits::l0subsys5.tester0 9835 # number of ReadReq hits
system.l1subsys2.cache1.ReadReq_hits::l0subsys5.tester1 9033 # number of ReadReq hits
system.l1subsys2.cache1.ReadReq_hits::total 18868 # number of ReadReq hits
system.l1subsys2.xbar.snoop_filter.tot_snoops 114014 # Total number of snoops made to the snoop filter.
system.l1subsys2.xbar.snoop_filter.hit_single_snoops 99574 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.l1subsys2.xbar.snoop_filter.hit_multi_snoops 14440 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l1subsys2.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l1subsys2.xbar.trans_dist::ReadResp 152712 # Transaction distribution
system.l1subsys2.xbar.trans_dist::ReadRespWithInvalidate 3827 # Transaction distribution
system.l1subsys2.xbar.trans_dist::WritebackDirty 93911 # Transaction distribution
system.l1subsys2.xbar.respLayer0.utilization 3.1 # Layer utilization (%)
system.l1subsys2.xbar.respLayer1.occupancy 316356652 # Layer occupancy (ticks)
system.l1subsys2.xbar.respLayer1.utilization 3.2 # Layer utilization (%)
+system.l2subsys0.cache0.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l2subsys0.cache0.tags.replacements 33571 # number of replacements
system.l2subsys0.cache0.tags.tagsinuse 498.351113 # Cycle average of tags in use
system.l2subsys0.cache0.tags.total_refs 14579 # Total number of references to valid blocks.
system.l2subsys0.cache0.tags.occ_task_id_percent::1024 0.990234 # Percentage of cache occupancy per task id
system.l2subsys0.cache0.tags.tag_accesses 327999 # Number of tag accesses
system.l2subsys0.cache0.tags.data_accesses 327999 # Number of data accesses
+system.l2subsys0.cache0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l2subsys0.cache0.ReadReq_hits::l2subsys0.tester 9421 # number of ReadReq hits
system.l2subsys0.cache0.ReadReq_hits::total 9421 # number of ReadReq hits
system.l2subsys0.cache0.WriteReq_hits::l2subsys0.tester 1165 # number of WriteReq hits
system.l2subsys0.cache0.demand_avg_mshr_miss_latency::total 65232.365364 # average overall mshr miss latency
system.l2subsys0.cache0.overall_avg_mshr_miss_latency::l2subsys0.tester 65232.365364 # average overall mshr miss latency
system.l2subsys0.cache0.overall_avg_mshr_miss_latency::total 65232.365364 # average overall mshr miss latency
+system.l2subsys0.cache1.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l2subsys0.cache1.tags.replacements 134581 # number of replacements
system.l2subsys0.cache1.tags.tagsinuse 1490.708088 # Cycle average of tags in use
system.l2subsys0.cache1.tags.total_refs 68619 # Total number of references to valid blocks.
system.l2subsys0.cache1.tags.occ_task_id_percent::1024 0.977214 # Percentage of cache occupancy per task id
system.l2subsys0.cache1.tags.tag_accesses 4309680 # Number of tag accesses
system.l2subsys0.cache1.tags.data_accesses 4309680 # Number of data accesses
+system.l2subsys0.cache1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l2subsys0.cache1.WritebackDirty_hits::writebacks 48994 # number of WritebackDirty hits
system.l2subsys0.cache1.WritebackDirty_hits::total 48994 # number of WritebackDirty hits
system.l2subsys0.cache1.ReadExReq_hits::l0subsys0.tester0 45 # number of ReadExReq hits
system.l2subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys1.tester0 88785.081065 # average overall mshr miss latency
system.l2subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys1.tester1 90884.489838 # average overall mshr miss latency
system.l2subsys0.cache1.overall_avg_mshr_miss_latency::total 88472.037304 # average overall mshr miss latency
+system.l2subsys0.cache2.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l2subsys0.cache2.tags.replacements 126032 # number of replacements
system.l2subsys0.cache2.tags.tagsinuse 1489.728979 # Cycle average of tags in use
system.l2subsys0.cache2.tags.total_refs 65365 # Total number of references to valid blocks.
system.l2subsys0.cache2.tags.occ_task_id_percent::1024 0.974609 # Percentage of cache occupancy per task id
system.l2subsys0.cache2.tags.tag_accesses 4109673 # Number of tag accesses
system.l2subsys0.cache2.tags.data_accesses 4109673 # Number of data accesses
+system.l2subsys0.cache2.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l2subsys0.cache2.WritebackDirty_hits::writebacks 45683 # number of WritebackDirty hits
system.l2subsys0.cache2.WritebackDirty_hits::total 45683 # number of WritebackDirty hits
system.l2subsys0.cache2.ReadExReq_hits::l0subsys2.tester0 37 # number of ReadExReq hits
system.l2subsys0.cache2.overall_avg_mshr_miss_latency::l0subsys3.tester0 86634.785961 # average overall mshr miss latency
system.l2subsys0.cache2.overall_avg_mshr_miss_latency::l0subsys3.tester1 86857.574211 # average overall mshr miss latency
system.l2subsys0.cache2.overall_avg_mshr_miss_latency::total 87244.093661 # average overall mshr miss latency
+system.l2subsys0.cache3.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l2subsys0.cache3.tags.replacements 130662 # number of replacements
system.l2subsys0.cache3.tags.tagsinuse 1489.946036 # Cycle average of tags in use
system.l2subsys0.cache3.tags.total_refs 67604 # Total number of references to valid blocks.
system.l2subsys0.cache3.tags.occ_task_id_percent::1024 0.975911 # Percentage of cache occupancy per task id
system.l2subsys0.cache3.tags.tag_accesses 4225473 # Number of tag accesses
system.l2subsys0.cache3.tags.data_accesses 4225473 # Number of data accesses
+system.l2subsys0.cache3.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l2subsys0.cache3.WritebackDirty_hits::writebacks 47372 # number of WritebackDirty hits
system.l2subsys0.cache3.WritebackDirty_hits::total 47372 # number of WritebackDirty hits
system.l2subsys0.cache3.ReadExReq_hits::l0subsys4.tester0 45 # number of ReadExReq hits
system.l2subsys0.cache3.overall_avg_mshr_miss_latency::l0subsys5.tester0 86334.880792 # average overall mshr miss latency
system.l2subsys0.cache3.overall_avg_mshr_miss_latency::l0subsys5.tester1 87645.156672 # average overall mshr miss latency
system.l2subsys0.cache3.overall_avg_mshr_miss_latency::total 87740.882016 # average overall mshr miss latency
+system.l2subsys0.checkers.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
+system.l2subsys0.tester.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l2subsys0.tester.numPackets 68517 # Number of packets generated
system.l2subsys0.tester.numRetries 121 # Number of retries
system.l2subsys0.tester.retryTicks 5829034 # Time spent waiting due to back-pressure (ticks)
system.l2subsys0.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.l2subsys0.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.l2subsys0.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l2subsys0.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states
system.l2subsys0.xbar.trans_dist::ReadResp 374921 # Transaction distribution
system.l2subsys0.xbar.trans_dist::ReadRespWithInvalidate 1348 # Transaction distribution
system.l2subsys0.xbar.trans_dist::WritebackDirty 151339 # Transaction distribution
sim_ticks 14181 # Number of ticks simulated
final_tick 14181 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 154609 # Simulator tick rate (ticks/s)
-host_mem_usage 480252 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
+host_tick_rate 238683 # Simulator tick rate (ticks/s)
+host_mem_usage 530468 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::dir_cntrl0 16576 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 16576 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::dir_cntrl0 576 # Number of bytes written to this memory
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
system.ruby.clk_domain.clock 1 # Clock period in ticks
+system.ruby.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
system.ruby.outstanding_req_hist_seqr::bucket_size 2
system.ruby.outstanding_req_hist_seqr::max_bucket 19
system.ruby.outstanding_req_hist_seqr::samples 63
system.cp_cntrl0.L2cache.num_data_array_writes 84 # number of data array writes
system.cp_cntrl0.L2cache.num_tag_array_reads 380 # number of tag array reads
system.cp_cntrl0.L2cache.num_tag_array_writes 371 # number of tag array writes
+system.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
system.cp_cntrl0.sequencer.store_waiting_on_load 2 # Number of times a store aliased with a pending load
system.cp_cntrl0.sequencer.store_waiting_on_store 3 # Number of times a store aliased with a pending store
+system.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
system.cp_cntrl0.sequencer1.store_waiting_on_load 1 # Number of times a store aliased with a pending load
system.cp_cntrl0.sequencer1.store_waiting_on_store 4 # Number of times a store aliased with a pending store
+system.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
system.cp_cntrl0.fully_busy_cycles 2 # cycles for which number of transistions == max transitions
+system.cpu.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
system.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits
system.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses
system.dir_cntrl0.L3CacheMemory.demand_accesses 0 # Number of cache demand accesses
system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 378 # number of tag array writes
system.dir_cntrl0.L3CacheMemory.num_tag_array_stalls 10169 # number of stalls caused by tag array
system.dir_cntrl0.L3CacheMemory.num_data_array_stalls 5502 # number of stalls caused by data array
+system.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
+system.ruby.network.ext_links00.int_node.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
system.ruby.network.ext_links00.int_node.percent_links_utilized 0.199210
system.ruby.network.ext_links00.int_node.msg_count.Control::0 308
system.ruby.network.ext_links00.int_node.msg_count.Request_Control::0 385
system.ruby.network.ext_links00.int_node.msg_bytes.Writeback_Data::2 4752
system.ruby.network.ext_links00.int_node.msg_bytes.Writeback_Control::2 560
system.ruby.network.ext_links00.int_node.msg_bytes.Unblock_Control::4 2424
+system.ruby.network.ext_links01.int_node.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
system.ruby.network.ext_links01.int_node.percent_links_utilized 0.120981
system.ruby.network.ext_links01.int_node.msg_count.Control::0 227
system.ruby.network.ext_links01.int_node.msg_count.Request_Control::0 153
system.tcp_cntrl0.L1cache.num_tag_array_reads 314 # number of tag array reads
system.tcp_cntrl0.L1cache.num_tag_array_writes 305 # number of tag array writes
system.tcp_cntrl0.L1cache.num_tag_array_stalls 38 # number of stalls caused by tag array
+system.tcp_cntrl0.coalescer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP
system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 5 # TCP to TCP load transfers
system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
system.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
system.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
system.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU
+system.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
+system.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
+system.ruby.network.ext_links02.int_node.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
system.ruby.network.ext_links02.int_node.percent_links_utilized 0.173894
system.ruby.network.ext_links02.int_node.msg_count.Control::0 81
system.ruby.network.ext_links02.int_node.msg_count.Control::1 814
system.tcp_cntrl1.L1cache.num_tag_array_reads 300 # number of tag array reads
system.tcp_cntrl1.L1cache.num_tag_array_writes 289 # number of tag array writes
system.tcp_cntrl1.L1cache.num_tag_array_stalls 44 # number of stalls caused by tag array
+system.tcp_cntrl1.coalescer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
system.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP
system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 4 # TCP to TCP load transfers
system.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
system.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
system.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
system.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU
+system.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
+system.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
system.tcp_cntrl2.L1cache.demand_hits 0 # Number of cache demand hits
system.tcp_cntrl2.L1cache.demand_misses 0 # Number of cache demand misses
system.tcp_cntrl2.L1cache.demand_accesses 0 # Number of cache demand accesses
system.tcp_cntrl2.L1cache.num_tag_array_writes 292 # number of tag array writes
system.tcp_cntrl2.L1cache.num_tag_array_stalls 36 # number of stalls caused by tag array
system.tcp_cntrl2.L1cache.num_data_array_stalls 3 # number of stalls caused by data array
+system.tcp_cntrl2.coalescer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
system.tcp_cntrl2.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP
system.tcp_cntrl2.coalescer.gpu_tcp_ld_transfers 9 # TCP to TCP load transfers
system.tcp_cntrl2.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
system.tcp_cntrl2.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
system.tcp_cntrl2.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
system.tcp_cntrl2.coalescer.cp_st_misses 0 # stores that miss in the GPU
+system.tcp_cntrl2.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
+system.tcp_cntrl2.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
system.tcp_cntrl3.L1cache.demand_hits 0 # Number of cache demand hits
system.tcp_cntrl3.L1cache.demand_misses 0 # Number of cache demand misses
system.tcp_cntrl3.L1cache.demand_accesses 0 # Number of cache demand accesses
system.tcp_cntrl3.L1cache.num_tag_array_writes 262 # number of tag array writes
system.tcp_cntrl3.L1cache.num_tag_array_stalls 16 # number of stalls caused by tag array
system.tcp_cntrl3.L1cache.num_data_array_stalls 3 # number of stalls caused by data array
+system.tcp_cntrl3.coalescer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
system.tcp_cntrl3.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP
system.tcp_cntrl3.coalescer.gpu_tcp_ld_transfers 13 # TCP to TCP load transfers
system.tcp_cntrl3.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
system.tcp_cntrl3.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
system.tcp_cntrl3.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
system.tcp_cntrl3.coalescer.cp_st_misses 0 # stores that miss in the GPU
+system.tcp_cntrl3.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
+system.tcp_cntrl3.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
system.tcp_cntrl4.L1cache.demand_hits 0 # Number of cache demand hits
system.tcp_cntrl4.L1cache.demand_misses 0 # Number of cache demand misses
system.tcp_cntrl4.L1cache.demand_accesses 0 # Number of cache demand accesses
system.tcp_cntrl4.L1cache.num_tag_array_reads 317 # number of tag array reads
system.tcp_cntrl4.L1cache.num_tag_array_writes 309 # number of tag array writes
system.tcp_cntrl4.L1cache.num_tag_array_stalls 29 # number of stalls caused by tag array
+system.tcp_cntrl4.coalescer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
system.tcp_cntrl4.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP
system.tcp_cntrl4.coalescer.gpu_tcp_ld_transfers 4 # TCP to TCP load transfers
system.tcp_cntrl4.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
system.tcp_cntrl4.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
system.tcp_cntrl4.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
system.tcp_cntrl4.coalescer.cp_st_misses 0 # stores that miss in the GPU
+system.tcp_cntrl4.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
+system.tcp_cntrl4.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
system.tcp_cntrl5.L1cache.demand_hits 0 # Number of cache demand hits
system.tcp_cntrl5.L1cache.demand_misses 0 # Number of cache demand misses
system.tcp_cntrl5.L1cache.demand_accesses 0 # Number of cache demand accesses
system.tcp_cntrl5.L1cache.num_tag_array_reads 295 # number of tag array reads
system.tcp_cntrl5.L1cache.num_tag_array_writes 287 # number of tag array writes
system.tcp_cntrl5.L1cache.num_tag_array_stalls 31 # number of stalls caused by tag array
+system.tcp_cntrl5.coalescer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
system.tcp_cntrl5.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP
system.tcp_cntrl5.coalescer.gpu_tcp_ld_transfers 6 # TCP to TCP load transfers
system.tcp_cntrl5.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
system.tcp_cntrl5.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
system.tcp_cntrl5.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
system.tcp_cntrl5.coalescer.cp_st_misses 0 # stores that miss in the GPU
+system.tcp_cntrl5.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
+system.tcp_cntrl5.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
system.tcp_cntrl6.L1cache.demand_hits 0 # Number of cache demand hits
system.tcp_cntrl6.L1cache.demand_misses 0 # Number of cache demand misses
system.tcp_cntrl6.L1cache.demand_accesses 0 # Number of cache demand accesses
system.tcp_cntrl6.L1cache.num_tag_array_reads 342 # number of tag array reads
system.tcp_cntrl6.L1cache.num_tag_array_writes 335 # number of tag array writes
system.tcp_cntrl6.L1cache.num_tag_array_stalls 49 # number of stalls caused by tag array
+system.tcp_cntrl6.coalescer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
system.tcp_cntrl6.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP
system.tcp_cntrl6.coalescer.gpu_tcp_ld_transfers 11 # TCP to TCP load transfers
system.tcp_cntrl6.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
system.tcp_cntrl6.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
system.tcp_cntrl6.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
system.tcp_cntrl6.coalescer.cp_st_misses 0 # stores that miss in the GPU
+system.tcp_cntrl6.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
+system.tcp_cntrl6.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
system.tcp_cntrl7.L1cache.demand_hits 0 # Number of cache demand hits
system.tcp_cntrl7.L1cache.demand_misses 0 # Number of cache demand misses
system.tcp_cntrl7.L1cache.demand_accesses 0 # Number of cache demand accesses
system.tcp_cntrl7.L1cache.num_tag_array_reads 263 # number of tag array reads
system.tcp_cntrl7.L1cache.num_tag_array_writes 256 # number of tag array writes
system.tcp_cntrl7.L1cache.num_tag_array_stalls 11 # number of stalls caused by tag array
+system.tcp_cntrl7.coalescer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
system.tcp_cntrl7.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP
system.tcp_cntrl7.coalescer.gpu_tcp_ld_transfers 10 # TCP to TCP load transfers
system.tcp_cntrl7.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC
system.tcp_cntrl7.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers
system.tcp_cntrl7.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC
system.tcp_cntrl7.coalescer.cp_st_misses 0 # stores that miss in the GPU
+system.tcp_cntrl7.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
+system.tcp_cntrl7.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
system.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits
system.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses
system.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses
system.sqc_cntrl0.L1cache.num_data_array_writes 12 # number of data array writes
system.sqc_cntrl0.L1cache.num_tag_array_reads 22 # number of tag array reads
system.sqc_cntrl0.L1cache.num_tag_array_writes 22 # number of tag array writes
+system.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
+system.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
system.sqc_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits
system.sqc_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses
system.sqc_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses
system.sqc_cntrl1.L1cache.num_data_array_writes 15 # number of data array writes
system.sqc_cntrl1.L1cache.num_tag_array_reads 29 # number of tag array reads
system.sqc_cntrl1.L1cache.num_tag_array_writes 29 # number of tag array writes
+system.sqc_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
+system.sqc_cntrl1.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
system.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits
system.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses
system.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses
+system.tcc_cntrl0.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
system.tccdir_cntrl0.directory.demand_hits 0 # Number of cache demand hits
system.tccdir_cntrl0.directory.demand_misses 0 # Number of cache demand misses
system.tccdir_cntrl0.directory.demand_accesses 0 # Number of cache demand accesses
system.tccdir_cntrl0.directory.num_tag_array_reads 917 # number of tag array reads
system.tccdir_cntrl0.directory.num_tag_array_writes 902 # number of tag array writes
+system.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Control 1430
system.ruby.network.msg_count.Request_Control 1616
system.ruby.network.msg_count.Response_Data 2430
system.ruby.network.msg_byte.Writeback_Data 9504
system.ruby.network.msg_byte.Writeback_Control 1120
system.ruby.network.msg_byte.Unblock_Control 11496
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states
system.ruby.network.ext_links00.int_node.throttle0.link_utilization 0.250555
system.ruby.network.ext_links00.int_node.throttle0.msg_count.Request_Control::0 385
system.ruby.network.ext_links00.int_node.throttle0.msg_count.Response_Data::2 85
sim_ticks 43191 # Number of ticks simulated
final_tick 43191 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 667875 # Simulator tick rate (ticks/s)
-host_mem_usage 406088 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_tick_rate 648785 # Simulator tick rate (ticks/s)
+host_mem_usage 451080 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 57728 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 57728 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 51904 # Number of bytes written to this memory
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states
system.ruby.clk_domain.clock 1 # Clock period in ticks
+system.ruby.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states
system.ruby.delayHist::bucket_size 4 # delay histogram for all message
system.ruby.delayHist::max_bucket 39 # delay histogram for all message
system.ruby.delayHist::samples 6720 # delay histogram for all message
system.ruby.miss_latency_hist_seqr::stdev 227.503250
system.ruby.miss_latency_hist_seqr | 65 6.94% 6.94% | 24 2.56% 9.51% | 5 0.53% 10.04% | 4 0.43% 10.47% | 32 3.42% 13.89% | 302 32.26% 46.15% | 418 44.66% 90.81% | 49 5.24% 96.05% | 28 2.99% 99.04% | 9 0.96% 100.00%
system.ruby.miss_latency_hist_seqr::total 936
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.L1Dcache.demand_hits 89 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 875 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 964 # Number of cache demand accesses
system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 4 # Number of times a store aliased with a pending load
system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 80 # Number of times a store aliased with a pending store
system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 6 # Number of times a load aliased with a pending store
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states
system.ruby.l2_cntrl0.L2cache.demand_hits 34 # Number of cache demand hits
system.ruby.l2_cntrl0.L2cache.demand_misses 904 # Number of cache demand misses
system.ruby.l2_cntrl0.L2cache.demand_accesses 938 # Number of cache demand accesses
+system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.percent_links_utilized 11.804543
system.ruby.network.routers0.msg_count.Control::0 939
system.ruby.network.routers0.msg_count.Request_Control::2 278
system.ruby.network.routers0.msg_bytes.Writeback_Data::0 56520
system.ruby.network.routers0.msg_bytes.Writeback_Data::1 15336
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 200
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states
system.ruby.network.routers1.percent_links_utilized 21.822255
system.ruby.network.routers1.msg_count.Control::0 1842
system.ruby.network.routers1.msg_count.Request_Control::2 279
system.ruby.network.routers1.msg_bytes.Writeback_Data::0 56520
system.ruby.network.routers1.msg_bytes.Writeback_Data::1 15336
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 200
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states
system.ruby.network.routers2.percent_links_utilized 10.015976
system.ruby.network.routers2.msg_count.Control::0 902
system.ruby.network.routers2.msg_count.Response_Data::1 1713
system.ruby.network.routers2.msg_bytes.Control::0 7216
system.ruby.network.routers2.msg_bytes.Response_Data::1 123336
system.ruby.network.routers2.msg_bytes.Response_Control::1 7880
+system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states
system.ruby.network.routers3.percent_links_utilized 14.547012
system.ruby.network.routers3.msg_count.Control::0 1841
system.ruby.network.routers3.msg_count.Request_Control::2 278
system.ruby.network.routers3.msg_bytes.Writeback_Data::0 56520
system.ruby.network.routers3.msg_bytes.Writeback_Data::1 15336
system.ruby.network.routers3.msg_bytes.Writeback_Control::0 200
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Control 5524
system.ruby.network.msg_count.Request_Control 835
system.ruby.network.msg_count.Response_Data 7947
system.ruby.network.msg_byte.Response_Control 65552
system.ruby.network.msg_byte.Writeback_Data 215568
system.ruby.network.msg_byte.Writeback_Control 600
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.throttle0.link_utilization 11.009238
system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 278
system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 936
sim_ticks 54211 # Number of ticks simulated
final_tick 54211 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 538772 # Simulator tick rate (ticks/s)
-host_mem_usage 406688 # Number of bytes of host memory used
+host_tick_rate 528623 # Simulator tick rate (ticks/s)
+host_mem_usage 452196 # Number of bytes of host memory used
host_seconds 0.10 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 54016 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 54016 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 48256 # Number of bytes written to this memory
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states
system.ruby.clk_domain.clock 1 # Clock period in ticks
+system.ruby.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states
system.ruby.outstanding_req_hist_seqr::bucket_size 2
system.ruby.outstanding_req_hist_seqr::max_bucket 19
system.ruby.outstanding_req_hist_seqr::samples 985
system.ruby.miss_latency_hist_seqr::stdev 251.425992
system.ruby.miss_latency_hist_seqr | 54 6.15% 6.15% | 6 0.68% 6.83% | 4 0.46% 7.29% | 388 44.19% 51.48% | 418 47.61% 99.09% | 8 0.91% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 878
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.L1Dcache.demand_hits 90 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 836 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 926 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_hits 2 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Icache.demand_misses 44 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Icache.demand_accesses 46 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 7 # Number of times a store aliased with a pending load
system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 75 # Number of times a store aliased with a pending store
system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 2 # Number of times a load aliased with a pending store
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states
system.ruby.l2_cntrl0.L2cache.demand_hits 36 # Number of cache demand hits
system.ruby.l2_cntrl0.L2cache.demand_misses 844 # Number of cache demand misses
system.ruby.l2_cntrl0.L2cache.demand_accesses 880 # Number of cache demand accesses
+system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.percent_links_utilized 8.888879
system.ruby.network.routers0.msg_count.Request_Control::0 880
system.ruby.network.routers0.msg_count.Response_Data::2 843
system.ruby.network.routers0.msg_bytes.Writeback_Data::2 62928
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 13992
system.ruby.network.routers0.msg_bytes.Unblock_Control::2 7024
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states
system.ruby.network.routers1.percent_links_utilized 16.994245
system.ruby.network.routers1.msg_count.Request_Control::0 880
system.ruby.network.routers1.msg_count.Request_Control::1 844
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 13992
system.ruby.network.routers1.msg_bytes.Writeback_Control::1 12072
system.ruby.network.routers1.msg_bytes.Unblock_Control::2 13760
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states
system.ruby.network.routers2.percent_links_utilized 8.101677
system.ruby.network.routers2.msg_count.Request_Control::1 844
system.ruby.network.routers2.msg_count.Response_Data::2 843
system.ruby.network.routers2.msg_bytes.Writeback_Data::2 54288
system.ruby.network.routers2.msg_bytes.Writeback_Control::1 12072
system.ruby.network.routers2.msg_bytes.Unblock_Control::2 6736
+system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states
system.ruby.network.routers3.percent_links_utilized 11.328267
system.ruby.network.routers3.msg_count.Request_Control::0 880
system.ruby.network.routers3.msg_count.Request_Control::1 844
system.ruby.network.routers3.msg_bytes.Writeback_Control::0 13992
system.ruby.network.routers3.msg_bytes.Writeback_Control::1 12072
system.ruby.network.routers3.msg_bytes.Unblock_Control::2 13760
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Request_Control 5172
system.ruby.network.msg_count.Response_Data 5058
system.ruby.network.msg_count.ResponseL2hit_Data 107
system.ruby.network.msg_byte.Writeback_Data 351648
system.ruby.network.msg_byte.Writeback_Control 78192
system.ruby.network.msg_byte.Unblock_Control 41280
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.throttle0.link_utilization 8.094298
system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 843
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 35
sim_ticks 50141 # Number of ticks simulated
final_tick 50141 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 969830 # Simulator tick rate (ticks/s)
-host_mem_usage 406616 # Number of bytes of host memory used
+host_tick_rate 922495 # Simulator tick rate (ticks/s)
+host_mem_usage 453168 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 50624 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 50624 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 46016 # Number of bytes written to this memory
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states
system.ruby.clk_domain.clock 1 # Clock period in ticks
+system.ruby.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states
system.ruby.outstanding_req_hist_seqr::bucket_size 2
system.ruby.outstanding_req_hist_seqr::max_bucket 19
system.ruby.outstanding_req_hist_seqr::samples 961
system.ruby.miss_latency_hist_seqr | 76 9.62% 9.62% | 7 0.89% 10.51% | 5 0.63% 11.14% | 245 31.01% 42.15% | 403 51.01% 93.16% | 54 6.84% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 790
system.ruby.Directory.incomplete_times_seqr 790
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.L1Dcache.demand_hits 105 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 788 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 893 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_hits 1 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Icache.demand_misses 54 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Icache.demand_accesses 55 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 6 # Number of times a store aliased with a pending load
system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 74 # Number of times a store aliased with a pending store
system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 6 # Number of times a load aliased with a pending store
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states
system.ruby.l2_cntrl0.L2cache.demand_hits 48 # Number of cache demand hits
system.ruby.l2_cntrl0.L2cache.demand_misses 793 # Number of cache demand misses
system.ruby.l2_cntrl0.L2cache.demand_accesses 841 # Number of cache demand accesses
+system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.percent_links_utilized 8.090684
system.ruby.network.routers0.msg_count.Request_Control::1 841
system.ruby.network.routers0.msg_count.Response_Data::4 790
system.ruby.network.routers0.msg_bytes.Response_Control::4 8
system.ruby.network.routers0.msg_bytes.Writeback_Data::4 62064
system.ruby.network.routers0.msg_bytes.Persistent_Control::3 544
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states
system.ruby.network.routers1.percent_links_utilized 8.057777
system.ruby.network.routers1.msg_count.Request_Control::1 841
system.ruby.network.routers1.msg_count.Request_Control::2 793
system.ruby.network.routers1.msg_bytes.Writeback_Data::4 111816
system.ruby.network.routers1.msg_bytes.Writeback_Control::4 520
system.ruby.network.routers1.msg_bytes.Persistent_Control::3 272
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states
system.ruby.network.routers2.percent_links_utilized 7.216150
system.ruby.network.routers2.msg_count.Request_Control::2 793
system.ruby.network.routers2.msg_count.Response_Data::4 790
system.ruby.network.routers2.msg_bytes.Writeback_Data::4 51768
system.ruby.network.routers2.msg_bytes.Writeback_Control::4 520
system.ruby.network.routers2.msg_bytes.Persistent_Control::3 272
+system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states
system.ruby.network.routers3.percent_links_utilized 7.788370
system.ruby.network.routers3.msg_count.Request_Control::1 841
system.ruby.network.routers3.msg_count.Request_Control::2 793
system.ruby.network.routers3.msg_bytes.Writeback_Data::4 112824
system.ruby.network.routers3.msg_bytes.Writeback_Control::4 520
system.ruby.network.routers3.msg_bytes.Persistent_Control::3 544
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Request_Control 4902
system.ruby.network.msg_count.Response_Data 2370
system.ruby.network.msg_count.ResponseL2hit_Data 150
system.ruby.network.msg_byte.Writeback_Data 338472
system.ruby.network.msg_byte.Writeback_Control 1560
system.ruby.network.msg_byte.Persistent_Control 1632
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.throttle0.link_utilization 7.698291
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 790
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 50
sim_ticks 29561 # Number of ticks simulated
final_tick 29561 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 593739 # Simulator tick rate (ticks/s)
-host_mem_usage 406316 # Number of bytes of host memory used
+host_tick_rate 585115 # Simulator tick rate (ticks/s)
+host_mem_usage 452068 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 56000 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 56000 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 50560 # Number of bytes written to this memory
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states
system.ruby.clk_domain.clock 1 # Clock period in ticks
+system.ruby.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states
system.ruby.outstanding_req_hist_seqr::bucket_size 2
system.ruby.outstanding_req_hist_seqr::max_bucket 19
system.ruby.outstanding_req_hist_seqr::samples 1027
system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits
system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses
system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.L1Dcache.demand_hits 96 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 859 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 955 # Number of cache demand accesses
system.ruby.l1_cntrl0.L2cache.demand_hits 39 # Number of cache demand hits
system.ruby.l1_cntrl0.L2cache.demand_misses 874 # Number of cache demand misses
system.ruby.l1_cntrl0.L2cache.demand_accesses 913 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 8 # Number of times a store aliased with a pending load
system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 72 # Number of times a store aliased with a pending store
system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 4 # Number of times a load aliased with a pending store
system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 3 # Number of times a load aliased with a pending load
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.percent_links_utilized 15.685362
system.ruby.network.routers0.msg_count.Request_Control::2 876
system.ruby.network.routers0.msg_count.Response_Data::4 874
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 6952
system.ruby.network.routers0.msg_bytes.Writeback_Control::5 616
system.ruby.network.routers0.msg_bytes.Unblock_Control::5 6968
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states
system.ruby.network.routers1.percent_links_utilized 15.679443
system.ruby.network.routers1.msg_count.Request_Control::2 876
system.ruby.network.routers1.msg_count.Response_Data::4 874
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 6952
system.ruby.network.routers1.msg_bytes.Writeback_Control::5 616
system.ruby.network.routers1.msg_bytes.Unblock_Control::5 6968
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states
system.ruby.network.routers2.percent_links_utilized 15.682825
system.ruby.network.routers2.msg_count.Request_Control::2 876
system.ruby.network.routers2.msg_count.Response_Data::4 874
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 6952
system.ruby.network.routers2.msg_bytes.Writeback_Control::5 616
system.ruby.network.routers2.msg_bytes.Unblock_Control::5 6968
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Request_Control 2628
system.ruby.network.msg_count.Response_Data 2622
system.ruby.network.msg_count.Writeback_Data 2373
system.ruby.network.msg_byte.Writeback_Data 170856
system.ruby.network.msg_byte.Writeback_Control 43560
system.ruby.network.msg_byte.Unblock_Control 20904
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.throttle0.link_utilization 14.774534
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 874
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 869
sim_ticks 37741 # Number of ticks simulated
final_tick 37741 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 877206 # Simulator tick rate (ticks/s)
-host_mem_usage 404076 # Number of bytes of host memory used
+host_tick_rate 891959 # Simulator tick rate (ticks/s)
+host_mem_usage 449872 # Number of bytes of host memory used
host_seconds 0.04 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 60992 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 60992 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 60800 # Number of bytes written to this memory
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states
system.ruby.clk_domain.clock 1 # Clock period in ticks
+system.ruby.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
system.ruby.delayHist::samples 1903 # delay histogram for all message
system.ruby.miss_latency_hist_seqr | 2 0.21% 0.21% | 9 0.94% 1.15% | 5 0.52% 1.68% | 89 9.34% 11.02% | 639 67.05% 78.07% | 153 16.05% 94.12% | 49 5.14% 99.27% | 7 0.73% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 953
system.ruby.Directory.incomplete_times_seqr 953
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.cacheMemory.demand_hits 39 # Number of cache demand hits
system.ruby.l1_cntrl0.cacheMemory.demand_misses 955 # Number of cache demand misses
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 994 # Number of cache demand accesses
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 7 # Number of times a store aliased with a pending load
system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 129 # Number of times a store aliased with a pending store
system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 6 # Number of times a load aliased with a pending store
system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 1 # Number of times a load aliased with a pending load
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.percent_links_utilized 12.606979
system.ruby.network.routers0.msg_count.Control::2 953
system.ruby.network.routers0.msg_count.Data::2 951
system.ruby.network.routers0.msg_bytes.Data::2 68472
system.ruby.network.routers0.msg_bytes.Response_Data::4 68616
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 7600
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states
system.ruby.network.routers1.percent_links_utilized 12.605654
system.ruby.network.routers1.msg_count.Control::2 953
system.ruby.network.routers1.msg_count.Data::2 950
system.ruby.network.routers1.msg_bytes.Data::2 68400
system.ruby.network.routers1.msg_bytes.Response_Data::4 68616
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 7600
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states
system.ruby.network.routers2.percent_links_utilized 12.605654
system.ruby.network.routers2.msg_count.Control::2 953
system.ruby.network.routers2.msg_count.Data::2 950
system.ruby.network.routers2.msg_bytes.Data::2 68400
system.ruby.network.routers2.msg_bytes.Response_Data::4 68616
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 7600
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Control 2859
system.ruby.network.msg_count.Data 2851
system.ruby.network.msg_count.Response_Data 2859
system.ruby.network.msg_byte.Data 205272
system.ruby.network.msg_byte.Response_Data 205848
system.ruby.network.msg_byte.Writeback_Control 22800
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.throttle0.link_utilization 12.621552
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 953
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 950
sim_ticks 100000000000 # Number of ticks simulated
final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 9064709748 # Simulator tick rate (ticks/s)
-host_mem_usage 219696 # Number of bytes of host memory used
-host_seconds 11.03 # Real time elapsed on the host
+host_tick_rate 10668065661 # Simulator tick rate (ticks/s)
+host_mem_usage 263968 # Number of bytes of host memory used
+host_seconds 9.37 # Real time elapsed on the host
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 100000000000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu 106649408 # Number of bytes read from this memory
system.physmem.bytes_read::total 106649408 # Number of bytes read from this memory
system.physmem.bytes_written::cpu 106680256 # Number of bytes written to this memory
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 96120321460 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 100000000000 # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::UNDEFINED 100000000000 # Cumulative time (in ticks) in various power states
system.cpu.numPackets 3333276 # Number of packets generated
system.cpu.numRetries 0 # Number of retries
system.cpu.retryTicks 0 # Time spent waiting due to back-pressure (ticks)
+system.membus.pwrStateResidencyTicks::UNDEFINED 100000000000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 1666397 # Transaction distribution
system.membus.trans_dist::ReadResp 1666397 # Transaction distribution
system.membus.trans_dist::WriteReq 1666879 # Transaction distribution
system.membus.reqLayer0.utilization 11.7 # Layer utilization (%)
system.membus.respLayer0.occupancy 11025969759 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 11.0 # Layer utilization (%)
+system.monitor.pwrStateResidencyTicks::UNDEFINED 100000000000 # Cumulative time (in ticks) in various power states
system.monitor.readBurstLengthHist::samples 1666397 # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets
sim_ticks 100000000000 # Number of ticks simulated
final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 16220790107 # Simulator tick rate (ticks/s)
-host_mem_usage 221740 # Number of bytes of host memory used
-host_seconds 6.17 # Real time elapsed on the host
+host_tick_rate 18414287723 # Simulator tick rate (ticks/s)
+host_mem_usage 264992 # Number of bytes of host memory used
+host_seconds 5.43 # Real time elapsed on the host
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 100000000000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu 64 # Number of bytes read from this memory
system.physmem.bytes_read::total 64 # Number of bytes read from this memory
system.physmem.bytes_written::cpu 853312 # Number of bytes written to this memory
system.physmem.bw_write::total 8533120 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu 8533760 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 8533760 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 100000000000 # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::UNDEFINED 100000000000 # Cumulative time (in ticks) in various power states
system.cpu.numPackets 13334 # Number of packets generated
system.cpu.numRetries 1 # Number of retries
system.cpu.retryTicks 1672 # Time spent waiting due to back-pressure (ticks)
+system.membus.pwrStateResidencyTicks::UNDEFINED 100000000000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 1 # Transaction distribution
system.membus.trans_dist::ReadResp 1 # Transaction distribution
system.membus.trans_dist::WriteReq 13333 # Transaction distribution
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.respLayer0.occupancy 13338000 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.monitor.pwrStateResidencyTicks::UNDEFINED 100000000000 # Cumulative time (in ticks) in various power states
system.monitor.readBurstLengthHist::samples 1 # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets
sim_ticks 45951567500 # Number of ticks simulated
final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1593313 # Simulator instruction rate (inst/s)
-host_op_rate 1593310 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 796655733 # Simulator tick rate (ticks/s)
-host_mem_usage 242160 # Number of bytes of host memory used
-host_seconds 57.68 # Real time elapsed on the host
+host_inst_rate 3168591 # Simulator instruction rate (inst/s)
+host_op_rate 3168590 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1584296087 # Simulator tick rate (ticks/s)
+host_mem_usage 288936 # Number of bytes of host memory used
+host_seconds 29.00 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 45951567500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 367612356 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 108337521 # Number of bytes read from this memory
system.physmem.bytes_read::total 475949877 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7999995996 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3030549393 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11030545389 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 45951567500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 45951567500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 91903136 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 91903089 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 45951567500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 111899287 # Transaction distribution
system.membus.trans_dist::ReadResp 111899287 # Transaction distribution
system.membus.trans_dist::WriteReq 6501103 # Transaction distribution
sim_ticks 118762761500 # Number of ticks simulated
final_tick 118762761500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 940295 # Simulator instruction rate (inst/s)
-host_op_rate 940295 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1215106876 # Simulator tick rate (ticks/s)
-host_mem_usage 251128 # Number of bytes of host memory used
-host_seconds 97.74 # Real time elapsed on the host
+host_inst_rate 1861883 # Simulator instruction rate (inst/s)
+host_op_rate 1861883 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2406038400 # Simulator tick rate (ticks/s)
+host_mem_usage 298932 # Number of bytes of host memory used
+host_seconds 49.36 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 137216 # Number of bytes read from this memory
system.physmem.bytes_read::total 304960 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 1412429 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1155379 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2567808 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 118762761500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 237525523 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 91903089 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 157 # number of replacements
system.cpu.dcache.tags.tagsinuse 1441.946319 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 59260.683761 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59260.683761 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 59260.683761 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 6681 # number of replacements
system.cpu.icache.tags.tagsinuse 1417.953327 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 183814690 # Number of tag accesses
system.cpu.icache.tags.data_accesses 183814690 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 27101.645123 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27101.645123 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 27101.645123 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 2073.923151 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 12687 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.094879 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 145425 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 145425 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 6681 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 6681 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3334500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 3043 # Transaction distribution
system.membus.trans_dist::ReadExReq 1722 # Transaction distribution
system.membus.trans_dist::ReadExResp 1722 # Transaction distribution
sim_ticks 99596491500 # Number of ticks simulated
final_tick 99596491500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2176341 # Simulator instruction rate (inst/s)
-host_op_rate 2294214 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1257887009 # Simulator tick rate (ticks/s)
-host_mem_usage 304976 # Number of bytes of host memory used
-host_seconds 79.18 # Real time elapsed on the host
+host_inst_rate 2111044 # Simulator instruction rate (inst/s)
+host_op_rate 2225381 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1220146763 # Simulator tick rate (ticks/s)
+host_mem_usage 306656 # Number of bytes of host memory used
+host_seconds 81.63 # Real time elapsed on the host
sim_insts 172317410 # Number of instructions simulated
sim_ops 181650342 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 759440208 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 110533661 # Number of bytes read from this memory
system.physmem.bytes_read::total 869973869 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7625170290 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1564177600 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9189347890 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 400 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 99596491500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 199192984 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 181650743 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 217614903 # Transaction distribution
system.membus.trans_dist::ReadResp 217637310 # Transaction distribution
system.membus.trans_dist::WriteReq 12364287 # Transaction distribution
sim_ticks 230197694500 # Number of ticks simulated
final_tick 230197694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1495549 # Simulator instruction rate (inst/s)
-host_op_rate 1576687 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2003415873 # Simulator tick rate (ticks/s)
-host_mem_usage 314964 # Number of bytes of host memory used
-host_seconds 114.90 # Real time elapsed on the host
+host_inst_rate 1499491 # Simulator instruction rate (inst/s)
+host_op_rate 1580842 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2008696236 # Simulator tick rate (ticks/s)
+host_mem_usage 315632 # Number of bytes of host memory used
+host_seconds 114.60 # Real time elapsed on the host
sim_insts 171842484 # Number of instructions simulated
sim_ops 181165371 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 110336 # Number of bytes read from this memory
system.physmem.bytes_read::total 220992 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 480700 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 479310 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 960010 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 400 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 230197694500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 460395389 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 181650743 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 40 # number of replacements
system.cpu.dcache.tags.tagsinuse 1363.571253 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.427002 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 80330619 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 80330619 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 27754163 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 27754163 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 59278.803132 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59279.765232 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 59279.765232 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 1506 # number of replacements
system.cpu.icache.tags.tagsinuse 1147.958164 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 189857002 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.754395 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 379723157 # Number of tag accesses
system.cpu.icache.tags.data_accesses 379723157 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 189857002 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 189857002 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 189857002 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 1675.610098 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2846 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.072296 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 54045 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 54045 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1448 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 1506 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 2683500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 2361 # Transaction distribution
system.membus.trans_dist::ReadExReq 1092 # Transaction distribution
system.membus.trans_dist::ReadExResp 1092 # Transaction distribution
sim_ticks 96722945000 # Number of ticks simulated
final_tick 96722945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1393535 # Simulator instruction rate (inst/s)
-host_op_rate 1393537 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 696772335 # Simulator tick rate (ticks/s)
-host_mem_usage 242012 # Number of bytes of host memory used
-host_seconds 138.82 # Real time elapsed on the host
+host_inst_rate 2890225 # Simulator instruction rate (inst/s)
+host_op_rate 2890229 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1445122551 # Simulator tick rate (ticks/s)
+host_mem_usage 288744 # Number of bytes of host memory used
+host_seconds 66.93 # Real time elapsed on the host
sim_insts 193444518 # Number of instructions simulated
sim_ops 193444756 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 96722945000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 773782140 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 223463413 # Number of bytes read from this memory
system.physmem.bytes_read::total 997245553 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7999985319 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3055415910 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11055401229 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 96722945000 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 401 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 96722945000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 193445891 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 193445773 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 96722945000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 251180603 # Transaction distribution
system.membus.trans_dist::ReadResp 251180603 # Transaction distribution
system.membus.trans_dist::WriteReq 18976439 # Transaction distribution
sim_ticks 270599529500 # Number of ticks simulated
final_tick 270599529500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 833752 # Simulator instruction rate (inst/s)
-host_op_rate 833752 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1166291607 # Simulator tick rate (ticks/s)
-host_mem_usage 251752 # Number of bytes of host memory used
-host_seconds 232.02 # Real time elapsed on the host
+host_inst_rate 1741327 # Simulator instruction rate (inst/s)
+host_op_rate 1741329 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2435851420 # Simulator tick rate (ticks/s)
+host_mem_usage 298736 # Number of bytes of host memory used
+host_seconds 111.09 # Real time elapsed on the host
sim_insts 193444518 # Number of instructions simulated
sim_ops 193444756 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory
system.physmem.bytes_read::total 331072 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 850733 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 372743 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1223476 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 401 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 270599529500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 541199059 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 193445773 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 2 # number of replacements
system.cpu.dcache.tags.tagsinuse 1237.159344 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 10362 # number of replacements
system.cpu.icache.tags.tagsinuse 1591.528232 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.940430 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 386903360 # Number of tag accesses
system.cpu.icache.tags.data_accesses 386903360 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 2678.246108 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 19053 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.125031 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 198999 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 198999 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 2 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 2 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 10362 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 2 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 10362 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 4095 # Transaction distribution
system.membus.trans_dist::ReadExReq 1078 # Transaction distribution
system.membus.trans_dist::ReadExResp 1078 # Transaction distribution
sim_ticks 131393279000 # Number of ticks simulated
final_tick 131393279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 719836 # Simulator instruction rate (inst/s)
-host_op_rate 1206511 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 716141111 # Simulator tick rate (ticks/s)
-host_mem_usage 284280 # Number of bytes of host memory used
-host_seconds 183.47 # Real time elapsed on the host
+host_inst_rate 1595970 # Simulator instruction rate (inst/s)
+host_op_rate 2674991 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1587777431 # Simulator tick rate (ticks/s)
+host_mem_usage 331680 # Number of bytes of host memory used
+host_seconds 82.75 # Real time elapsed on the host
sim_insts 132071193 # Number of instructions simulated
sim_ops 221363385 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 131393279000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 1387954936 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 310423752 # Number of bytes read from this memory
system.physmem.bytes_read::total 1698378688 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 10563363260 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3122274945 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13685638205 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 131393279000 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 131393279000 # Cumulative time (in ticks) in various power states
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 131393279000 # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 131393279000 # Cumulative time (in ticks) in various power states
system.cpu.workload.num_syscalls 400 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 131393279000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 262786559 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 221363385 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 131393279000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 230176372 # Transaction distribution
system.membus.trans_dist::ReadResp 230176372 # Transaction distribution
system.membus.trans_dist::WriteReq 20515731 # Transaction distribution
sim_ticks 250987138500 # Number of ticks simulated
final_tick 250987138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 489633 # Simulator instruction rate (inst/s)
-host_op_rate 820669 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 930494730 # Simulator tick rate (ticks/s)
-host_mem_usage 293244 # Number of bytes of host memory used
-host_seconds 269.74 # Real time elapsed on the host
+host_inst_rate 1028477 # Simulator instruction rate (inst/s)
+host_op_rate 1723822 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1954510825 # Simulator tick rate (ticks/s)
+host_mem_usage 341680 # Number of bytes of host memory used
+host_seconds 128.41 # Real time elapsed on the host
sim_insts 132071193 # Number of instructions simulated
sim_ops 221363385 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory
system.physmem.bytes_read::total 303040 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 724181 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 483212 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1207393 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
system.cpu.workload.num_syscalls 400 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 250987138500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 501974277 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 221363385 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 41 # number of replacements
system.cpu.dcache.tags.tagsinuse 1363.414730 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks.
system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 154397377 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits
system.cpu.dcache.demand_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 2836 # number of replacements
system.cpu.icache.tags.tagsinuse 1455.245085 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks.
system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 346993428 # Number of tag accesses
system.cpu.icache.tags.data_accesses 346993428 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 173489673 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 173489673 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 173489673 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 2058.105553 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 4732 # Total number of references to valid blocks.
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.096558 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 80550 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 80550 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 7 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 7 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 2836 # number of WritebackClean hits
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 7 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 2836 # Transaction distribution
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 3160 # Transaction distribution
system.membus.trans_dist::ReadExReq 1575 # Transaction distribution
system.membus.trans_dist::ReadExResp 1575 # Transaction distribution
projects / gem5.git / commitdiff