Merge branch 'master' into clifford/ids

diff --cc passes/opt/opt_expr.cc
index 8f6e660a22fae5c82e7518db30058bb5b0e025b9,90bda6bd3d2affd4c073e7059895139fffc37f5b..fcdc1d173892699eb1d2978a61fcbbeae1dc8ec5
--- 1/passes/opt/opt_expr.cc
--- 2/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@@ -641,11 -641,12 +641,12 @@@ void replace_const_cells(RTLIL::Design 
                                }
                        }
  
-                       if (cell->type.in(ID($add), ID($sub))) {
 -                      if (cell->type.in("$add", "$sub"))
++                      if (cell->type.in(ID($add), ID($sub)))
+                       {
 -                              RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
 -                              RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
 -                              RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 -                              bool sub = cell->type == "$sub";
 +                              RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID(A)));
 +                              RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID(B)));
 +                              RTLIL::SigSpec sig_y = cell->getPort(ID(Y));
 +                              bool sub = cell->type == ID($sub);
  
                                int i;
                                for (i = 0; i < GetSize(sig_y); i++) {
@@@ -665,15 -666,62 +666,62 @@@
                                        did_something = true;
                                }
                        }
+ 
+                       if (cell->type == "$alu")
+                       {
+                               RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
+                               RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
+                               RTLIL::SigBit sig_ci = assign_map(cell->getPort("\\CI"));
+                               RTLIL::SigBit sig_bi = assign_map(cell->getPort("\\BI"));
+                               RTLIL::SigSpec sig_x = cell->getPort("\\X");
+                               RTLIL::SigSpec sig_y = cell->getPort("\\Y");
+                               RTLIL::SigSpec sig_co = cell->getPort("\\CO");
+ 
+                               if (sig_ci.wire || sig_bi.wire)
+                                       goto next_cell;
+ 
+                               bool sub = (sig_ci == State::S1 && sig_bi == State::S1);
+ 
+                               // If not a subtraction, yet there is a carry or B is inverted
+                               //   then no optimisation is possible as carry will not be constant
+                               if (!sub && (sig_ci != State::S0 || sig_bi != State::S0))
+                                       goto next_cell;
+ 
+                               int i;
+                               for (i = 0; i < GetSize(sig_y); i++) {
+                                       if (sig_b.at(i, State::Sx) == State::S0 && sig_a.at(i, State::Sx) != State::Sx) {
+                                               module->connect(sig_x[i], sub ? module->Not(NEW_ID, sig_a[i]).as_bit() : sig_a[i]);
+                                               module->connect(sig_y[i], sig_a[i]);
+                                               module->connect(sig_co[i], sub ? State::S1 : State::S0);
+                                       }
+                                       else if (!sub && sig_a.at(i, State::Sx) == State::S0 && sig_b.at(i, State::Sx) != State::Sx) {
+                                               module->connect(sig_x[i], sig_b[i]);
+                                               module->connect(sig_y[i], sig_b[i]);
+                                               module->connect(sig_co[i], State::S0);
+                                       }
+                                       else
+                                               break;
+                               }
+                               if (i > 0) {
+                                       cover("opt.opt_expr.fine.$alu");
+                                       cell->setPort("\\A", sig_a.extract_end(i));
+                                       cell->setPort("\\B", sig_b.extract_end(i));
+                                       cell->setPort("\\X", sig_x.extract_end(i));
+                                       cell->setPort("\\Y", sig_y.extract_end(i));
+                                       cell->setPort("\\CO", sig_co.extract_end(i));
+                                       cell->fixup_parameters();
+                                       did_something = true;
+                               }
+                       }
                }
  
 -              if (cell->type.in("$reduce_xor", "$reduce_xnor", "$shift", "$shiftx", "$shl", "$shr", "$sshl", "$sshr",
 -                                      "$lt", "$le", "$ge", "$gt", "$neg", "$add", "$sub", "$mul", "$div", "$mod", "$pow"))
 +              if (cell->type.in(ID($reduce_xor), ID($reduce_xnor), ID($shift), ID($shiftx), ID($shl), ID($shr), ID($sshl), ID($sshr),
 +                                      ID($lt), ID($le), ID($ge), ID($gt), ID($neg), ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow)))
                {
 -                      RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
 -                      RTLIL::SigSpec sig_b = cell->hasPort("\\B") ? assign_map(cell->getPort("\\B")) : RTLIL::SigSpec();
 +                      RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID(A)));
 +                      RTLIL::SigSpec sig_b = cell->hasPort(ID(B)) ? assign_map(cell->getPort(ID(B))) : RTLIL::SigSpec();
  
 -                      if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx"))
 +                      if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)))
                                sig_a = RTLIL::SigSpec();
  
                        for (auto &bit : sig_a.to_sigbit_vector())