back.verilog: detect undriven public wires using Yosys.

This should never happen, and is certainly a logic bug in nMigen.

diff --git a/nmigen/back/verilog.py b/nmigen/back/verilog.py
index 90a5c2f61ab39de42a42b00cb8289bb0578bbb69..8ac5f1fff49195f9fab88964b953a7c89f4a5d38 100644 (file)
--- a/nmigen/back/verilog.py
+++ b/nmigen/back/verilog.py
@@ -19,6 +19,7 @@ def convert(*args, **kwargs):
         stderr=subprocess.PIPE,
         encoding="utf-8")
     verilog_text, error = popen.communicate("""
+# Convert nMigen's RTLIL to readable Verilog.
 read_ilang <<rtlil
 {}
 rtlil
@@ -27,6 +28,9 @@ proc_arst
 proc_dff
 proc_clean
 write_verilog
+# Make sure there are no undriven wires in generated RTLIL.
+proc
+select -assert-none w:* i:* %a %d c:* %co* %a %d n:$* %d
 """.format(il_text))
     if popen.returncode:
         raise YosysError(error.strip())