Best implemented on top of a Multi-Issue Out-of-Order Micro-architecture,
REMAP Schedules are 100% Deterministic **including Indexing** and are
designed to be incorporated in between the Decode and Issue phases,
-directly into Register Hazard Management.
+directly into Register Hazard Management
+
+As long as the SVSHAPE SPRs
+are not written to directly, Hardware may treat REMAP as 100%
+Deterministic: all REMAP Management instructions take static
+operands with the exception of Indexed Mode, and even then
+Architectural State is permitted to assume that the Indices
+are cacheable from the point at which the `svindex` instruction
+is executed.
Parallel Reduction is unusual in that it requires a full vector array
of results (not a scalar) and uses the rest of the result Vector for