/** List of glsl_to_tgsi_instruction */
exec_list instructions;
- glsl_to_tgsi_instruction *emit(ir_instruction *ir, unsigned op);
+ glsl_to_tgsi_instruction *emit_asm(ir_instruction *ir, unsigned op);
- glsl_to_tgsi_instruction *emit(ir_instruction *ir, unsigned op,
- st_dst_reg dst, st_src_reg src0);
+ glsl_to_tgsi_instruction *emit_asm(ir_instruction *ir, unsigned op,
+ st_dst_reg dst, st_src_reg src0);
- glsl_to_tgsi_instruction *emit(ir_instruction *ir, unsigned op,
- st_dst_reg dst, st_dst_reg dst1,
- st_src_reg src0);
+ glsl_to_tgsi_instruction *emit_asm(ir_instruction *ir, unsigned op,
+ st_dst_reg dst, st_dst_reg dst1,
+ st_src_reg src0);
- glsl_to_tgsi_instruction *emit(ir_instruction *ir, unsigned op,
- st_dst_reg dst, st_src_reg src0, st_src_reg src1);
+ glsl_to_tgsi_instruction *emit_asm(ir_instruction *ir, unsigned op,
+ st_dst_reg dst, st_src_reg src0, st_src_reg src1);
- glsl_to_tgsi_instruction *emit(ir_instruction *ir, unsigned op,
- st_dst_reg dst,
- st_src_reg src0, st_src_reg src1, st_src_reg src2);
+ glsl_to_tgsi_instruction *emit_asm(ir_instruction *ir, unsigned op,
+ st_dst_reg dst,
+ st_src_reg src0, st_src_reg src1, st_src_reg src2);
- glsl_to_tgsi_instruction *emit(ir_instruction *ir, unsigned op,
- st_dst_reg dst,
- st_src_reg src0, st_src_reg src1,
- st_src_reg src2, st_src_reg src3);
+ glsl_to_tgsi_instruction *emit_asm(ir_instruction *ir, unsigned op,
+ st_dst_reg dst,
+ st_src_reg src0, st_src_reg src1,
+ st_src_reg src2, st_src_reg src3);
- glsl_to_tgsi_instruction *emit(ir_instruction *ir, unsigned op,
- st_dst_reg dst, st_dst_reg dst1,
- st_src_reg src0, st_src_reg src1,
- st_src_reg src2, st_src_reg src3);
+ glsl_to_tgsi_instruction *emit_asm(ir_instruction *ir, unsigned op,
+ st_dst_reg dst, st_dst_reg dst1,
+ st_src_reg src0, st_src_reg src1,
+ st_src_reg src2, st_src_reg src3);
unsigned get_opcode(ir_instruction *ir, unsigned op,
st_dst_reg dst,
}
glsl_to_tgsi_instruction *
-glsl_to_tgsi_visitor::emit(ir_instruction *ir, unsigned op,
- st_dst_reg dst, st_dst_reg dst1,
- st_src_reg src0, st_src_reg src1,
- st_src_reg src2, st_src_reg src3)
+glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, unsigned op,
+ st_dst_reg dst, st_dst_reg dst1,
+ st_src_reg src0, st_src_reg src1,
+ st_src_reg src2, st_src_reg src3)
{
glsl_to_tgsi_instruction *inst = new(mem_ctx) glsl_to_tgsi_instruction();
int num_reladdr = 0, i, j;
}
glsl_to_tgsi_instruction *
-glsl_to_tgsi_visitor::emit(ir_instruction *ir, unsigned op,
- st_dst_reg dst,
- st_src_reg src0, st_src_reg src1,
- st_src_reg src2, st_src_reg src3)
+glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, unsigned op,
+ st_dst_reg dst,
+ st_src_reg src0, st_src_reg src1,
+ st_src_reg src2, st_src_reg src3)
{
- return emit(ir, op, dst, undef_dst, src0, src1, src2, src3);
+ return emit_asm(ir, op, dst, undef_dst, src0, src1, src2, src3);
}
glsl_to_tgsi_instruction *
-glsl_to_tgsi_visitor::emit(ir_instruction *ir, unsigned op,
- st_dst_reg dst, st_src_reg src0,
- st_src_reg src1, st_src_reg src2)
+glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, unsigned op,
+ st_dst_reg dst, st_src_reg src0,
+ st_src_reg src1, st_src_reg src2)
{
- return emit(ir, op, dst, undef_dst, src0, src1, src2, undef_src);
+ return emit_asm(ir, op, dst, undef_dst, src0, src1, src2, undef_src);
}
glsl_to_tgsi_instruction *
-glsl_to_tgsi_visitor::emit(ir_instruction *ir, unsigned op,
- st_dst_reg dst, st_src_reg src0, st_src_reg src1)
+glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, unsigned op,
+ st_dst_reg dst, st_src_reg src0, st_src_reg src1)
{
- return emit(ir, op, dst, undef_dst, src0, src1, undef_src, undef_src);
+ return emit_asm(ir, op, dst, undef_dst, src0, src1, undef_src, undef_src);
}
glsl_to_tgsi_instruction *
-glsl_to_tgsi_visitor::emit(ir_instruction *ir, unsigned op,
- st_dst_reg dst, st_src_reg src0)
+glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, unsigned op,
+ st_dst_reg dst, st_src_reg src0)
{
assert(dst.writemask != 0);
- return emit(ir, op, dst, undef_dst, src0, undef_src, undef_src, undef_src);
+ return emit_asm(ir, op, dst, undef_dst, src0, undef_src, undef_src, undef_src);
}
glsl_to_tgsi_instruction *
-glsl_to_tgsi_visitor::emit(ir_instruction *ir, unsigned op,
- st_dst_reg dst, st_dst_reg dst1, st_src_reg src0)
+glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, unsigned op,
+ st_dst_reg dst, st_dst_reg dst1, st_src_reg src0)
{
- return emit(ir, op, dst, dst1, src0, undef_src, undef_src, undef_src);
+ return emit_asm(ir, op, dst, dst1, src0, undef_src, undef_src, undef_src);
}
glsl_to_tgsi_instruction *
-glsl_to_tgsi_visitor::emit(ir_instruction *ir, unsigned op)
+glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, unsigned op)
{
- return emit(ir, op, undef_dst, undef_dst, undef_src, undef_src, undef_src, undef_src);
+ return emit_asm(ir, op, undef_dst, undef_dst, undef_src, undef_src, undef_src, undef_src);
}
/**
TGSI_OPCODE_DP2, TGSI_OPCODE_DP3, TGSI_OPCODE_DP4
};
- return emit(ir, dot_opcodes[elements - 2], dst, src0, src1);
+ return emit_asm(ir, dot_opcodes[elements - 2], dst, src0, src1);
}
/**
src1_swiz, src1_swiz);
dst.writemask = this_mask;
- emit(ir, op, dst, src0, src1);
+ emit_asm(ir, op, dst, src0, src1);
done_mask |= this_mask;
}
}
if (dst.index >= this->num_address_regs)
this->num_address_regs = dst.index + 1;
- emit(NULL, op, dst, src0);
+ emit_asm(NULL, op, dst, src0);
}
int
*/
st_src_reg src(PROGRAM_STATE_VAR, index, GLSL_TYPE_FLOAT);
src.swizzle = slots[i].swizzle;
- emit(ir, TGSI_OPCODE_MOV, dst, src);
+ emit_asm(ir, TGSI_OPCODE_MOV, dst, src);
/* even a float takes up a whole vec4 reg in a struct/array. */
dst.index++;
}
void
glsl_to_tgsi_visitor::visit(ir_loop *ir)
{
- emit(NULL, TGSI_OPCODE_BGNLOOP);
+ emit_asm(NULL, TGSI_OPCODE_BGNLOOP);
visit_exec_list(&ir->body_instructions, this);
- emit(NULL, TGSI_OPCODE_ENDLOOP);
+ emit_asm(NULL, TGSI_OPCODE_ENDLOOP);
}
void
{
switch (ir->mode) {
case ir_loop_jump::jump_break:
- emit(NULL, TGSI_OPCODE_BRK);
+ emit_asm(NULL, TGSI_OPCODE_BRK);
break;
case ir_loop_jump::jump_continue:
- emit(NULL, TGSI_OPCODE_CONT);
+ emit_asm(NULL, TGSI_OPCODE_CONT);
break;
}
}
this->result = get_temp(ir->type);
result_dst = st_dst_reg(this->result);
result_dst.writemask = (1 << ir->type->vector_elements) - 1;
- emit(ir, TGSI_OPCODE_MAD, result_dst, a, b, c);
+ emit_asm(ir, TGSI_OPCODE_MAD, result_dst, a, b, c);
return true;
}
b.negate = ~b.negate;
this->result = get_temp(ir->type);
- emit(ir, TGSI_OPCODE_MAD, st_dst_reg(this->result), a, b, a);
+ emit_asm(ir, TGSI_OPCODE_MAD, st_dst_reg(this->result), a, b, a);
return true;
}
if (*num_reladdr != 1) {
st_src_reg temp = get_temp(glsl_type::vec4_type);
- emit(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), *reg);
+ emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), *reg);
*reg = temp;
}
switch (ir->operation) {
case ir_unop_logic_not:
if (result_dst.type != GLSL_TYPE_FLOAT)
- emit(ir, TGSI_OPCODE_NOT, result_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_NOT, result_dst, op[0]);
else {
/* Previously 'SEQ dst, src, 0.0' was used for this. However, many
* older GPUs implement SEQ using multiple instructions (i915 uses two
* 0.0 and 1.0, 1-x also implements !x.
*/
op[0].negate = ~op[0].negate;
- emit(ir, TGSI_OPCODE_ADD, result_dst, op[0], st_src_reg_for_float(1.0));
+ emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], st_src_reg_for_float(1.0));
}
break;
case ir_unop_neg:
if (result_dst.type == GLSL_TYPE_INT || result_dst.type == GLSL_TYPE_UINT)
- emit(ir, TGSI_OPCODE_INEG, result_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_INEG, result_dst, op[0]);
else if (result_dst.type == GLSL_TYPE_DOUBLE)
- emit(ir, TGSI_OPCODE_DNEG, result_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_DNEG, result_dst, op[0]);
else {
op[0].negate = ~op[0].negate;
result_src = op[0];
}
break;
case ir_unop_abs:
- emit(ir, TGSI_OPCODE_ABS, result_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_ABS, result_dst, op[0]);
break;
case ir_unop_sign:
- emit(ir, TGSI_OPCODE_SSG, result_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_SSG, result_dst, op[0]);
break;
case ir_unop_rcp:
emit_scalar(ir, TGSI_OPCODE_RCP, result_dst, op[0]);
break;
case ir_unop_saturate: {
glsl_to_tgsi_instruction *inst;
- inst = emit(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
+ inst = emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
inst->saturate = true;
break;
}
case ir_unop_dFdx:
case ir_unop_dFdx_coarse:
- emit(ir, TGSI_OPCODE_DDX, result_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_DDX, result_dst, op[0]);
break;
case ir_unop_dFdx_fine:
- emit(ir, TGSI_OPCODE_DDX_FINE, result_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_DDX_FINE, result_dst, op[0]);
break;
case ir_unop_dFdy:
case ir_unop_dFdy_coarse:
st_src_reg temp = get_temp(glsl_type::vec4_type);
- emit(ir, TGSI_OPCODE_MUL, st_dst_reg(temp), transform_y, op[0]);
- emit(ir, ir->operation == ir_unop_dFdy_fine ?
+ emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(temp), transform_y, op[0]);
+ emit_asm(ir, ir->operation == ir_unop_dFdy_fine ?
TGSI_OPCODE_DDY_FINE : TGSI_OPCODE_DDY, result_dst, temp);
break;
}
case ir_unop_frexp_sig:
- emit(ir, TGSI_OPCODE_DFRACEXP, result_dst, undef_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_DFRACEXP, result_dst, undef_dst, op[0]);
break;
case ir_unop_frexp_exp:
- emit(ir, TGSI_OPCODE_DFRACEXP, undef_dst, result_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_DFRACEXP, undef_dst, result_dst, op[0]);
break;
case ir_unop_noise: {
* place to do this is in the GL state tracker, not the poor
* driver.
*/
- emit(ir, TGSI_OPCODE_MOV, result_dst, st_src_reg_for_float(0.5));
+ emit_asm(ir, TGSI_OPCODE_MOV, result_dst, st_src_reg_for_float(0.5));
break;
}
case ir_binop_add:
- emit(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
+ emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
break;
case ir_binop_sub:
- emit(ir, TGSI_OPCODE_SUB, result_dst, op[0], op[1]);
+ emit_asm(ir, TGSI_OPCODE_SUB, result_dst, op[0], op[1]);
break;
case ir_binop_mul:
- emit(ir, TGSI_OPCODE_MUL, result_dst, op[0], op[1]);
+ emit_asm(ir, TGSI_OPCODE_MUL, result_dst, op[0], op[1]);
break;
case ir_binop_div:
if (result_dst.type == GLSL_TYPE_FLOAT || result_dst.type == GLSL_TYPE_DOUBLE)
assert(!"not reached: should be handled by ir_div_to_mul_rcp");
else
- emit(ir, TGSI_OPCODE_DIV, result_dst, op[0], op[1]);
+ emit_asm(ir, TGSI_OPCODE_DIV, result_dst, op[0], op[1]);
break;
case ir_binop_mod:
if (result_dst.type == GLSL_TYPE_FLOAT)
assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
else
- emit(ir, TGSI_OPCODE_MOD, result_dst, op[0], op[1]);
+ emit_asm(ir, TGSI_OPCODE_MOD, result_dst, op[0], op[1]);
break;
case ir_binop_less:
- emit(ir, TGSI_OPCODE_SLT, result_dst, op[0], op[1]);
+ emit_asm(ir, TGSI_OPCODE_SLT, result_dst, op[0], op[1]);
break;
case ir_binop_greater:
- emit(ir, TGSI_OPCODE_SLT, result_dst, op[1], op[0]);
+ emit_asm(ir, TGSI_OPCODE_SLT, result_dst, op[1], op[0]);
break;
case ir_binop_lequal:
- emit(ir, TGSI_OPCODE_SGE, result_dst, op[1], op[0]);
+ emit_asm(ir, TGSI_OPCODE_SGE, result_dst, op[1], op[0]);
break;
case ir_binop_gequal:
- emit(ir, TGSI_OPCODE_SGE, result_dst, op[0], op[1]);
+ emit_asm(ir, TGSI_OPCODE_SGE, result_dst, op[0], op[1]);
break;
case ir_binop_equal:
- emit(ir, TGSI_OPCODE_SEQ, result_dst, op[0], op[1]);
+ emit_asm(ir, TGSI_OPCODE_SEQ, result_dst, op[0], op[1]);
break;
case ir_binop_nequal:
- emit(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
+ emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
break;
case ir_binop_all_equal:
/* "==" operator producing a scalar boolean. */
st_dst_reg temp_dst = st_dst_reg(temp);
st_src_reg temp1 = st_src_reg(temp), temp2 = st_src_reg(temp);
- emit(ir, TGSI_OPCODE_SEQ, st_dst_reg(temp), op[0], op[1]);
+ emit_asm(ir, TGSI_OPCODE_SEQ, st_dst_reg(temp), op[0], op[1]);
/* Emit 1-3 AND operations to combine the SEQ results. */
switch (ir->operands[0]->type->vector_elements) {
temp_dst.writemask = WRITEMASK_Y;
temp1.swizzle = SWIZZLE_YYYY;
temp2.swizzle = SWIZZLE_ZZZZ;
- emit(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
+ emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
break;
case 4:
temp_dst.writemask = WRITEMASK_X;
temp1.swizzle = SWIZZLE_XXXX;
temp2.swizzle = SWIZZLE_YYYY;
- emit(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
+ emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
temp_dst.writemask = WRITEMASK_Y;
temp1.swizzle = SWIZZLE_ZZZZ;
temp2.swizzle = SWIZZLE_WWWW;
- emit(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
+ emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
}
temp1.swizzle = SWIZZLE_XXXX;
temp2.swizzle = SWIZZLE_YYYY;
- emit(ir, TGSI_OPCODE_AND, result_dst, temp1, temp2);
+ emit_asm(ir, TGSI_OPCODE_AND, result_dst, temp1, temp2);
} else {
- emit(ir, TGSI_OPCODE_SNE, st_dst_reg(temp), op[0], op[1]);
+ emit_asm(ir, TGSI_OPCODE_SNE, st_dst_reg(temp), op[0], op[1]);
/* After the dot-product, the value will be an integer on the
* range [0,4]. Zero becomes 1.0, and positive values become zero.
*/
st_src_reg sge_src = result_src;
sge_src.negate = ~sge_src.negate;
- emit(ir, TGSI_OPCODE_SGE, result_dst, sge_src, st_src_reg_for_float(0.0));
+ emit_asm(ir, TGSI_OPCODE_SGE, result_dst, sge_src, st_src_reg_for_float(0.0));
}
} else {
- emit(ir, TGSI_OPCODE_SEQ, result_dst, op[0], op[1]);
+ emit_asm(ir, TGSI_OPCODE_SEQ, result_dst, op[0], op[1]);
}
break;
case ir_binop_any_nequal:
st_src_reg temp = get_temp(native_integers ?
glsl_type::uvec4_type :
glsl_type::vec4_type);
- emit(ir, TGSI_OPCODE_SNE, st_dst_reg(temp), op[0], op[1]);
+ emit_asm(ir, TGSI_OPCODE_SNE, st_dst_reg(temp), op[0], op[1]);
if (native_integers) {
st_dst_reg temp_dst = st_dst_reg(temp);
temp_dst.writemask = WRITEMASK_Y;
temp1.swizzle = SWIZZLE_YYYY;
temp2.swizzle = SWIZZLE_ZZZZ;
- emit(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
+ emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
break;
case 4:
temp_dst.writemask = WRITEMASK_X;
temp1.swizzle = SWIZZLE_XXXX;
temp2.swizzle = SWIZZLE_YYYY;
- emit(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
+ emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
temp_dst.writemask = WRITEMASK_Y;
temp1.swizzle = SWIZZLE_ZZZZ;
temp2.swizzle = SWIZZLE_WWWW;
- emit(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
+ emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
}
temp1.swizzle = SWIZZLE_XXXX;
temp2.swizzle = SWIZZLE_YYYY;
- emit(ir, TGSI_OPCODE_OR, result_dst, temp1, temp2);
+ emit_asm(ir, TGSI_OPCODE_OR, result_dst, temp1, temp2);
} else {
/* After the dot-product, the value will be an integer on the
* range [0,4]. Zero stays zero, and positive values become 1.0.
*/
st_src_reg slt_src = result_src;
slt_src.negate = ~slt_src.negate;
- emit(ir, TGSI_OPCODE_SLT, result_dst, slt_src, st_src_reg_for_float(0.0));
+ emit_asm(ir, TGSI_OPCODE_SLT, result_dst, slt_src, st_src_reg_for_float(0.0));
}
}
} else {
- emit(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
+ emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
}
break;
GET_SWZ(op0_swizzle, 3),
GET_SWZ(op0_swizzle, 3),
GET_SWZ(op0_swizzle, 3));
- emit(ir, TGSI_OPCODE_OR, result_dst, accum, op[0]);
+ emit_asm(ir, TGSI_OPCODE_OR, result_dst, accum, op[0]);
accum = st_src_reg(result_dst);
accum.swizzle = dst_swizzle;
/* fallthrough */
GET_SWZ(op0_swizzle, 2),
GET_SWZ(op0_swizzle, 2),
GET_SWZ(op0_swizzle, 2));
- emit(ir, TGSI_OPCODE_OR, result_dst, accum, op[0]);
+ emit_asm(ir, TGSI_OPCODE_OR, result_dst, accum, op[0]);
accum = st_src_reg(result_dst);
accum.swizzle = dst_swizzle;
/* fallthrough */
GET_SWZ(op0_swizzle, 1),
GET_SWZ(op0_swizzle, 1),
GET_SWZ(op0_swizzle, 1));
- emit(ir, TGSI_OPCODE_OR, result_dst, accum, op[0]);
+ emit_asm(ir, TGSI_OPCODE_OR, result_dst, accum, op[0]);
break;
default:
assert(!"Unexpected vector size");
*/
st_src_reg slt_src = result_src;
slt_src.negate = ~slt_src.negate;
- emit(ir, TGSI_OPCODE_SLT, result_dst, slt_src, st_src_reg_for_float(0.0));
+ emit_asm(ir, TGSI_OPCODE_SLT, result_dst, slt_src, st_src_reg_for_float(0.0));
}
else {
/* Use SNE 0 if integers are being used as boolean values. */
- emit(ir, TGSI_OPCODE_SNE, result_dst, result_src, st_src_reg_for_int(0));
+ emit_asm(ir, TGSI_OPCODE_SNE, result_dst, result_src, st_src_reg_for_int(0));
}
}
break;
case ir_binop_logic_xor:
if (native_integers)
- emit(ir, TGSI_OPCODE_XOR, result_dst, op[0], op[1]);
+ emit_asm(ir, TGSI_OPCODE_XOR, result_dst, op[0], op[1]);
else
- emit(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
+ emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
break;
case ir_binop_logic_or: {
* instruction.
*/
assert(native_integers);
- emit(ir, TGSI_OPCODE_OR, result_dst, op[0], op[1]);
+ emit_asm(ir, TGSI_OPCODE_OR, result_dst, op[0], op[1]);
} else {
/* After the addition, the value will be an integer on the
* range [0,2]. Zero stays zero, and positive values become 1.0.
*/
glsl_to_tgsi_instruction *add =
- emit(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
+ emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
if (this->prog->Target == GL_FRAGMENT_PROGRAM_ARB) {
/* The clamping to [0,1] can be done for free in the fragment
* shader with a saturate if floats are being used as boolean values.
*/
st_src_reg slt_src = result_src;
slt_src.negate = ~slt_src.negate;
- emit(ir, TGSI_OPCODE_SLT, result_dst, slt_src, st_src_reg_for_float(0.0));
+ emit_asm(ir, TGSI_OPCODE_SLT, result_dst, slt_src, st_src_reg_for_float(0.0));
}
}
break;
* actual AND opcode.
*/
if (native_integers)
- emit(ir, TGSI_OPCODE_AND, result_dst, op[0], op[1]);
+ emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], op[1]);
else
- emit(ir, TGSI_OPCODE_MUL, result_dst, op[0], op[1]);
+ emit_asm(ir, TGSI_OPCODE_MUL, result_dst, op[0], op[1]);
break;
case ir_binop_dot:
} else {
/* sqrt(x) = x * rsq(x). */
emit_scalar(ir, TGSI_OPCODE_RSQ, result_dst, op[0]);
- emit(ir, TGSI_OPCODE_MUL, result_dst, result_src, op[0]);
+ emit_asm(ir, TGSI_OPCODE_MUL, result_dst, result_src, op[0]);
/* For incoming channels <= 0, set the result to 0. */
op[0].negate = ~op[0].negate;
- emit(ir, TGSI_OPCODE_CMP, result_dst,
+ emit_asm(ir, TGSI_OPCODE_CMP, result_dst,
op[0], result_src, st_src_reg_for_float(0.0));
}
break;
break;
case ir_unop_i2f:
if (native_integers) {
- emit(ir, TGSI_OPCODE_I2F, result_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_I2F, result_dst, op[0]);
break;
}
/* fallthrough to next case otherwise */
case ir_unop_b2f:
if (native_integers) {
- emit(ir, TGSI_OPCODE_AND, result_dst, op[0], st_src_reg_for_float(1.0));
+ emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], st_src_reg_for_float(1.0));
break;
}
/* fallthrough to next case otherwise */
* GLSL requires that int(bool) return 1 for true and 0 for false.
* This conversion is done with AND, but it could be done with NEG.
*/
- emit(ir, TGSI_OPCODE_AND, result_dst, op[0], st_src_reg_for_int(1));
+ emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], st_src_reg_for_int(1));
} else {
/* Booleans and integers are both stored as floats when native
* integers are disabled.
break;
case ir_unop_f2i:
if (native_integers)
- emit(ir, TGSI_OPCODE_F2I, result_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_F2I, result_dst, op[0]);
else
- emit(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
break;
case ir_unop_f2u:
if (native_integers)
- emit(ir, TGSI_OPCODE_F2U, result_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_F2U, result_dst, op[0]);
else
- emit(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
break;
case ir_unop_bitcast_f2i:
result_src = op[0];
result_src.type = GLSL_TYPE_FLOAT;
break;
case ir_unop_f2b:
- emit(ir, TGSI_OPCODE_SNE, result_dst, op[0], st_src_reg_for_float(0.0));
+ emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], st_src_reg_for_float(0.0));
break;
case ir_unop_d2b:
- emit(ir, TGSI_OPCODE_SNE, result_dst, op[0], st_src_reg_for_double(0.0));
+ emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], st_src_reg_for_double(0.0));
break;
case ir_unop_i2b:
if (native_integers)
- emit(ir, TGSI_OPCODE_USNE, result_dst, op[0], st_src_reg_for_int(0));
+ emit_asm(ir, TGSI_OPCODE_USNE, result_dst, op[0], st_src_reg_for_int(0));
else
- emit(ir, TGSI_OPCODE_SNE, result_dst, op[0], st_src_reg_for_float(0.0));
+ emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], st_src_reg_for_float(0.0));
break;
case ir_unop_trunc:
- emit(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
break;
case ir_unop_ceil:
- emit(ir, TGSI_OPCODE_CEIL, result_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_CEIL, result_dst, op[0]);
break;
case ir_unop_floor:
- emit(ir, TGSI_OPCODE_FLR, result_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_FLR, result_dst, op[0]);
break;
case ir_unop_round_even:
- emit(ir, TGSI_OPCODE_ROUND, result_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_ROUND, result_dst, op[0]);
break;
case ir_unop_fract:
- emit(ir, TGSI_OPCODE_FRC, result_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_FRC, result_dst, op[0]);
break;
case ir_binop_min:
- emit(ir, TGSI_OPCODE_MIN, result_dst, op[0], op[1]);
+ emit_asm(ir, TGSI_OPCODE_MIN, result_dst, op[0], op[1]);
break;
case ir_binop_max:
- emit(ir, TGSI_OPCODE_MAX, result_dst, op[0], op[1]);
+ emit_asm(ir, TGSI_OPCODE_MAX, result_dst, op[0], op[1]);
break;
case ir_binop_pow:
emit_scalar(ir, TGSI_OPCODE_POW, result_dst, op[0], op[1]);
case ir_unop_bit_not:
if (native_integers) {
- emit(ir, TGSI_OPCODE_NOT, result_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_NOT, result_dst, op[0]);
break;
}
case ir_unop_u2f:
if (native_integers) {
- emit(ir, TGSI_OPCODE_U2F, result_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_U2F, result_dst, op[0]);
break;
}
case ir_binop_lshift:
if (native_integers) {
- emit(ir, TGSI_OPCODE_SHL, result_dst, op[0], op[1]);
+ emit_asm(ir, TGSI_OPCODE_SHL, result_dst, op[0], op[1]);
break;
}
case ir_binop_rshift:
if (native_integers) {
- emit(ir, TGSI_OPCODE_ISHR, result_dst, op[0], op[1]);
+ emit_asm(ir, TGSI_OPCODE_ISHR, result_dst, op[0], op[1]);
break;
}
case ir_binop_bit_and:
if (native_integers) {
- emit(ir, TGSI_OPCODE_AND, result_dst, op[0], op[1]);
+ emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], op[1]);
break;
}
case ir_binop_bit_xor:
if (native_integers) {
- emit(ir, TGSI_OPCODE_XOR, result_dst, op[0], op[1]);
+ emit_asm(ir, TGSI_OPCODE_XOR, result_dst, op[0], op[1]);
break;
}
case ir_binop_bit_or:
if (native_integers) {
- emit(ir, TGSI_OPCODE_OR, result_dst, op[0], op[1]);
+ emit_asm(ir, TGSI_OPCODE_OR, result_dst, op[0], op[1]);
break;
}
}
else {
/* Relative/variable index into constant buffer */
- emit(ir, TGSI_OPCODE_USHR, st_dst_reg(index_reg), op[1],
+ emit_asm(ir, TGSI_OPCODE_USHR, st_dst_reg(index_reg), op[1],
st_src_reg_for_int(4));
cbuf.reladdr = ralloc(mem_ctx, st_src_reg);
memcpy(cbuf.reladdr, &index_reg, sizeof(index_reg));
const_offset % 16 / 4);
if (ir->type->base_type == GLSL_TYPE_BOOL) {
- emit(ir, TGSI_OPCODE_USNE, result_dst, cbuf, st_src_reg_for_int(0));
+ emit_asm(ir, TGSI_OPCODE_USNE, result_dst, cbuf, st_src_reg_for_int(0));
} else {
- emit(ir, TGSI_OPCODE_MOV, result_dst, cbuf);
+ emit_asm(ir, TGSI_OPCODE_MOV, result_dst, cbuf);
}
break;
}
case ir_triop_lrp:
/* note: we have to reorder the three args here */
- emit(ir, TGSI_OPCODE_LRP, result_dst, op[2], op[1], op[0]);
+ emit_asm(ir, TGSI_OPCODE_LRP, result_dst, op[2], op[1], op[0]);
break;
case ir_triop_csel:
if (this->ctx->Const.NativeIntegers)
- emit(ir, TGSI_OPCODE_UCMP, result_dst, op[0], op[1], op[2]);
+ emit_asm(ir, TGSI_OPCODE_UCMP, result_dst, op[0], op[1], op[2]);
else {
op[0].negate = ~op[0].negate;
- emit(ir, TGSI_OPCODE_CMP, result_dst, op[0], op[1], op[2]);
+ emit_asm(ir, TGSI_OPCODE_CMP, result_dst, op[0], op[1], op[2]);
}
break;
case ir_triop_bitfield_extract:
- emit(ir, TGSI_OPCODE_IBFE, result_dst, op[0], op[1], op[2]);
+ emit_asm(ir, TGSI_OPCODE_IBFE, result_dst, op[0], op[1], op[2]);
break;
case ir_quadop_bitfield_insert:
- emit(ir, TGSI_OPCODE_BFI, result_dst, op[0], op[1], op[2], op[3]);
+ emit_asm(ir, TGSI_OPCODE_BFI, result_dst, op[0], op[1], op[2], op[3]);
break;
case ir_unop_bitfield_reverse:
- emit(ir, TGSI_OPCODE_BREV, result_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_BREV, result_dst, op[0]);
break;
case ir_unop_bit_count:
- emit(ir, TGSI_OPCODE_POPC, result_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_POPC, result_dst, op[0]);
break;
case ir_unop_find_msb:
- emit(ir, TGSI_OPCODE_IMSB, result_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_IMSB, result_dst, op[0]);
break;
case ir_unop_find_lsb:
- emit(ir, TGSI_OPCODE_LSB, result_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_LSB, result_dst, op[0]);
break;
case ir_binop_imul_high:
- emit(ir, TGSI_OPCODE_IMUL_HI, result_dst, op[0], op[1]);
+ emit_asm(ir, TGSI_OPCODE_IMUL_HI, result_dst, op[0], op[1]);
break;
case ir_triop_fma:
/* In theory, MAD is incorrect here. */
if (have_fma)
- emit(ir, TGSI_OPCODE_FMA, result_dst, op[0], op[1], op[2]);
+ emit_asm(ir, TGSI_OPCODE_FMA, result_dst, op[0], op[1], op[2]);
else
- emit(ir, TGSI_OPCODE_MAD, result_dst, op[0], op[1], op[2]);
+ emit_asm(ir, TGSI_OPCODE_MAD, result_dst, op[0], op[1], op[2]);
break;
case ir_unop_interpolate_at_centroid:
- emit(ir, TGSI_OPCODE_INTERP_CENTROID, result_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_INTERP_CENTROID, result_dst, op[0]);
break;
case ir_binop_interpolate_at_offset:
- emit(ir, TGSI_OPCODE_INTERP_OFFSET, result_dst, op[0], op[1]);
+ emit_asm(ir, TGSI_OPCODE_INTERP_OFFSET, result_dst, op[0], op[1]);
break;
case ir_binop_interpolate_at_sample:
- emit(ir, TGSI_OPCODE_INTERP_SAMPLE, result_dst, op[0], op[1]);
+ emit_asm(ir, TGSI_OPCODE_INTERP_SAMPLE, result_dst, op[0], op[1]);
break;
case ir_unop_d2f:
- emit(ir, TGSI_OPCODE_D2F, result_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_D2F, result_dst, op[0]);
break;
case ir_unop_f2d:
- emit(ir, TGSI_OPCODE_F2D, result_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_F2D, result_dst, op[0]);
break;
case ir_unop_d2i:
- emit(ir, TGSI_OPCODE_D2I, result_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_D2I, result_dst, op[0]);
break;
case ir_unop_i2d:
- emit(ir, TGSI_OPCODE_I2D, result_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_I2D, result_dst, op[0]);
break;
case ir_unop_d2u:
- emit(ir, TGSI_OPCODE_D2U, result_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_D2U, result_dst, op[0]);
break;
case ir_unop_u2d:
- emit(ir, TGSI_OPCODE_U2D, result_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_U2D, result_dst, op[0]);
break;
case ir_unop_unpack_double_2x32:
case ir_unop_pack_double_2x32:
- emit(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
+ emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
break;
case ir_binop_ldexp:
if (ir->operands[0]->type->base_type == GLSL_TYPE_DOUBLE) {
- emit(ir, TGSI_OPCODE_DLDEXP, result_dst, op[0], op[1]);
+ emit_asm(ir, TGSI_OPCODE_DLDEXP, result_dst, op[0], op[1]);
} else {
assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
}
index_reg = get_temp(native_integers ?
glsl_type::int_type : glsl_type::float_type);
- emit(ir, TGSI_OPCODE_MUL, st_dst_reg(index_reg),
+ emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(index_reg),
this->result, st_src_reg_for_type(index_reg.type, element_size));
}
st_src_reg accum_reg = get_temp(native_integers ?
glsl_type::int_type : glsl_type::float_type);
- emit(ir, TGSI_OPCODE_ADD, st_dst_reg(accum_reg),
+ emit_asm(ir, TGSI_OPCODE_ADD, st_dst_reg(accum_reg),
index_reg, *src.reladdr);
index_reg = accum_reg;
l_src.swizzle = swizzle_for_size(type->vector_elements);
if (native_integers) {
- emit(ir, TGSI_OPCODE_UCMP, *l, *cond,
+ emit_asm(ir, TGSI_OPCODE_UCMP, *l, *cond,
cond_swap ? l_src : *r,
cond_swap ? *r : l_src);
} else {
- emit(ir, TGSI_OPCODE_CMP, *l, *cond,
+ emit_asm(ir, TGSI_OPCODE_CMP, *l, *cond,
cond_swap ? l_src : *r,
cond_swap ? *r : l_src);
}
} else {
- emit(ir, TGSI_OPCODE_MOV, *l, *r);
+ emit_asm(ir, TGSI_OPCODE_MOV, *l, *r);
}
l->index++;
r->index++;
*/
glsl_to_tgsi_instruction *inst, *new_inst;
inst = (glsl_to_tgsi_instruction *)this->instructions.get_tail();
- new_inst = emit(ir, inst->op, l, inst->src[0], inst->src[1], inst->src[2]);
+ new_inst = emit_asm(ir, inst->op, l, inst->src[0], inst->src[1], inst->src[2]);
new_inst->saturate = inst->saturate;
inst->dead_mask = inst->dst[0].writemask;
} else {
src = this->result;
for (i = 0; i < (unsigned int)size; i++) {
- emit(ir, TGSI_OPCODE_MOV, temp, src);
+ emit_asm(ir, TGSI_OPCODE_MOV, temp, src);
src.index++;
temp.index++;
ir->array_elements[i]->accept(this);
src = this->result;
for (int j = 0; j < size; j++) {
- emit(ir, TGSI_OPCODE_MOV, temp, src);
+ emit_asm(ir, TGSI_OPCODE_MOV, temp, src);
src.index++;
temp.index++;
ir->type->vector_elements,
GL_FLOAT,
&src.swizzle);
- emit(ir, TGSI_OPCODE_MOV, mat_column, src);
+ emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
mat_column.index++;
}
l.cond_mask = COND_TR;
for (i = 0; i < type_size(param->type); i++) {
- emit(ir, TGSI_OPCODE_MOV, l, r);
+ emit_asm(ir, TGSI_OPCODE_MOV, l, r);
l.index++;
r.index++;
}
}
/* Emit call instruction */
- call_inst = emit(ir, TGSI_OPCODE_CAL);
+ call_inst = emit_asm(ir, TGSI_OPCODE_CAL);
call_inst->function = entry;
/* Process out parameters. */
st_dst_reg l = st_dst_reg(this->result);
for (i = 0; i < type_size(param->type); i++) {
- emit(ir, TGSI_OPCODE_MOV, l, r);
+ emit_asm(ir, TGSI_OPCODE_MOV, l, r);
l.index++;
r.index++;
}
coord = get_temp(glsl_type::vec4_type);
coord_dst = st_dst_reg(coord);
coord_dst.writemask = (1 << ir->coordinate->type->vector_elements) - 1;
- emit(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
+ emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
}
if (ir->projector) {
if (opcode == TGSI_OPCODE_TEX) {
/* Slot the projector in as the last component of the coord. */
coord_dst.writemask = WRITEMASK_W;
- emit(ir, TGSI_OPCODE_MOV, coord_dst, projector);
+ emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, projector);
coord_dst.writemask = WRITEMASK_XYZW;
opcode = TGSI_OPCODE_TXP;
} else {
* projective divide now.
*/
coord_dst.writemask = WRITEMASK_W;
- emit(ir, TGSI_OPCODE_RCP, coord_dst, projector);
+ emit_asm(ir, TGSI_OPCODE_RCP, coord_dst, projector);
/* In the case where we have to project the coordinates "by hand,"
* the shadow comparator value must also be projected.
assert(!sampler_type->sampler_array);
tmp_dst.writemask = WRITEMASK_Z;
- emit(ir, TGSI_OPCODE_MOV, tmp_dst, this->result);
+ emit_asm(ir, TGSI_OPCODE_MOV, tmp_dst, this->result);
tmp_dst.writemask = WRITEMASK_XY;
- emit(ir, TGSI_OPCODE_MOV, tmp_dst, coord);
+ emit_asm(ir, TGSI_OPCODE_MOV, tmp_dst, coord);
}
coord_dst.writemask = WRITEMASK_XYZ;
- emit(ir, TGSI_OPCODE_MUL, coord_dst, tmp_src, coord_w);
+ emit_asm(ir, TGSI_OPCODE_MUL, coord_dst, tmp_src, coord_w);
coord_dst.writemask = WRITEMASK_XYZW;
coord.swizzle = SWIZZLE_XYZW;
cube_sc = get_temp(glsl_type::float_type);
cube_sc_dst = st_dst_reg(cube_sc);
cube_sc_dst.writemask = WRITEMASK_X;
- emit(ir, TGSI_OPCODE_MOV, cube_sc_dst, this->result);
+ emit_asm(ir, TGSI_OPCODE_MOV, cube_sc_dst, this->result);
cube_sc_dst.writemask = WRITEMASK_X;
}
else {
} else {
coord_dst.writemask = WRITEMASK_Z;
}
- emit(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
+ emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
coord_dst.writemask = WRITEMASK_XYZW;
}
}
if (ir->op == ir_txf_ms) {
coord_dst.writemask = WRITEMASK_W;
- emit(ir, TGSI_OPCODE_MOV, coord_dst, sample_index);
+ emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, sample_index);
coord_dst.writemask = WRITEMASK_XYZW;
} else if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXB ||
opcode == TGSI_OPCODE_TXF) {
/* TGSI stores LOD or LOD bias in the last channel of the coords. */
coord_dst.writemask = WRITEMASK_W;
- emit(ir, TGSI_OPCODE_MOV, coord_dst, lod_info);
+ emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, lod_info);
coord_dst.writemask = WRITEMASK_XYZW;
}
}
if (opcode == TGSI_OPCODE_TXD)
- inst = emit(ir, opcode, result_dst, coord, dx, dy);
+ inst = emit_asm(ir, opcode, result_dst, coord, dx, dy);
else if (opcode == TGSI_OPCODE_TXQ) {
if (ir->op == ir_query_levels) {
/* the level is stored in W */
- inst = emit(ir, opcode, st_dst_reg(levels_src), lod_info);
+ inst = emit_asm(ir, opcode, st_dst_reg(levels_src), lod_info);
result_dst.writemask = WRITEMASK_X;
levels_src.swizzle = SWIZZLE_WWWW;
- emit(ir, TGSI_OPCODE_MOV, result_dst, levels_src);
+ emit_asm(ir, TGSI_OPCODE_MOV, result_dst, levels_src);
} else
- inst = emit(ir, opcode, result_dst, lod_info);
+ inst = emit_asm(ir, opcode, result_dst, lod_info);
} else if (opcode == TGSI_OPCODE_TXF) {
- inst = emit(ir, opcode, result_dst, coord);
+ inst = emit_asm(ir, opcode, result_dst, coord);
} else if (opcode == TGSI_OPCODE_TXL2 || opcode == TGSI_OPCODE_TXB2) {
- inst = emit(ir, opcode, result_dst, coord, lod_info);
+ inst = emit_asm(ir, opcode, result_dst, coord, lod_info);
} else if (opcode == TGSI_OPCODE_TEX2) {
- inst = emit(ir, opcode, result_dst, coord, cube_sc);
+ inst = emit_asm(ir, opcode, result_dst, coord, cube_sc);
} else if (opcode == TGSI_OPCODE_TG4) {
if (is_cube_array && ir->shadow_comparitor) {
- inst = emit(ir, opcode, result_dst, coord, cube_sc);
+ inst = emit_asm(ir, opcode, result_dst, coord, cube_sc);
} else {
- inst = emit(ir, opcode, result_dst, coord, component);
+ inst = emit_asm(ir, opcode, result_dst, coord, component);
}
} else
- inst = emit(ir, opcode, result_dst, coord);
+ inst = emit_asm(ir, opcode, result_dst, coord);
if (ir->shadow_comparitor)
inst->tex_shadow = GL_TRUE;
l = st_dst_reg(current_function->return_reg);
for (i = 0; i < type_size(current_function->sig->return_type); i++) {
- emit(ir, TGSI_OPCODE_MOV, l, r);
+ emit_asm(ir, TGSI_OPCODE_MOV, l, r);
l.index++;
r.index++;
}
}
- emit(ir, TGSI_OPCODE_RET);
+ emit_asm(ir, TGSI_OPCODE_RET);
}
void
/* Convert the bool condition to a float so we can negate. */
if (native_integers) {
st_src_reg temp = get_temp(ir->condition->type);
- emit(ir, TGSI_OPCODE_AND, st_dst_reg(temp),
+ emit_asm(ir, TGSI_OPCODE_AND, st_dst_reg(temp),
condition, st_src_reg_for_float(1.0));
condition = temp;
}
condition.negate = ~condition.negate;
- emit(ir, TGSI_OPCODE_KILL_IF, undef_dst, condition);
+ emit_asm(ir, TGSI_OPCODE_KILL_IF, undef_dst, condition);
} else {
/* unconditional kil */
- emit(ir, TGSI_OPCODE_KILL);
+ emit_asm(ir, TGSI_OPCODE_KILL);
}
}
if_opcode = native_integers ? TGSI_OPCODE_UIF : TGSI_OPCODE_IF;
- if_inst = emit(ir->condition, if_opcode, undef_dst, this->result);
+ if_inst = emit_asm(ir->condition, if_opcode, undef_dst, this->result);
this->instructions.push_tail(if_inst);
visit_exec_list(&ir->then_instructions, this);
if (!ir->else_instructions.is_empty()) {
- emit(ir->condition, TGSI_OPCODE_ELSE);
+ emit_asm(ir->condition, TGSI_OPCODE_ELSE);
visit_exec_list(&ir->else_instructions, this);
}
- if_inst = emit(ir->condition, TGSI_OPCODE_ENDIF);
+ if_inst = emit_asm(ir->condition, TGSI_OPCODE_ENDIF);
}
assert(this->prog->Target == GL_GEOMETRY_PROGRAM_NV);
ir->stream->accept(this);
- emit(ir, TGSI_OPCODE_EMIT, undef_dst, this->result);
+ emit_asm(ir, TGSI_OPCODE_EMIT, undef_dst, this->result);
}
void
assert(this->prog->Target == GL_GEOMETRY_PROGRAM_NV);
ir->stream->accept(this);
- emit(ir, TGSI_OPCODE_ENDPRIM, undef_dst, this->result);
+ emit_asm(ir, TGSI_OPCODE_ENDPRIM, undef_dst, this->result);
}
glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
coord = st_src_reg(PROGRAM_INPUT, VARYING_SLOT_TEX0, glsl_type::vec2_type);
src0 = v->get_temp(glsl_type::vec4_type);
dst0 = st_dst_reg(src0);
- inst = v->emit(NULL, TGSI_OPCODE_TEX, dst0, coord);
+ inst = v->emit_asm(NULL, TGSI_OPCODE_TEX, dst0, coord);
inst->sampler_array_size = 1;
inst->tex_target = TEXTURE_2D_INDEX;
/* MAD colorTemp, colorTemp, scale, bias; */
scale = st_src_reg(PROGRAM_STATE_VAR, scale_p, GLSL_TYPE_FLOAT);
bias = st_src_reg(PROGRAM_STATE_VAR, bias_p, GLSL_TYPE_FLOAT);
- inst = v->emit(NULL, TGSI_OPCODE_MAD, dst0, src0, scale, bias);
+ inst = v->emit_asm(NULL, TGSI_OPCODE_MAD, dst0, src0, scale, bias);
}
if (pixel_maps) {
/* TEX temp.rg, colorTemp.rgba, texture[1], 2D; */
temp_dst.writemask = WRITEMASK_XY; /* write R,G */
- inst = v->emit(NULL, TGSI_OPCODE_TEX, temp_dst, src0);
+ inst = v->emit_asm(NULL, TGSI_OPCODE_TEX, temp_dst, src0);
inst->sampler.index = 1;
inst->sampler_array_size = 1;
inst->tex_target = TEXTURE_2D_INDEX;
/* TEX temp.ba, colorTemp.baba, texture[1], 2D; */
src0.swizzle = MAKE_SWIZZLE4(SWIZZLE_Z, SWIZZLE_W, SWIZZLE_Z, SWIZZLE_W);
temp_dst.writemask = WRITEMASK_ZW; /* write B,A */
- inst = v->emit(NULL, TGSI_OPCODE_TEX, temp_dst, src0);
+ inst = v->emit_asm(NULL, TGSI_OPCODE_TEX, temp_dst, src0);
inst->sampler.index = 1;
inst->sampler_array_size = 1;
inst->tex_target = TEXTURE_2D_INDEX;
v->samplers_used |= (1 << 1);
/* MOV colorTemp, temp; */
- inst = v->emit(NULL, TGSI_OPCODE_MOV, dst0, temp);
+ inst = v->emit_asm(NULL, TGSI_OPCODE_MOV, dst0, temp);
}
/* Now copy the instructions from the original glsl_to_tgsi_visitor into the
prog->InputsRead |= BITFIELD64_BIT(src_regs[i].index);
}
- newinst = v->emit(NULL, inst->op, inst->dst[0], src_regs[0], src_regs[1], src_regs[2]);
+ newinst = v->emit_asm(NULL, inst->op, inst->dst[0], src_regs[0], src_regs[1], src_regs[2]);
newinst->tex_target = inst->tex_target;
newinst->sampler_array_size = inst->sampler_array_size;
}
coord = st_src_reg(PROGRAM_INPUT, VARYING_SLOT_TEX0, glsl_type::vec2_type);
src0 = v->get_temp(glsl_type::vec4_type);
dst0 = st_dst_reg(src0);
- inst = v->emit(NULL, TGSI_OPCODE_TEX, dst0, coord);
+ inst = v->emit_asm(NULL, TGSI_OPCODE_TEX, dst0, coord);
inst->sampler.index = samplerIndex;
inst->sampler_array_size = 1;
inst->tex_target = TEXTURE_2D_INDEX;
src0.negate = NEGATE_XYZW;
if (st->bitmap.tex_format == PIPE_FORMAT_L8_UNORM)
src0.swizzle = SWIZZLE_XXXX;
- inst = v->emit(NULL, TGSI_OPCODE_KILL_IF, undef_dst, src0);
+ inst = v->emit_asm(NULL, TGSI_OPCODE_KILL_IF, undef_dst, src0);
/* Now copy the instructions from the original glsl_to_tgsi_visitor into the
* new visitor. */
prog->InputsRead |= BITFIELD64_BIT(src_regs[i].index);
}
- newinst = v->emit(NULL, inst->op, inst->dst[0], src_regs[0], src_regs[1], src_regs[2]);
+ newinst = v->emit_asm(NULL, inst->op, inst->dst[0], src_regs[0], src_regs[1], src_regs[2]);
newinst->tex_target = inst->tex_target;
newinst->sampler_array_size = inst->sampler_array_size;
}
if (!entry->bgn_inst) {
v->current_function = entry;
- entry->bgn_inst = v->emit(NULL, TGSI_OPCODE_BGNSUB);
+ entry->bgn_inst = v->emit_asm(NULL, TGSI_OPCODE_BGNSUB);
entry->bgn_inst->function = entry;
visit_exec_list(&entry->sig->body, v);
glsl_to_tgsi_instruction *last;
last = (glsl_to_tgsi_instruction *)v->instructions.get_tail();
if (last->op != TGSI_OPCODE_RET)
- v->emit(NULL, TGSI_OPCODE_RET);
+ v->emit_asm(NULL, TGSI_OPCODE_RET);
glsl_to_tgsi_instruction *end;
- end = v->emit(NULL, TGSI_OPCODE_ENDSUB);
+ end = v->emit_asm(NULL, TGSI_OPCODE_ENDSUB);
end->function = entry;
progress = GL_TRUE;
v->renumber_registers();
/* Write the END instruction. */
- v->emit(NULL, TGSI_OPCODE_END);
+ v->emit_asm(NULL, TGSI_OPCODE_END);
if (ctx->_Shader->Flags & GLSL_DUMP) {
_mesa_log("\n");
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