Daily bump.

diff --git a/contrib/ChangeLog b/contrib/ChangeLog
index 9b7e4a7691025afc7e7cea22123822a1828525c1..1efbbeeb8be48c2be279ea1dd02b5512ff1baedd 100644 (file)
--- a/contrib/ChangeLog
+++ b/contrib/ChangeLog
@@ -1,3 +1,8 @@
+2021-01-28  Eric Botcazou  <ebotcazou@adacore.com>
+
+       PR lto/85574
+       * compare-lto: Deal with PE-COFF executables specifically.
+
 2021-01-14  Martin Liska  <mliska@suse.cz>
 
        * mklog.py: Fix infinite loop for unsupported files.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 70b8f0aa0096605e463e68739a96a737376181ca..f0c0390ebb947ec2665fb1244331921d96ce590e 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,109 @@
+2021-01-28  Marek Polacek  <polacek@redhat.com>
+
+       PR c++/94775
+       * stor-layout.c (finalize_type_size): If we reset TYPE_USER_ALIGN in
+       the main variant, maybe reset it in its variants too.
+       * tree.c (check_base_type): Return true only if TYPE_USER_ALIGN match.
+       (check_aligned_type): Check if TYPE_USER_ALIGN match.
+
+2021-01-28  Christophe Lyon  <christophe.lyon@linaro.org>
+
+       PR target/98730
+       * config/arm/arm.c (arm_rtx_costs_internal): Adjust cost of vector
+       of constant zero for comparisons.
+
+2021-01-28  Michael Meissner  <meissner@linux.ibm.com>
+
+       * config/rs6000/rs6000.c (rs6000_mangle_decl_assembler_name): Add
+       support for mapping built-in function names for long double
+       built-in functions if long double is IEEE 128-bit.
+
+2021-01-28  Jonathan Wright  <jonathan.wright@arm.com>
+
+       * config/aarch64/aarch64-simd-builtins.def: Add [su]mlsl_n
+       builtin generator macros.
+       * config/aarch64/aarch64-simd.md (aarch64_<su>mlsl_n<mode>):
+       Define.
+       * config/aarch64/arm_neon.h (vmlsl_n_s16): Use RTL builtin
+       instead of inline asm.
+       (vmlsl_n_s32): Likewise.
+       (vmlsl_n_u16): Likewise.
+       (vmlsl_n_u32): Likewise.
+
+2021-01-28  Jonathan Wright  <jonathan.wright@arm.com>
+
+       * config/aarch64/aarch64-simd-builtins.def: Add [su]mlal_n
+       builtin generator macros.
+       * config/aarch64/aarch64-simd.md (aarch64_<su>mlal_n<mode>):
+       Define.
+       * config/aarch64/arm_neon.h (vmlal_n_s16): Use RTL builtin
+       instead of inline asm.
+       (vmlal_n_s32): Likewise.
+       (vmlal_n_u16): Likewise.
+       (vmlal_n_u32): Likewise.
+
+2021-01-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * config/aarch64/aarch64-simd-builtins.def (shrn2): Define
+       builtin.
+       * config/aarch64/aarch64-simd.md (aarch64_shrn2<mode>_insn_le):
+       Define.
+       (aarch64_shrn2<mode>_insn_be): Likewise.
+       (aarch64_shrn2<mode>): Likewise.
+       * config/aarch64/arm_neon.h (vshrn_high_n_s16): Reimlplement
+       using builtins.
+       (vshrn_high_n_s32): Likewise.
+       (vshrn_high_n_s64): Likewise.
+       (vshrn_high_n_u16): Likewise.
+       (vshrn_high_n_u32): Likewise.
+       (vshrn_high_n_u64): Likewise.
+
+2021-01-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * config/aarch64/aarch64-simd-builtins.def (shrn): Define
+       builtin.
+       * config/aarch64/aarch64-simd.md (aarch64_shrn<mode>_insn_le):
+       Define.
+       (aarch64_shrn<mode>_insn_be): Likewise.
+       (aarch64_shrn<mode>): Likewise.
+       * config/aarch64/arm_neon.h (vshrn_n_s16): Reimplement using
+       builtins.
+       (vshrn_n_s32): Likewise.
+       (vshrn_n_s64): Likewise.
+       (vshrn_n_u16): Likewise.
+       (vshrn_n_u32): Likewise.
+       (vshrn_n_u64): Likewise.
+       * config/aarch64/iterators.md (vn_mode): New mode attribute.
+
+2021-01-28  Richard Biener  <rguenther@suse.de>
+
+       PR rtl-optimization/80960
+       * dse.c (check_mem_read_rtx): Call get_addr on the
+       offsetted address.
+
+2021-01-28  Xionghu Luo  <luoxhu@linux.ibm.com>
+           David Edelsohn  <dje.gcc@gmail.com>
+
+       PR target/98799
+       * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
+       Don't generate VIEW_CONVERT_EXPR for fcode ALTIVEC_BUILTIN_VEC_INSERT
+       when -m32.
+       * config/rs6000/rs6000-protos.h (rs6000_expand_vector_set_var):
+       Delete.
+       * config/rs6000/rs6000.c (rs6000_expand_vector_set): Remove the
+       wrapper call rs6000_expand_vector_set_var for cleanup.  Call
+       rs6000_expand_vector_set_var_p9 and rs6000_expand_vector_set_var_p8
+       directly.
+       (rs6000_expand_vector_set_var): Delete.
+       (rs6000_expand_vector_set_var_p9): Make static.
+       (rs6000_expand_vector_set_var_p8): Make static.
+
+2021-01-28  Xing GUO  <higuoxing@gmail.com>
+
+       * common/config/riscv/riscv-common.c
+       (riscv_subset_list::parsing_subset_version): Fix -march option parsing
+       when `p` extension exists.
+
 2021-01-27  Vladimir N. Makarov  <vmakarov@redhat.com>
 
        PR rtl-optimization/97684

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 6f2e9366761e6446eca72edbccfb3dc03a20ce51..1cdaac431948dab81543b48c68c486d8b405d9c0 100644 (file)
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20210128
+20210129

diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog
index b57663dda60f8688557bb170e007662931047af3..fa67d1a783e665cd56166ece97064c06db4d8cec 100644 (file)
--- a/gcc/c-family/ChangeLog
+++ b/gcc/c-family/ChangeLog
@@ -1,3 +1,9 @@
+2021-01-28  Jakub Jelinek  <jakub@redhat.com>
+
+       * c.opt (-std=c++2a, -std=c++20, -std=gnu++2a, -std=gnu++20): Remove
+       draft from description.
+       (-std=c++2b): Fix a pasto, 2020 -> 2023.
+
 2021-01-26  Paul Fee  <paul.f.fee@gmail.com>
 
        * c-common.h (cxx_dialect): Add cxx23 as a dialect.

diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index 252bda6c0b9c4960748fc37e148bb22e9001fc82..144ff952d45ac4914a8278758f6839d43b7a4598 100644 (file)
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,28 @@
+2021-01-28  Jakub Jelinek  <jakub@redhat.com>
+
+       PR c++/98841
+       * typeck.c (build_x_indirect_ref): For *this, return current_class_ref.
+
+2021-01-28  Jakub Jelinek  <jakub@redhat.com>
+
+       PR c++/33661
+       PR c++/98847
+       * decl.c (cp_finish_decl): For register vars with asmspec in templates
+       call set_user_assembler_name and set DECL_HARD_REGISTER.
+       * pt.c (tsubst_expr): When instantiating DECL_HARD_REGISTER vars,
+       pass asmspec_tree to cp_finish_decl.
+
+2021-01-28  Nathan Sidwell  <nathan@acm.org>
+
+       PR c++/98770
+       * module.cc (trees_out::decl_value): Swap is_typedef & TYPE_NAME
+       check order.
+       (trees_in::decl_value): Do typedef frobbing only when installing
+       a new typedef, adjust is_matching_decl call.  Swap is_typedef
+       & TYPE_NAME check.
+       (trees_in::is_matching_decl): Add is_typedef parm. Adjust variable
+       names and deal with typedef checking.
+
 2021-01-27  Jason Merrill  <jason@redhat.com>
 
        PR c++/97874

diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index ec26cea2ebcefcf396738a6124a390dccec7383d..560250369e3d9cdfc35540f3d840b48d4ae02c92 100644 (file)
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,9 @@
+2021-01-28  Harald Anlauf  <anlauf@gmx.de>
+
+       PR fortran/86470
+       * trans.c (gfc_call_malloc): Allocate area of size 1 if passed
+       size is NULL (as documented).
+
 2021-01-27  Paul Thomas  <pault@gcc.gnu.org>
 
        PR fortran/93924

diff --git a/gcc/go/ChangeLog b/gcc/go/ChangeLog
index 8a9e2823daece00a0efda1f40f8df2ceb9125ca9..85bd3435a18c84c13644b91932e815236a3c060d 100644 (file)
--- a/gcc/go/ChangeLog
+++ b/gcc/go/ChangeLog
@@ -1,3 +1,8 @@
+2021-01-28  Ian Lance Taylor  <iant@golang.org>
+
+       * gospec.c (lang_specific_driver): Add -g if no debugging options
+       were passed.
+
 2021-01-15  Ian Lance Taylor  <iant@golang.org>
 
        * Make-lang.in (GO_OBJS): Add go/embed.o.

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index c985d48f797fa7d298a65ff6a80c80e4d08a82e1..37000934e92ab770b8cf241296fdb0a5ca8c210a 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,77 @@
+2021-01-28  Jakub Jelinek  <jakub@redhat.com>
+
+       PR c++/98841
+       * g++.dg/warn/effc5.C: New test.
+
+2021-01-28  Marek Polacek  <polacek@redhat.com>
+
+       PR c++/94775
+       * g++.dg/cpp0x/alignas19.C: New test.
+       * g++.dg/warn/Warray-bounds15.C: New test.
+
+2021-01-28  Christophe Lyon  <christophe.lyon@linaro.org>
+
+       PR target/98730
+       * gcc.target/arm/simd/vceqzq_p64.c: Update expected result.
+
+2021-01-28  David Edelsohn  <dje.gcc@gmail.com>
+
+       * gfortran.dg/ISO_Fortran_binding_18.c: Include
+       ../../../libgfortran/ISO_Fortran_binding.h rather than
+       ISO_Fortran_binding.h.
+
+2021-01-28  Michael Meissner  <meissner@linux.ibm.com>
+
+       * gcc.target/powerpc/float128-longdouble-math.c: New test.
+       * gcc.target/powerpc/float128-longdouble-stdio.c: New test.
+       * gcc.target/powerpc/float128-math.c: Adjust test for new name
+       being generated.  Add support for running test on power10.  Add
+       support for running if long double defaults to 64-bits.
+
+2021-01-28  Jakub Jelinek  <jakub@redhat.com>
+
+       PR c++/33661
+       PR c++/98847
+       * g++.target/i386/pr98847.C: New test.
+
+2021-01-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * gcc.target/aarch64/narrow_high-intrinsics.c: Fix shrn2 scan.
+
+2021-01-28  Nathan Sidwell  <nathan@acm.org>
+
+       PR c++/98770
+       * g++.dg/modules/pr98770_a.C: New.
+       * g++.dg/modules/pr98770_b.C: New.
+
+2021-01-28  Harald Anlauf  <anlauf@gmx.de>
+
+       PR fortran/86470
+       * gfortran.dg/gomp/pr86470.f90: New test.
+
+2021-01-28  Xionghu Luo  <luoxhu@linux.ibm.com>
+
+       PR target/98827
+       * gcc.target/powerpc/fold-vec-insert-char-p8.c: Adjust ilp32.
+       * gcc.target/powerpc/fold-vec-insert-char-p9.c: Likewise.
+       * gcc.target/powerpc/fold-vec-insert-double.c: Likewise.
+       * gcc.target/powerpc/fold-vec-insert-float-p8.c: Likewise.
+       * gcc.target/powerpc/fold-vec-insert-float-p9.c: Likewise.
+       * gcc.target/powerpc/fold-vec-insert-int-p8.c: Likewise.
+       * gcc.target/powerpc/fold-vec-insert-int-p9.c: Likewise.
+       * gcc.target/powerpc/fold-vec-insert-longlong.c: Likewise.
+       * gcc.target/powerpc/fold-vec-insert-short-p8.c: Likewise.
+       * gcc.target/powerpc/fold-vec-insert-short-p9.c: Likewise.
+       * gcc.target/powerpc/pr79251.p8.c: Likewise.
+       * gcc.target/powerpc/pr79251.p9.c: Likewise.
+       * gcc.target/powerpc/vsx-builtin-7.c: Likewise.
+       * gcc.target/powerpc/pr79251-run.c: Build and run with vsx
+       option.
+
+2021-01-28  Xing GUO  <higuoxing@gmail.com>
+
+       * gcc.target/riscv/attribute-18.c: New test.
+
 2021-01-27  Harris Snyder  <hsnyder@structura.bio>
 
        * gfortran.dg/ISO_Fortran_binding_18.c: New test.

diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 1d976faaafe82f97c45d015cb505e48371c39053..e7b7ed0c7ee46918b54580c041a1a6740da9c34c 100644 (file)
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,21 @@
+2021-01-28  Jonathan Wakely  <jwakely@redhat.com>
+
+       * include/experimental/bits/numeric_traits.h: Update copyright
+       dates.
+       * include/experimental/bits/simd.h: Likewise.
+       * include/experimental/bits/simd_builtin.h: Likewise.
+       * include/experimental/bits/simd_converter.h: Likewise.
+       * include/experimental/bits/simd_detail.h: Likewise.
+       * include/experimental/bits/simd_fixed_size.h: Likewise.
+       * include/experimental/bits/simd_math.h: Likewise.
+       * include/experimental/bits/simd_neon.h: Likewise.
+       * include/experimental/bits/simd_ppc.h: Likewise.
+       * include/experimental/bits/simd_scalar.h: Likewise.
+       * include/experimental/bits/simd_x86.h: Likewise.
+       * include/experimental/bits/simd_x86_conversions.h: Likewise.
+       * include/experimental/simd: Likewise.
+       * testsuite/experimental/simd/*: Likewise.
+
 2021-01-27  Jonathan Wakely  <jwakely@redhat.com>
 
        * doc/xml/manual/status_cxx2017.xml: Replace invalid entity.