projects / litex.git / commitdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: 7fa1cd7)
pipistrello: rename sdram->ddram
authorRobert Jordens <jordens@gmail.com>
Thu, 19 Mar 2015 17:47:54 +0000 (18:47 +0100)
committerSebastien Bourdeauducq <sb@m-labs.hk>
Thu, 19 Mar 2015 17:48:22 +0000 (18:48 +0100)
mibuild/platforms/pipistrello.py patch | blob | history

diff --git a/mibuild/platforms/pipistrello.py b/mibuild/platforms/pipistrello.py
index dc9bebd4209487a7f760e6ea5a47c3a9cdc985af..65e8d1067b626934f6038cd6cf6966d6435b8c83 100644 (file)
--- a/mibuild/platforms/pipistrello.py
+++ b/mibuild/platforms/pipistrello.py
@@ -97,13 +97,13 @@ _io = [
                IOStandard("LVTTL")
        ),
 
-       ("sdram_clock", 0,
+       ("ddram_clock", 0,
                Subsignal("p", Pins("G3")),
                Subsignal("n", Pins("G1")),
                IOStandard("MOBILE_DDR")
        ),
 
-       ("sdram", 0,
+       ("ddram", 0,
                Subsignal("a", Pins("J7 J6 H5 L7 F3 H4 H3 H6 D2 D1 F4 D3 G6")),
                Subsignal("ba", Pins("F2 F1")),
                Subsignal("cke", Pins("H7")),