# Increasing area efficiency and reducing resource utilisation for the Power ISA
+originally posted at: <https://lists.libre-soc.org/pipermail/libre-soc-dev/2022-February/004505.html>
+
in between attempting to compile microwatt and Libre-SOC for an 85k LUT4 FPGA which took 4 hours (and then did not run), i decided to see if, in Libre-SOC's HDL, what level of resource reduction could be achieved by going to 32 bit ALUs and register files.
the difference was an astounding 1.4 to 1.